US7669036B2 - Direct path monitoring by primary processor to each status register in pipeline chained secondary processors for task allocation via downstream communication - Google Patents
Direct path monitoring by primary processor to each status register in pipeline chained secondary processors for task allocation via downstream communication Download PDFInfo
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- US7669036B2 US7669036B2 US11/763,377 US76337707A US7669036B2 US 7669036 B2 US7669036 B2 US 7669036B2 US 76337707 A US76337707 A US 76337707A US 7669036 B2 US7669036 B2 US 7669036B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
- G06F15/17368—Indirect interconnection networks non hierarchical topologies
- G06F15/17375—One dimensional, e.g. linear array, ring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30094—Condition code generation, e.g. Carry, Zero flag
Definitions
- the present disclosure relates generally to the field of multi-processor systems and, more specifically, to techniques for resource management in multi-processor systems having a primary processor and pipelined secondary processors.
- a multi-processor system typically includes a primary processor administering a plurality of pipelined (i.e., connected in series) processors or co-processors, which are collectively referred to herein as secondary processors. In some applications, master-slave relationship may be formed between the primary processor and secondary processors.
- Such multi-processor systems may be used, for example, for processing of large amounts of video data or rendering graphics, among other computationally intensive applications.
- instructions and, occasionally, data blocks are forwarded by the primary or a respective intermediate secondary processor downstream to the adjacent secondary processor, and acknowledgements confirming completion of particular tasks (i.e., task status data) are communicated by the secondary processors upstream to the primary processor.
- the primary processor assigns new tasks to the secondary processors or re-allocates computational and memory resources in the system upon receipt of acknowledgements that the preceding tasks have been completed.
- At least one secondary processor is provided with a register containing status information for tasks executed by that secondary processor.
- the register is directly accessible by the primary processor via a dedicated data port of the secondary processor and a bus connecting the port to the primary processor.
- the register may be formed in a portion of a system memory that is directly accessible by the primary processor.
- the status information from intermediate secondary processors bypasses the upstream secondary processors and, as such, may be available to the primary processor in a real time.
- the disclosed techniques are used for managing computational and memory resources in multi-processor systems of wireless communication devices during execution of video applications, such as processing of video data or rendering graphics.
- FIG. 1 shows a block diagram of an exemplary multi-processor system.
- FIG. 2 shows a high-level block diagram of an exemplary pipelined processor of the system of FIG. 1 .
- FIG. 3 shows a flow diagram of a method for managing computational and memory resources in the system of FIG. 1 .
- exemplary is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.
- FIG. 1 depicts a block diagram of an exemplary multi-processor system 100 in accordance with one embodiment of the present invention.
- the system 100 may be used for processing video data and/or rendering graphics, among other computationally intensive data processing applications.
- the system 100 is a portion of a graphics processing unit (GPU) of a wireless communication apparatus, such as a cellular phone, a video game console, a personal digital assistant (PDA), a laptop computer, an audio/video-enabled device (e.g., video-enabled MP3 player), and the like.
- GPU graphics processing unit
- PDA personal digital assistant
- MP3 player an audio/video-enabled device
- the GPU may be compliant, for example, with a document “OpenVG Specification, Version 1.0,” Jul. 28, 2005, which is publicly available. This document is a standard for 2D vector graphics suitable for handheld and mobile devices, such as cellular phones and other referred to above wireless communication apparatuses. Additionally, the GPU 402 may also be compliant with OpenGL2.0, OpenGL ES2.0, or D3D9.0 graphics standards.
- the system 100 illustratively includes a primary processor 110 , a plurality of pipelined secondary processors 120 1 - 120 K , a memory 130 , an optional hardware graphics core 106 , a memory bus 132 , an acknowledgements bus 140 , and system interfaces 102 , 126 1 - 126 K , and 107 , where K is an integer and K ⁇ 2.
- the primary processor 110 and the secondary processors 120 1 - 120 K are interconnected using the system interfaces 126 1 - 126 K , and the secondary processor is connected to the hardware graphics core 106 using the system interface 107 , respectively.
- at least one of the secondary processors 120 1 - 120 K may be a portion of the hardware graphics core 106 or, alternatively, perform functions of the hardware graphics core 106 .
- the primary processor 110 , the pipelined secondary processors 120 1 - 120 K , and hardware graphics core 106 may be formed on a single integrated circuit (IC). Such IC may be a portion of, for example, a system-on-chip (SoC) integrated circuit device of a wireless communication apparatus. Alternatively, the primary processor 110 and at least one of the secondary processors 120 1 - 120 K or the hardware graphics core 106 or portions thereof may be formed on separate ICs.
- SoC system-on-chip
- each of the system interfaces 102 , 126 1 - 126 K , and 107 includes a command bus and, optionally, at least portions of data or address busses (not shown).
- the primary processor 110 and secondary processors 120 1 - 120 K may also include sub-processors, internal memories, peripheral devices, support circuits, and the like elements, which are collectively referred to herein as modules 115 and 120 1 - 120 K , respectively.
- the primary processor 110 comprises an input/output (I/O) module 118 including an input buffer (IB) 112 and an output buffer (OB) 114 .
- each of the secondary processors 120 1 - 120 K comprises a respective input/output (I/O) module 128 including an input buffer 122 and an output buffer 124 .
- the I/O modules 118 and 120 1 - 120 K facilitate communications within the system 100 or to/from the system 100 .
- an input buffer 122 of a preceding (i.e., upstream) secondary processor 120 is connected to an output buffer 124 of the adjacent downstream secondary processor.
- an input buffer 122 2 of a secondary processor 120 2 is connected, via a system interface 126 2 , to an output buffer 124 1 of a secondary processor 120 1 .
- an output buffer 124 2 of the secondary processor 120 2 is connected, via a system interface 126 3 , to an input buffer 122 3 of a secondary processor 120 3 (not shown).
- the primary processor 110 may be connected to at least one of a remote processor, a network, or a user controls means, which are collectively shown as a means 104 .
- the memory 130 generally includes a memory bank 111 of the primary processor 110 , memory banks 121 1 - 121 K of the respective the secondary processors 120 1 - 120 K , and a memory bank 109 of the hardware graphics core 106 .
- these memory banks together, form a shared memory block 134 , which is accessible by the primary and secondary processors via a branch 131 (shown in phantom) of the memory bus 132 .
- the input and output buffers 124 may contain additional references (pointers) to memory space jointly used by the respective secondary processors 120 .
- the secondary processors 120 1 - 120 K and the hardware graphics core 106 include respective status registers 142 1 - 142 K+1 and data ports 144 1 - 144 K+1 , and the primary processor 110 includes an input port 146 .
- the status registers 141 1 - 142 K+1 contain status information for tasks executed by the corresponding secondary processors 120 1 - 120 K and the hardware graphics core 106 .
- the hardware graphics core 106 may include the status registers 142 and the data ports 144 .
- the data ports 144 1 - 144 K+1 and the input port 146 are selectively coupled to the acknowledgements bus 140 .
- the primary processor 110 may directly access (i.e., read content of) the status registers 142 .
- the acknowledgements bus 140 may be implemented as a direct input-output interface, for example, direct port or serial data input-output interface.
- the primary processor 110 may directly access the status registers 142 via a link 147 (shown in phantom) coupling the I/O module 118 to the acknowledgements bus 140 .
- the status registers 142 may be accessed by remote processors (not shown), for example, processors monitoring performance of or debugging the system 100 .
- the respective registers 142 may be formed (shown in phantom) in the memory banks 121 1 - 121 K and 109 .
- the registers 142 may be associated with the shared memory block 134 .
- the memory bus 132 provides the primary processor 110 with a direct access to contents of at least the registers 142 .
- FIG. 2 depicts a high-level block diagram of an exemplary pipelined secondary processor 120 of the system 100 of FIG. 1 in accordance with one embodiment of the present invention.
- the secondary processor 120 may be fabricated as a single IC, a portion thereof, or include several ICs.
- the secondary processor 120 may, for example, be a portion of a multi-processor GPU of a wireless communication apparatus, among other mobile or stationary video-enabled devices, as well as a portion of a networked server having architecture adapted for large-scale graphics processing.
- the secondary processor 120 includes a processing core 210 , a program controller 220 , a memory module 230 , digital signal processing (DSP) circuits 240 comprising a plurality of arithmetic-logic units (ALUs) 242 , the I/O module 128 , the status register 142 , and the data port 144 .
- DSP digital signal processing
- the status register 142 may be a portion of the memory module 230 .
- the memory module 230 includes a program memory 232 , which contains one or more software modules that, in operation, define a content of the status register 142 and, via the data port 144 , facilitate accessibility of the content by the primary processor 110 or other authorized user, as discussed above in reference to FIG. 1 .
- FIG. 3 shows a flow diagram of a method 300 for managing computational and memory resources in the system 100 of FIG. 1 in accordance with one embodiment of the present invention.
- method steps of the method 300 are performed in the depicted order or at least two of these steps or portions thereof (e.g., steps 330 and 340 ) may be performed contemporaneously or in parallel.
- steps 330 and 340 may be performed contemporaneously or in parallel.
- the status registers 142 and data ports 144 are formed in the pipelined secondary processors 120 and the optional hardware graphics core 106 or the memory 130 of the multi-processor system 100 , as discussed above in reference to FIG. 1 . Contents of the status registers 142 are directly accessible by the primary processor 110 of system 100 .
- secondary processors 120 identify when particular tasks assigned or monitored by the primary processor 110 are completed. Upon completion of such a task, the corresponding status information is entered, in a pre-determined data format, in the status register 142 of the respective secondary processor 120 .
- the status information generally represents an acknowledgement, or confirmation, that the currently performed task is finished and, as such, the secondary processor and its computational and memory resources are available for the next task, as well as any resources of the primary processor that must be retained until completion of the task.
- such tasks may include repetitive cycles of processing graphics primitives, vertex buffer objects (VOBs), rendering video frames, and the like.
- the primary processor 110 selectively accesses the status registers 142 and, with a pre-determined periodicity, acquires their contents.
- the status information from a pipelined secondary processor 120 bypasses upstream intermediate processors and becomes available to the primary processor 110 immediately upon completion of the respective task, i.e., in a real time.
- the status registers 142 formed in the memory banks 121 1 - 121 K and 109 may directly be accessed by the primary processor 110 via the memory bus 130 .
- the primary processor 110 analyzes the status information acquired from the status registers 142 and, in operation, manages computational and/or memory resources of the multi-processor system 100 based on that information.
- the primary processor 110 may allocate or re-allocate data between the respective memory blocks 111 , 121 1 - 121 K , and 109 , selectively assign to or initiate new tasks in the respective secondary processors 120 or the hardware graphics core 106 , and the like.
- the method 300 may be implemented in hardware, software, firmware, or any combination thereof in a form of a computer program product comprising one or more computer-executable instructions.
- the computer program product may be stored on or transmitted using a computer-readable medium, which includes computer storage medium and computer communication medium.
- the term “computer storage medium” refers herein to any medium adapted for storing the instructions that cause the computer to execute the method.
- the computer storage medium may comprise solid-sate memory devices, including electronic memory devices (e.g., RAM, ROM, EEPROM, and the like), optical memory devices (e.g., compact discs (CD), digital versatile discs (DVD), and the like), or magnetic memory devices (e.g., hard drives, flash drives, tape drives, and the like), or other memory devices adapted to store the computer program product, or a combination of such memory devices.
- the term “computer communication medium” refers herein to any physical interface adapted to transmit the computer program product from one place to another using for example, a modulated carrier wave, an optical signal, a DC or AC current, and the like means.
- the computer communication medium may comprise twisted wire pairs, printed or flat cables, coaxial cables, fiber-optic cables, digital subscriber lines (DSL), or other wired, wireless, or optical serial or parallel interfaces, or a combination thereof.
- aspects of the present invention are illustratively described within the context of the processors of a multi-processor graphics pipeline. It will be appreciated by those skilled in the art that the invention may also be utilized within the context of other multi-processor systems having pipelined processors/co-processors, which are administered by one or more supervisory processor. Management of computational or memory resources in such systems using the techniques discussed above in reference to FIGS. 1-3 has been contemplated and is within the scope of the present invention.
- the invention may be used in cellular phones, video game consoles, PDAs, laptop computers, MP3 players and other graphics-enabled mobile or stationary devices having multi-processor architectures.
Abstract
Description
Claims (31)
Priority Applications (6)
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US11/763,377 US7669036B2 (en) | 2007-06-14 | 2007-06-14 | Direct path monitoring by primary processor to each status register in pipeline chained secondary processors for task allocation via downstream communication |
DE602008005671T DE602008005671D1 (en) | 2007-06-14 | 2008-03-31 | Resource management in multiprocessor systems |
EP08006412A EP2003548B1 (en) | 2007-06-14 | 2008-03-31 | Resource management in multi-processor system |
AT08006412T ATE503222T1 (en) | 2007-06-14 | 2008-03-31 | RESOURCE MANAGEMENT IN MULTI-PROCESSOR SYSTEMS |
PCT/US2008/066453 WO2008154552A1 (en) | 2007-06-14 | 2008-06-10 | Resource management in multi-processor system |
TW097122254A TW200907699A (en) | 2007-06-14 | 2008-06-13 | Resource management in multi-processor system |
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EP2003548B1 (en) | 2011-03-23 |
DE602008005671D1 (en) | 2011-05-05 |
WO2008154552A1 (en) | 2008-12-18 |
TW200907699A (en) | 2009-02-16 |
EP2003548A1 (en) | 2008-12-17 |
US20080313380A1 (en) | 2008-12-18 |
ATE503222T1 (en) | 2011-04-15 |
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