US7538596B2 - Low distortion quadrature mixer and method therefor - Google Patents
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- US7538596B2 US7538596B2 US10/853,473 US85347304A US7538596B2 US 7538596 B2 US7538596 B2 US 7538596B2 US 85347304 A US85347304 A US 85347304A US 7538596 B2 US7538596 B2 US 7538596B2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1441—Balanced arrangements with transistors using field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1458—Double balanced arrangements, i.e. where both input signals are differential
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1491—Arrangements to linearise a transconductance stage of a mixer arrangement
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/16—Multiple-frequency-changing
- H03D7/165—Multiple-frequency-changing at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
- H03D2200/0001—Circuit elements of demodulators
- H03D2200/0033—Current mirrors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
- H03D2200/0041—Functional aspects of demodulators
- H03D2200/0043—Bias and operating point
Definitions
- the present invention generally relates to frequency conversion circuits, and more particularly to mixers.
- Radio frequency (RF) receivers are used in a wide variety of applications such as television, cellular telephones, pagers, global positioning system (GPS) receivers, cable modems, cordless phones, satellite radio receivers, and the like.
- RF receiver One common type of RF receiver is the so-called superheterodyne receiver.
- a superheterodyne receiver mixes the desired data-carrying signal with the output of tunable oscillator to produce an output at a fixed intermediate frequency (IF).
- IF intermediate frequency
- the fixed IF signal can then be conveniently filtered and converted back down to baseband for further processing.
- a superheterodyne receiver requires one or more mixing steps.
- a superheterodyne receiver is a receiver that mixes the desired data-carrying signal with the output of tunable oscillator to produce an output at a fixed intermediate frequency (IF).
- the fixed IF signal can then be conveniently filtered and converted back down to baseband for further processing.
- Superheterodyne receivers are useful in a wide variety of applications in which the desired channel can occur within a wide band of frequencies, such as AM and FM radio, satellite radio, etc.
- CMOS complementary metal-oxide-semiconductor
- CMOS complementary metal-oxide-semiconductor
- a conventional CMOS mixer is formed by a local oscillator (LO) and a multiplier circuit.
- the multiplier circuit converts an input voltage conveying the signal to be mixed into a current signal.
- a portion of the multiplier known as a chopper circuit selectively diverts the current signal based on clock signals output by the LO.
- the LO is usually laid out as a block on an adjacent part of the IC from the multiplier.
- the clock signals are then provided to the chopper switches using conductors such as metal lines.
- the chopping process distorts the output signal because the transistors cannot be perfectly matched.
- the signals are usually mixed with both an in-phase LO signal and a quadrature LO signal to form an in-phase mixed signal and a quadrature mixed signal.
- the transistors in the in-phase mixer and the quadrature mixer will also typically not track each other so that when they are recombined at baseband the image component will not perfectly cancel out, resulting in distortion of the output signal. What is needed is a mixer that has lower distortion than such known mixers.
- a mixer in one form includes an input amplifier and a barrel shifter.
- the input amplifier has an input for receiving an input signal, and first through fourth output terminals for respectively providing first through fourth current signals.
- the barrel shifter has first through fourth input terminals for respectively receiving the first through fourth current signals, first through fourth control terminals for respectively receiving first through fourth clock signals, and first through fourth output terminals for respectively providing positive and negative in-phase output signals and positive and negative quadrature output signals.
- a mixer in another form, includes an input amplifier and a chopper circuit.
- the input amplifier receives an input signal and provides a plurality of input current signals in response thereto.
- the chopper circuit is coupled to the input amplifier, and receives a plurality of phases of a local oscillator signal for selectively switching the plurality of input current signals in response to the plurality of phases of the local oscillator signal to provide both an in-phase output current signal and a quadrature output current signal to corresponding ones of a plurality of nodes.
- the chopper circuit forms at least one of the in-phase output current signal and the quadrature output current signal by selectively switching all of the plurality of input current signals to a respective node.
- a method for mixing a signal from a first frequency to a second frequency.
- An input signal is converted into first through fourth input current signals.
- First through fourth clock signals are generated in response to phases of a local oscillator signal.
- the first through fourth input current signals are selectively switched to first through fourth output terminals, respectively, in response to the first clock signal, to the second, third, fourth, and first output terminals, respectively, in response to the second clock signal, to the third, fourth, first, and second output terminals, respectively, in response to the third clock signal, and to the fourth, first, second, and third output terminals, respectively, in response to the fourth clock signal.
- a second mixer for use in a receiver comprising a first mixer, a first filter, a second mixer, and a second filter.
- the first mixer has an input for receiving an RF signal, and an output for providing an intermediate frequency (IF) signal.
- the first filter has an input for receiving the IF signal, and an output for providing a filtered IF signal.
- the second mixer has an input for receiving the filtered IF signal, and an output for providing a baseband signal.
- the second filter having an input for receiving the baseband signal, and an output for providing a filtered baseband signal.
- the second mixer includes an input amplifier and a chopper circuit. The input amplifier receives the filtered IF signal and provides a plurality of input current signals in response thereto.
- the chopper circuit is coupled to the input amplifier and receives a plurality of phases of a local oscillator signal for selectively switching the plurality of input current signals in response to a plurality of phases of a local oscillator signal to provide both an in-phase output current signal and a quadrature output current signal to corresponding ones of a plurality of nodes.
- the chopper circuit forms at least one of the in-phase output current signal and the quadrature output current signal by selectively switching all of the plurality of input current signals to a respective node.
- a mixer in yet another form includes a local oscillator, an input amplifier, a barrel shifter, and a load circuit.
- the local oscillator has a plurality of output terminals for providing first through fourth phase clock signals.
- the input amplifier has a first input terminal for receiving a positive input signal of a differential signal pair, a second input terminal for receiving a negative input signal of the differential signal pair, and first through fourth output terminals for respectively providing positive and negative input current signals of first and second differential current signal pairs.
- the barrel shifter has first through fourth input terminals respectively coupled to the first through fourth output terminals of the input amplifier, first through fourth control input terminals coupled to the local oscillator for respectively receiving the first through fourth phase clock signals, and first through fourth output terminals for providing positive and negative in-phase output current signals and positive and negative quadrature output current signals.
- the load circuit is coupled to the first through fourth output terminals of the barrel shifter for providing positive and negative in-phase output voltages and positive and negative quadrature output voltages respectively in response to the positive and negative in-phase output current signals and the positive and negative quadrature output current signals.
- FIG. 1 illustrates in partial block diagram and partial schematic form a radio receiver according to the present invention
- FIG. 2 illustrates in schematic form a portion of a mixer known in the prior art
- FIG. 3 illustrates in schematic form a portion of another mixer known in the prior art
- FIG. 4 illustrates in partial block diagram and partial schematic the mixer of FIG. 1 ;
- FIG. 5 illustrates a timing diagram for timing signals associated with the mixer of FIG. 4 ;
- FIG. 6 illustrates in partial block diagram and partial schematic the multiplier of the mixer of FIG. 1 ;
- FIG. 7 illustrates in schematic form the barrel shifter of FIG. 6 .
- FIG. 1 illustrates in partial block diagram and partial schematic form a radio receiver 100 according to the present invention.
- Receiver 100 is a dual-superheterodyne receiver that includes generally an antenna 102 , a low noise amplifier labeled “LNA” 104 , an RF to IF mixer 106 , a bandpass filter 112 , image rejecting mixer 114 , a programmable gain amplifier labeled “PGA” 120 , and a lowpass filter 122 .
- Amplifier 104 has an input terminal connected to antenna 102 , and an output terminal, and amplifies a broadband signal received on antenna 102 to provide an amplified signal to the output terminal thereof.
- Mixer 106 mixes the amplified signal to IF as follows.
- Mixer 106 includes a multiplier 108 and a tunable oscillator 110 .
- Multiplier 108 has a first input terminal connected to the output terminal of amplifier 104 , a second input terminal, and an output terminal.
- Tunable oscillator 110 has a tuning input terminal and an output terminal that provides an RF local oscillator (LO) signal.
- the RF LO signal is selected by the tuning input to have a frequency such that a desired channel is mixed from RF to a selected IF, which is also the center frequency of bandpass filter 112 .
- Bandpass filter 112 has an input terminal connected to the output terminal of multiplier 108 , and an output terminal for providing an output signal with significant signal energy in a passband centered around the chosen IF, and with significant attenuation of signal energy in a stopband outside the passband.
- Image rejecting mixer 114 includes a multiplier 116 and an oscillator 118 .
- Multiplier 116 has a first input terminal connected to the output terminal of bandpass filter 112 , a second input terminal, and an output terminal.
- Multiplier 114 further includes a polyphase filter for rejecting an image frequency, as will be described more fully below.
- Oscillator 118 provides an IF LO signal at an output terminal thereof.
- the IF LO signal is selected to have an output frequency chosen to mix the selected IF signal to baseband, and multiplier 116 thus provides the output signal thereof at baseband.
- Amplifier 120 is provided to amplify this signal to a desired level, and has an input terminal connected to the output terminal of multiplier 116 , and an output terminal.
- Filter 122 has an input terminal connected to the output terminal of amplifier 120 , and an output terminal for providing an output signal of receiver 100 labeled “BASEBAND OUT”.
- Receiver 100 is a dual-superheterodyne receiver with an image rejecting mixer.
- image rejecting mixer 114 preferably uses a polyphase filter, not shown in FIG. 1 , such as the one described in copending application Ser. No. 10/814,615.
- the design of the oscillator 116 and multiplier 118 facilitates the image rejecting function of mixer 114 by producing differential in-phase and quadrature baseband signals with lower distortion due to improved phase clock accuracy and reduced susceptibility to gain mismatch.
- FIG. 2 illustrates in schematic form a portion 200 of a mixer known in the prior art.
- Mixer 200 includes three N-channel metal-oxide-semiconductor (MOS) transistors 202 , 204 , and 206 .
- MOS metal-oxide-semiconductor
- Transistor 202 has a drain, a gate for receiving an input signal labeled “IF”, and a source connected to a ground potential, typically at zero volts.
- Transistor 204 has a drain for providing a positive output current signal labeled “P+”, a gate for receiving a positive local oscillator signal labeled “LO+”, and a source connected to the drain of transistor 202 .
- Transistor 206 has a drain for providing a negative output current signal labeled “P ⁇ ”, a gate for receiving a positive local oscillator signal labeled “LO ⁇ ”, and a source connected to the drain of transistor 202 .
- Portion 200 forms what is referred to as a single balanced mixer, in which the input signal (which may be an intermediate frequency signal) is mixed with a local oscillator signal to form a differential in-phase current signal.
- this circuitry will be replicated to form a differential quadrature current signal using an LO signal in quadrature with the LO+ and LO ⁇ signal.
- the single-balanced mixer is susceptible to distortion caused by phase error mismatch between transistors 204 and 206 , as well as between transistor 202 and the corresponding transistor in the corresponding quadrature portion of the mixer.
- FIG. 3 illustrates in schematic form a portion 300 of another mixer known in the prior art.
- Portion 300 include a current source 302 , and N-channel transistors 304 , 306 , 308 , 310 , 312 , and 314 .
- Current source 302 has a first terminal and a second terminal connected to ground.
- Transistor 304 has a drain, a gate for receiving IF+, and a source connected to the first terminal of current source 302 .
- Transistor 306 has a drain, a gate for receiving IF ⁇ , and a source connected to the first terminal of current source 302 .
- Transistor 308 has a drain for providing current signal P+, a gate for receiving signal LO+, and a source connected to the drain of transistor 304 .
- Transistor 310 has a drain for providing current signal P ⁇ , a gate for receiving signal LO ⁇ , and a source connected to the drain of transistor 304 .
- Transistor 312 has a drain connected to the drain of transistor 308 , a gate for receiving signal LO ⁇ , and a source connected to the drain of transistor 306 .
- Transistor 314 has a drain connected to the drain of transistor 310 , a gate for receiving signal LO+, and a source connected to the drain of transistor 306 .
- Portion 300 forms what is referred to as a double balanced mixer or Gilbert cell, in which the differential input signal is mixed with a differential local oscillator signal to form a differential in-phase current signal. Like the single balanced case, this circuitry may be replicated to form a differential quadrature current signal using a quadrature local oscillator signal. Transistors 304 and 306 selectively divert the current of current source 302 based on the differential input signal. Transistors 308 , 310 , 312 , and 314 form a “chopper” circuit that “chops” the two portions of the differential current using the differential LO signal.
- each output current signal of the differential current pair namely P+ and P ⁇
- P+ and P ⁇ are formed by chopping using both LO signals, they are less susceptible to distortion from phase error between the positive and negative components of the LO clock signal. However they are still susceptible to distortion caused by phase error between the in-phase LO signal and the quadrature LO signal. They are also susceptible to mismatch between transistors 304 and 306 , as well as mismatch between the current sources 302 of the in-phase and quadrature mixers.
- FIG. 4 illustrates in partial block diagram and partial schematic mixer 114 of FIG. 1 , including local oscillator 116 and multiplier 118 .
- Local oscillator 116 includes generally an oscillator 402 , a phase clock generator 404 , a first set of conductors 410 , a latch 420 , and a second set of conductors 430 .
- Oscillator 402 provides an output clock signal labeled “4 ⁇ CLOCK” referenced to ground.
- Phase clock generator 404 has an input terminal for receiving the 4 ⁇ CLOCK, and output terminals for providing four phase clock signals labeled “ ⁇ 1 ”, “ ⁇ 2 ”, “ ⁇ 3 ”, and “ ⁇ 4 ”.
- the phase clock signals are conducted on respective conductors 412 , 414 , 416 , and 418 , with phase clock generator 404 connected to a first end of the conductor and latch 420 connected to a second end.
- Latch 420 includes D flip-flops 422 , 424 , 426 , and 428 .
- Flip-flop 422 has a D input terminal connected to the second end of conductor 412 , a clock input terminal for receiving the 4 ⁇ CLOCK, and a Q output terminal for providing a latched phase clock signal labeled “ ⁇ 1 ”.
- Flip-flop 424 has a D input terminal connected to the second end of conductor 414 , a clock input terminal for receiving the 4 ⁇ CLOCK, and a Q output terminal for providing a latched phase clock signal labeled “ ⁇ 2 ′”.
- Flip-flop 426 has a D input terminal connected to the second end of conductor 416 , a clock input terminal for receiving the 4 ⁇ CLOCK, and a Q output terminal for providing a latched phase clock signal labeled “ ⁇ 3 ′”.
- Flip-flop 428 has a D input terminal connected to the second end of conductor 418 , a clock input terminal for receiving the 4 ⁇ CLOCK, and a Q output terminal for providing a latched phase clock signal labeled “ ⁇ 4 ′”.
- Conductors 430 include four conductors 432 , 434 , 436 , and 438 each having a first end connected to the Q output terminals of latches 422 , 424 , 426 , and 428 , respectively, and a second end connected to corresponding input terminals of multiplier 118 .
- Multiplier 118 has four inputs connected to the second ends of conductors 432 , 434 , 436 , and 438 , a pair of signal input terminals for receiving IF+ and IF ⁇ , and four output terminals respectively providing baseband signals P+, Q+, P ⁇ , and Q ⁇ .
- mixer 114 resynchronizes the phase clocks using the 4 ⁇ CLOCK at a physical location on the integrated circuit near where the phase clocks are used, that is at multiplier 118 .
- Latch 420 requires a relatively small amount of circuitry and it can be placed to reduce the length of conductors 430 as much as possible.
- the an important feature is that the impedance of conductors 430 is less than the impedance of corresponding conductors 410 . Note that this characteristic will generally mean that the length of conductors 430 will be shorter than the length of conductors 410 . Note however that other factors contribute to the impedance such as total conductor area, dielectric (usually silicon dioxide or silicon nitride) spacing, etc. so that length is not the only determinant of impedance.
- each individual D flip-flop in latch 420 might be laid out as a repeated cell in close proximity to multiplier 118 .
- the uniformity in repeating the flip-flop cell layout may cause the length of conductors 430 to be somewhat above the theoretical minimum distance but it would be desirable to reduce it as much as practical to achieve the objective of reducing distortion.
- the lengths of each one of conductors 430 need to be made as nearly equal as possible.
- sum mixer 114 improves phase clock accuracy by reducing critical signal routing length of conductors 430 (therefore reducing the opportunity for differing propagation lengths and mismatched loading), decreasing the loading at the output of latch 420 , and allowing the flip flops in latch 420 to be laid out so as to match their characteristics as nearly as possible.
- FIG. 5 illustrates a timing diagram 500 for timing signals associated with mixer 114 of FIG. 4 .
- Timing diagram 500 illustrates the 4 ⁇ CLOCK signal and the four phase clock signals ⁇ 1 , ⁇ 2 , ⁇ 3 , and ⁇ 4 . It also illustrates two signals labeled “B 0 ” and “B 1 ” that are used to generate the phase clock signals.
- B 0 and B 1 are the outputs of a binary counter (not shown in FIG. 4 ) that is part of phase clock generator 404 and that increments once for each cycle of the 4 ⁇ CLOCK.
- Phase clock generator 404 generates the phase clock signals by performing logical operations on the counter outputs.
- phase clock generator 404 may be implemented using other similar digital logic circuits.
- FIG. 6 illustrates in partial block diagram and partial schematic multiplier 118 of mixer 114 of FIG. 1 .
- Multiplier 118 includes generally a transconductance amplifier 620 , a chopper circuit in the form of a barrel shifter 640 , and a load circuit 660 .
- Transconductance amplifier 620 includes N-channel MOS transistors 622 , 624 , 626 , 628 , 632 , 634 , 636 , and 638 .
- Transistor 622 has a drain and gate connected together and receiving signal IF+, and a source connected to ground.
- Transistor 624 has a drain, a gate connected to the drain and gate of transistor 622 , and a source connected to ground.
- Transistor 626 has a drain for providing a negative current of a first differential input current pair, a gate for receiving a bias voltage labeled “VBN 2 ”, and a source connected to the drain of transistor 622 .
- Transistor 628 has a drain for providing a positive current of the first differential input current pair, a gate for receiving bias voltage VBN 2 , and a source connected to the drain of transistor 624 .
- Transistor 632 has a drain and gate connected together and receiving signal IF ⁇ , and a source connected to ground.
- Transistor 634 has a drain, a gate connected to the drain and gate of transistor 632 , and a source connected to ground.
- Transistor 636 has a drain for providing a positive current of a second differential input current pair, a gate for receiving bias voltage VBN 2 , and a source connected to the drain of transistor 632 .
- Transistor 638 has a drain for providing a negative current of the second differential input current pair, a gate for receiving bias voltage VBN 2 , and a source connected to the drain of transistor 634 .
- Barrel shifter 620 has four input terminals respectively receiving the positive and negative currents of the first and second differential input current pairs, four clock input terminals for receiving clock signals ⁇ 1 - ⁇ 4 , and four output terminals connected to respective nodes for providing positive and negative currents of each of the first and second differential output current pairs.
- Load circuit 660 includes four N-channel MOS transistors 662 , 664 , 666 , and 668 , and four current sources 682 , 684 , 686 , and 688 .
- Transistor 662 has a drain for providing an output voltage labeled “P+”, a gate for receiving a bias voltage labeled “VNB 3 ”, and a source connected to the first node for receiving the negative current of the first differential output current pair.
- Transistor 664 has a drain for providing an output voltage labeled “Q+”, a gate for receiving bias voltage VNB 3 , and a source connected to the second node for receiving the positive current of the first differential output current pair.
- Transistor 666 has a drain for providing an output voltage labeled “P ⁇ ”, a gate for receiving bias voltage VNB 3 , and a source connected to the third node for receiving the positive current of the second differential output current pair.
- Transistor 668 has a drain for providing an output voltage labeled “Q ⁇ ”, a gate for receiving bias voltage VNB 3 , and a source connected to the fourth node for receiving the negative current of the second differential output current pair.
- Current source 682 has a first terminal connected to a positive power supply voltage terminal, and a second terminal connected to the drain of transistor 662 .
- Current source 684 has a first terminal connected to the positive power supply voltage terminal, and a second terminal connected to the drain of transistor 664 .
- Current source 686 has a first terminal connected to the positive power supply voltage terminal, and a second terminal connected to the drain of transistor 666 .
- Current source 688 has a first terminal connected to the positive power supply voltage terminal, and a second terminal connected to the drain of transistor 668 .
- transconductance amplifier 620 provides a linear input impedance and a linear differential output current.
- the linear input impedance is formed using two stacked pairs of N-channel MOS transistors, 622 / 626 and 632 / 636 , operating in saturation and strong inversion.
- Transistors 622 and 632 are diode connected and cascode transistors 626 and 636 are biased with a constant bias voltage VBN 2 .
- Each of two additional pairs of transistors 624 / 628 and 634 / 638 forms a current mirror with their respective diode-connected transistors.
- the differential currents formed thereby are linear with respect to the input voltage.
- the linear input impedance helps the receiver IC operate with an impedance-sensitive external SAW filter.
- the input impedance Z IN is given by:
- Barrel shifter 640 compensates for phase clock error by switching currents forming both in-phase and quadrature output signals using the same set of clock signals, substantially canceling the effect of this phase clock error.
- Barrel shifter 640 includes four input nodes labeled “A”, “B”, “C”, and “D” for receiving positive and negative input currents of first and second differential input current pairs, and four output nodes labeled “A′”, “B′”, “C′” and “D′” into which barrel shifter 640 provides positive and negative output currents of first and second differential output current pairs.
- Barrel shifter 640 includes generally four rows of transistors 710 , 720 , 730 , and 740 .
- Row 710 includes N-channel MOS transistors 711 , 712 , 713 , and 714 each having a source connected to the A input node, gates for receiving respective ones of signals ⁇ 4 , ⁇ 1 , ⁇ 2 , and ⁇ 3 , and drains connected to respective ones of output nodes A′, B′, C′, and D′.
- Row 720 includes N-channel MOS transistors 721 , 722 , 723 , and 724 each having a source connected to the B input node, gates for receiving respective ones of signals ⁇ 3 , ⁇ 4 , ⁇ 1 , and ⁇ 2 , and drains connected to respective ones of output nodes A′, B′, C′, and D′.
- Row 730 includes N-channel MOS transistors 731 , 732 , 733 , and 734 each having a source connected to the C input node, gates for receiving respective ones of signals ⁇ 2 , ⁇ 3 , ⁇ 4 , and ⁇ 1 , and drains connected to respective ones of output nodes A′, B′, C′, and D′.
- Row 740 includes N-channel MOS transistors 741 , 742 , 743 , and 744 each having a source connected to the D input node, gates for receiving respective ones of signals ⁇ 1 , ⁇ 2 , ⁇ 3 , and ⁇ 4 , and drains connected to respective ones of output nodes A′, B′, C′, and D′.
- Barrel shifter 640 improves mixer gain matching over known chopper circuits by rotating the transistors used to chop each input current. Thus if one transistor caused gain mismatch relative to other transistors, it would be used to chop the input current only one-fourth of the time. Barrel shifter 640 also drives each output current using all four phase clock signals. Since such a phase clock error will distort both the positive and negative components of the differential in-phase or quadrature current pair in the same way, the effect will tend to be cancelled.
- load circuit 660 converts the differential output current pairs at the output of barrel shifter 640 into corresponding differential voltage pairs.
- Cascode transistors 662 , 664 , 666 , and 668 are biased by constant bias voltage VBN 3 and reduce the voltage swing on cascode transistors 626 , 628 , 636 , and 638 , thereby improving linearity. Furthermore they also reduce the coupling of switching noise to the outputs.
- mixer 114 uses the polyphase filter to pass the upper sideband and attenuate the lower sideband of the desired signal.
- mixer 114 may be altered to pass the lower sideband and attenuate the upper sideband by simply reversing the sequence of clocks ⁇ 1 - ⁇ 4 , for example by swapping clocks ⁇ 1 and ⁇ 3 (or ⁇ 2 and ⁇ 4 ).
- Known mixers require that one of the LO clocks (in-phase or quadrature) be inverted to change the selected sideband.
Abstract
Description
- 1. Application Ser. No. 10/814,615, filed on Mar. 31, 2004, entitled “Polyphase Filter with Passband Compensation and Method Therefor” invented by Andrew W. Dornbusch and assigned to the assignee hereof.
- 2. Application Ser. No. 10/853,633, filed of even date herewith, entitled “Transconductance Amplifier with Substantially Constant Resistance and Mixer Using Same” invented by Andrew W. Dornbusch and assigned to the assignee hereof.
- 3. Application Ser. No. 10/853,444, filed of even date herewith, entitled “Mixer with Clock Resynchronization and Method Therefor” invented by Andrew W. Dornbusch and assigned to the assignee hereof.
I D622=β622(V IF+ −V T)2 [1]
where VIF+ is the voltage of signal IF+, VT is the threshold of
I D626=β626[(V BN2 −V IF+)−V T]2 [2]
Now if VBN2 and VIN are defined to be set as follows:
V BN2≡2V T+2V ON [3]
and
V IF+ ≡V T +V ON +V I [4]
where VON is a constant and VI is the input signal relative to (VT+VON), then
I D622=β622(V ON +V I)2 [5]
and
I D626=β626(V ON −V I)2 [6]
We know that
which is linear with respect to input voltage. The input impedance ZIN is given by:
which is constant and controllable. The first differential input current IDIFF1 is given by
I OUT ≡I D628 −I D626 =I D626 −I D622=−4βVI V ON [9]
since ID628=ID624=ID622. It should be clear that the second differential input current IDIFF2 is derived similarly and the other portion of
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US9543897B2 (en) | 2015-02-13 | 2017-01-10 | Qualcomm Incorporated | Fully I/Q balanced quadrature radio frequency mixer with low noise and low conversion loss |
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US20050220224A1 (en) * | 2004-03-31 | 2005-10-06 | Silicon Laboratories Inc. | Polyphase filter with passband compensation and method therefor |
US7471134B2 (en) * | 2004-05-25 | 2008-12-30 | Silicon Laboratories, Inc. | Mixer with clock resynchronization and method therefor |
US7750724B2 (en) * | 2007-12-20 | 2010-07-06 | Cirrus Logic, Inc. | Temperature and process-stable magnetic field sensor bias current source |
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