|Publication number||US7386661 B2|
|Application number||US 10/965,468|
|Publication date||10 Jun 2008|
|Filing date||13 Oct 2004|
|Priority date||13 Oct 2004|
|Also published as||US8417900, US20060080563|
|Publication number||10965468, 965468, US 7386661 B2, US 7386661B2, US-B2-7386661, US7386661 B2, US7386661B2|
|Inventors||Angel G. Perozo, Theodore C. White, William W. Dennin, Aurelio J. Cruz|
|Original Assignee||Marvell International Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (105), Non-Patent Citations (7), Referenced by (4), Classifications (14), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates generally to storage device controllers, and more particularly, to a power saving system and methodology for storage device controllers.
Conventional computer systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and streaming storage devices (for example, tape drives) (referred to herein as “storage device”).
In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.
The storage device is coupled to the host system via a controller that handles complex details of interfacing the storage devices to the host system. Communications between the host system and the controller is usually provided using one of a variety of standard I/O bus interfaces.
Typically, when data is read from a storage device, a host system sends a read command to the controller, which stores the read command into the buffer memory. Data is read from the device and stored in the buffer memory.
Buffer memory may be a Synchronous Dynamic Random access Memory (“SDRAM”), or Double Data Rate-Synchronous Dynamic Random Access Memory (referred to as “DDR”).
Various clocks are used for operating various storage controller components. For example, a buffer controller clock (“BCCLK”) is used for various storage controller components; a Fibre Channel clock (“FCCLK”) is used for a Fibre Channel port/interface through which data enters the storage controller; and a receive channel (also referred to as “Channel 1” or “CH1”) clock (designated as “RxCLK”). Other clocks may also be used for other components in a storage controller.
In conventional systems, in order to save power, some of these clocks are turned off in different parts of the storage controller. However, this solution may result in loss of data, especially, when unsolicited frames arrive from a Fibre Channel interface.
Therefore, there is a need for a system and method that can save power and also minimize loss of data.
A storage controller for transferring data between a storage device and a host system is provided. The storage controller includes, a power save module that is enabled in a power save mode after a receive logic in the storage controller has processed all frames and during the power save mode at least a clock is turned off to save power while a clock for operating the receive logic is kept on to process any unsolicited frames that may be received by the receive logic.
The storage controller operates in a single frame mode during the power save mode to process any unsolicited frames. Setting a bit in a configuration register for a processor enables the power save mode. The power save mode is enabled after a memory controller is in a self-refresh mode. The power save module monitors a bit that denotes when a memory controller is in a self-refresh mode. A clock power control module is used to turn off a buffer controller clock during the power save mode.
The power save module exits the power save mode upon receiving an unsolicited frame or a reset signal from a processor.
A system for transferring data between a storage device and a host system is provided. The system includes a storage controller with a power save module that is described above.
In yet another aspect of the present invention, a method used by a storage controller that facilitates data transfer between a host system and a storage device is provided. The method includes, enabling a power save module to start a power save sequence when a receive logic in the storage controller has processed all frames, wherein during the power save mode at least a clock is turned off to save power while a clock for operating the receive logic is kept on to process any unsolicited frames; enabling a single frame mode during which a received frame is handled by storage controller firmware; and exiting the power save mode if an unsolicited frame is received by the receive logic.
This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof concerning the attached drawings.
The foregoing features and other features of the present invention will now be described with reference to the drawings of a preferred embodiment. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following Figures:
To facilitate an understanding of the preferred embodiment, the general architecture and operation of a controller will initially be described. The specific architecture and operation of the preferred embodiment will then be described with reference to the general architecture.
The system of
As shown in
A read only memory (“ROM”) omitted from the drawing is used to store firmware code executed by microprocessor 100. Fibre Channel interface interfaces with host interface 104A and processes Fibre Channel frames. Fibre Channel interface 103 operates under the FCCLK.
Controller 101 can be an integrated circuit (IC) that comprises of various functional modules, which provide for the writing and reading of data stored on storage device 110. Microprocessor 100 is coupled to controller 101 via interface 109 to facilitate transfer of data, address, timing and control information.
Buffer memory 111 is coupled to controller 101 via ports to facilitate transfer of data, timing and address information. Buffer memory 111 may be a DDR or SDRAM or any other type of memory. Buffer memory 111 operates under the BCCLK.
Disk formatter 104 is connected to microprocessor bus 107 and to buffer controller 108. A direct memory access (“DMA”) DMA interface (not shown) is connected to microprocessor bus 107 and to data and control port (not shown).
Buffer controller (also referred to as “BC”) 108 connects buffer memory 111, channel one (CH1) 105, error correction code (“ECC”) module 106 and to bus 107. Buffer controller 108 regulates data movement into and out of buffer memory 111. BC 108, DF 104 and ECC module 106 operate under the BCCLK.
Data flow between a host and disk passes through buffer memory 111. ECC module 106 generates the ECC that is saved on disk 110 writes and provides correction mask to BC 108 for disk 110 read operation.
Plural channels may be used to allow data flow. Channels (for example, channel 0 (“CH0”), CH1 105 and channel 2 (“CH2”) (not shown)) are granted arbitration turns when they are allowed access to buffer memory 111 in high speed burst write or read for a certain number of clocks. The plural channels use first-in-first out (“FIFO”) type memories to store data that is in transit.
CH1 105 may be inside BC 108 or outside BC 108, as shown in
Buffer Controller 108:
BC 108 also includes a memory controller 108B that interfaces with buffer 111 through a SDRAM interface 108J. Interrupts 108I are sent from buffer controller 108 to processor 100.
BCCLK that is used for various components may be generated by using an oscillator (not shown) and controlled by a clock distribution module. The clock distribution module and clock generation has been described in U.S. patent application Ser. No. 10/867,113 filed on Jun. 24, 2004, the disclosure of which is incorporated herein by reference in its entirety.
As described below, power save module 113 and BCCLK Power Save module 114 (may also be referred to as BCCLK Power Save Module or BCCLK_PWR_CNTRL) are used to save power in storage controller 101, according to one aspect of the present invention.
Power Save Module 113:
In one aspect of the present invention, power save module 113 is provided that uses a clock distribution system so that the BCCLK is shut down in various modules, for example, ECC module 106, DF 104, and memory controller 108B. The receive clocks for Fibre Channel interface 103 and CH1 105 in the receive path are kept running to process unsolicited frames that may be received via interface 103.
The Power Save Mode is turned on when there are no pending interrupts in the receive logic (i.e. Fibre Channel Interface 103 and CH1 105). State machine 113A monitors CH1 105 flags and waits until all the data in CH1 105 has been processed. Thereafter, the Power Save Mode is enabled.
A single frame mode (“SFM”) is also used in conjunction with the power save mode. During the SFM, unsolicited frames are not sent to BC 108 when the BCCLK is turned off, but instead frames are handled/processed/throttled (used interchangeably) individually.
A user that wants to use controller 101 in the power save mode sets the “Power Save Mode” bit (shown as 201) in MP 100 configuration register 200 in
Upon receiving signal 113E, power save module sends signal 113B to CH1 105 logic. Signal 113B sets CH1 105 into SFM and during this mode each frame in CH1 105 is throttled (or handled) individually. Every frame that is received during the SFM uses a firmware action before being transferred to buffer memory 111. After this, power save module 113 waits until CH1 105 FIFO (not shown) and transmit pipe used for moving frames (not shown) are empty.
Signal 113C notifies power save module 113 when CH1 105 has processed all the frames. Once the FIFO and the pipes are empty, power save module 113 instructs MP 100 via signal 113I to enter into a self-refresh mode and to turn off the BCCLK (via signal 113D). In turn, MP 100 notifies BCCLK Power Control module 114, via signal 113J to enter into a self-refresh mode and to turn off the BCCLK. The self-refresh mode allows data in buffer memory 111 to stay current/valid.
BCCLK Power Control module 114 notifies memory controller 108B, via signal 113G to enter into a self refresh mode. Power save module 113 monitors signal 113H to determine if and when buffer memory 111 is in refresh mode. Once buffer memory 111 is in refresh mode, BCCLK power control module 114 sends signal 113L to memory controller 108B to turn off the BCCLK. This turns off the BCCLK for various modules, including BC 108, ECC module 106, and DF 104. The clocks for FC interface 103 and CH1 105 are always running to receive an unsolicited frame.
When an unsolicited frame is received by FC interface 103 and CH1 105, an interrupt 113K is generated. This resets the Power Save Mode and Power Save module 113 exits the power save sequence. The unsolicited frame is processed in the SFM. Thereafter, the entire process is repeated again.
Power save status is provided to MP 100 via signal 113M and is represented by plural bits 202, as listed below:
Bit 00001: State Machine 113A is in idle state 300 and the Power Save mode bit 201 is 0.
Bit 00010: The Power Save module 113 is waiting for CH1 105 FIFOs and pipelines to become empty.
Bit 00100: The Power Save module 113 is waiting for buffer memory 111 to go into the self-refresh mode.
Bit 01000: Buffer memory 111 is in self-refresh mode and the BCCLK is not running.
Bit 10000: An interrupt 113K occurred or MP 100 requested (via signal 113F,
Bit 203: This bit is used to turn off the BCCLK. The bit may be set by an external microprocessor or by the Power Save mode.
Bit 204: This bit when set (for example, 1), allows the memory controller 108B to go in the self-refresh mode. When the bit is cleared (for example, 0), the memory controller 108B exits the self-refresh mode.
State Machine 113A Diagram:
In state 302, state machine 113B waits for CH1 105 FIFO's to become empty. This occurs after the power save mode bit 201 is set. During this state, the SFM is enabled and the BCCLK is on.
In state 304, the self-refresh mode is enabled, after CH1 105 FIFO and frame-processing pipeline (not shown) is empty. During this state, the SFM is turned on, a self-refresh request is placed and the BCCLK is still on.
Once the self-refresh mode is enabled, in state 306, the BCCLK is turned off, while the SFM is still enabled. The state machine 113A now waits for a wake up event. Two events may “wakeup” state machine 113A, first an interrupt 113K from MC 102 or a reset request 113F from MF 100. Once the wake up event occurs, the self-refresh is disabled in state 310. The BCCLK is still turned off and SFM 1 is still enabled. During this state, if an unsolicited frame arrived, then the frame is processed in the SFM. After the frame is processed, the state machine is back to the idle state 300.
In one aspect of the present invention, clocks are turned off selectively to components that are idle. The components that may receive unsolicited frames have their clocks on to process incoming frames. This saves power with minimum loss of data.
Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3800281||26 Dec 1972||26 Mar 1974||Ibm||Error detection and correction systems|
|US3988716||5 Aug 1974||26 Oct 1976||Nasa||Computer interface system|
|US4001883||7 Mar 1974||4 Jan 1977||Honeywell Information Systems, Inc.||High density data storage on magnetic disk|
|US4016368||12 Dec 1975||5 Apr 1977||North Electric Company||Framing circuit for digital receiver|
|US4050097||27 Sep 1976||20 Sep 1977||Honeywell Information Systems, Inc.||Synchronization technique for data transfers over an asynchronous common bus network coupling data processing apparatus|
|US4080649||16 Dec 1976||21 Mar 1978||Honeywell Information Systems Inc.||Balancing the utilization of I/O system processors|
|US4156867||6 Sep 1977||29 May 1979||Motorola, Inc.||Data communication system with random and burst error protection and correction|
|US4225960||1 Mar 1979||30 Sep 1980||Westinghouse Electric Corp.||Automatic synchronizing system for digital asynchronous communications|
|US4275457||22 Oct 1979||23 Jun 1981||Martin Marietta Corporation||Apparatus and method for receiving digital data at a first rate and outputting the data at a different rate|
|US4390969||21 Apr 1980||28 Jun 1983||Burroughs Corporation||Asynchronous data transmission system with state variable memory and handshaking protocol circuits|
|US4451898||9 Nov 1981||29 May 1984||Hewlett-Packard Company||Asynchronous interface message transmission using source and receive devices|
|US4486750||14 May 1982||4 Dec 1984||Takeda Riken Co. Ltd.||Data transfer system|
|US4500926||14 Jun 1982||19 Feb 1985||Tokyo Shibaura Denki Kabushiki Kaisha||Data-recording apparatus|
|US4587609||1 Jul 1983||6 May 1986||Honeywell Information Systems Inc.||Lockout operation among asynchronous accessers of a shared computer system resource|
|US4603382||27 Feb 1984||29 Jul 1986||International Business Machines Corporation||Dynamic buffer reallocation|
|US4625321||23 May 1985||25 Nov 1986||Standard Microsystems Corporation||Dual edge clock address mark detector|
|US4667286||20 Dec 1984||19 May 1987||Advanced Micro Devices, Inc.||Method and apparatus for transferring data between a disk and a central processing unit|
|US4777635||8 Aug 1986||11 Oct 1988||Data Systems Technology Corp.||Reed-Solomon code encoder and syndrome generator circuit|
|US4805046||23 Oct 1986||14 Feb 1989||Matsushita Electric Industrial Co., Ltd.||Information recording and reproducing apparatus using sectors divided into a plurality of frames and having means for proper storage of the frame data|
|US4807116||18 May 1987||21 Feb 1989||Tandem Computers Incorporated||Interprocessor communication|
|US4807253||13 Nov 1987||21 Feb 1989||American Telephone And Telegraph Company, At&T Bell Laboratories||Time-varying trellis-coded modulation formats which are robust in channels with phase variations|
|US4809091||15 Apr 1987||28 Feb 1989||Hitachi, Ltd.||Disk apparatus|
|US4811282||18 Dec 1986||7 Mar 1989||Sgs Mircroelettronica Spa||Retiming circuit for pulse signals, particularly for microprocessor peripherals|
|US4812769||30 Apr 1986||14 Mar 1989||Tektronix, Inc.||Programmable sampling time base circuit|
|US4860333||11 Mar 1987||22 Aug 1989||Oread Laboratories, Inc.||Error protected central control unit of a switching system and method of operation of its memory configuration|
|US4866606||24 Jun 1987||12 Sep 1989||Austria Miktosystem International Gmbh||Loosely coupled distributed computer system with node synchronization for precision in real time applications|
|US4881232||5 Feb 1988||14 Nov 1989||Sony Corporation||Method and apparatus for error correction|
|US4920535||14 Dec 1988||24 Apr 1990||Fujitsu Limited||Demultiplexer system|
|US4949342||11 Apr 1988||14 Aug 1990||Matsushita Electric Industrial Co., Ltd.||Code error detecting method|
|US4970418||26 Sep 1989||13 Nov 1990||Apple Computer, Inc.||Programmable memory state machine for providing variable clocking to a multimode memory|
|US4972417||15 Jun 1989||20 Nov 1990||Sony Corporation||PCM data transmitting apparatus and method|
|US4975915||13 Apr 1989||4 Dec 1990||Sony Corporation||Data transmission and reception apparatus and method|
|US4989190||19 Jul 1988||29 Jan 1991||Oki Electric Industry Co., Ltd.||Apparatus for seeking a track of an optical disk in which information is recorded|
|US5014186||27 Sep 1988||7 May 1991||International Business Machines Corporation||Data-processing system having a packet transfer type input/output system|
|US5023612||13 Jul 1989||11 Jun 1991||Pacific Bell||Illegal sequence detection and protection circuit|
|US5027357||14 Oct 1988||25 Jun 1991||Advanced Micro Devices, Inc.||ECC/CRC error detection and correction system|
|US5050013||4 May 1990||17 Sep 1991||Seagate Technology, Inc.||Hard sectoring circuit and method for a rotating disk data storage device|
|US5051998||28 Jun 1989||24 Sep 1991||Matsushita Electric Industrial Co., Ltd.||Data block deinterleaving and error correction system|
|US5068755||1 Jun 1990||26 Nov 1991||Micropolis Corporation||Sector pulse generator for hard disk drive assembly|
|US5068857||1 Sep 1989||26 Nov 1991||Mitsubishi Denki Kabushiki Kaisha||Error correction circuit|
|US5072420||16 Mar 1989||10 Dec 1991||Western Digital Corporation||FIFO control architecture and method for buffer memory access arbitration|
|US5088093||16 Oct 1987||11 Feb 1992||Cias, Inc.||Self-correcting registers, error-detecting/correcting registers, and inversion coding using one bit, and other information storage media|
|US5109500||28 Oct 1987||28 Apr 1992||Hitachi, Ltd.||Disk drive control unit having sets of operating command and operation length information and generating end signal based upon operation length information|
|US5117442||14 Dec 1988||26 May 1992||National Semiconductor Corporation||Methods and circuits for synchronizing signals in a modular redundant fault tolerant computer system|
|US5127098||28 Sep 1989||30 Jun 1992||Sun Microsystems, Inc.||Method and apparatus for the context switching of devices|
|US5133062||13 Aug 1990||21 Jul 1992||Advanced Micro Devices, Inc.||RAM buffer controller for providing simulated first-in-first-out (FIFO) buffers in a random access memory|
|US5136592||28 Jun 1989||4 Aug 1992||Digital Equipment Corporation||Error detection and correction system for long burst errors|
|US5146585||5 Nov 1990||8 Sep 1992||International Business Machines Corporation||Synchronized fault tolerant clocks for multiprocessor systems|
|US5157669||23 Apr 1991||20 Oct 1992||Advanced Micro Devices, Inc.||Comparison of an estimated CRC syndrome to a generated CRC syndrome in an ECC/CRC system to detect uncorrectable errors|
|US5162954||31 Jul 1990||10 Nov 1992||Seagate Technology Inc.||Apparatus for generating an index pulse in a data storage system|
|US5193197||30 Aug 1990||9 Mar 1993||Digital Equipment Corporation||Apparatus and method for distributed dynamic priority arbitration for access to a shared resource|
|US5204859||13 Feb 1991||20 Apr 1993||Gec Plessey Telecommunications Limited||Method and apparatus for detecting a frame alignment word in a data system|
|US5218564||7 Jun 1991||8 Jun 1993||National Semiconductor Corporation||Layout efficient 32-bit shifter/register with 16-bit interface|
|US5220569||9 Jul 1990||15 Jun 1993||Seagate Technology, Inc.||Disk array with error type indication and selection of error correction method|
|US5237593||1 May 1990||17 Aug 1993||Stc, Plc||Sequence synchronisation|
|US5243471||10 Jan 1991||7 Sep 1993||Hewlett-Packard Company||Method and apparatus for detecting a start of data position in differing tracks|
|US5249271||19 Feb 1993||28 Sep 1993||Emulex Corporation||Buffer memory data flow controller|
|US5257143||15 Jan 1991||26 Oct 1993||Zenith Data Systems Corporation||Method and apparatus for positioning head of disk drive using zone-bit-recording|
|US5261081||26 Jul 1990||9 Nov 1993||Ncr Corporation||Sequence control apparatus for producing output signals in synchronous with a consistent delay from rising or falling edge of clock input signal|
|US5271018||27 Apr 1990||14 Dec 1993||Next, Inc.||Method and apparatus for media defect management and media addressing|
|US5274509||10 Sep 1992||28 Dec 1993||Digital Equipment Corporation||On-the-fly splitting of disk data blocks using timed sampling of a data position indicator|
|US5276564||16 Apr 1992||4 Jan 1994||Hewlett-Packard Company||Programmable start-of-sector pulse generator for a disk drive using embedded servo bursts and split data fields|
|US5276662||1 Oct 1992||4 Jan 1994||Seagate Technology, Inc.||Disc drive with improved data transfer management apparatus|
|US5276807||20 Jul 1990||4 Jan 1994||Emulex Corporation||Bus interface synchronization circuitry for reducing time between successive data transmission in a system using an asynchronous handshaking|
|US5280488||8 Nov 1990||18 Jan 1994||Neal Glover||Reed-Solomon code system employing k-bit serial techniques for encoding and burst error trapping|
|US5285327||5 May 1993||8 Feb 1994||International Business Machines Corporation||Apparatus for controlling reading and writing in a disk drive|
|US5285451||15 Jul 1992||8 Feb 1994||Micro Technology, Inc.||Failure-tolerant mass storage system|
|US5301333||27 Aug 1993||5 Apr 1994||Bell Communications Research, Inc.||Tree structured variable priority arbitration implementing a round-robin scheduling policy|
|US5307216||4 Sep 1991||26 Apr 1994||International Business Machines Corporation||Sector identification method and apparatus for a direct access storage device|
|US5315708||6 Apr 1993||24 May 1994||Micro Technology, Inc.||Method and apparatus for transferring data through a staging memory|
|US5339443||17 Dec 1992||16 Aug 1994||Sun Microsystems, Inc.||Arbitrating multiprocessor accesses to shared resources|
|US5361266||19 Oct 1993||1 Nov 1994||Mitsubishi Denki Kabushiki Kaisha||Error correction circuit|
|US5361267||24 Apr 1992||1 Nov 1994||Digital Equipment Corporation||Scheme for error handling in a computer system|
|US5408644||5 Jun 1992||18 Apr 1995||Compaq Computer Corporation||Method and apparatus for improving the performance of partial stripe operations in a disk array subsystem|
|US5420984||13 Aug 1993||30 May 1995||Genroco, Inc.||Apparatus and method for rapid switching between control of first and second DMA circuitry to effect rapid switching beween DMA communications|
|US5428627||10 Nov 1992||27 Jun 1995||Qlogic Corporation||Method and apparatus for initializing an ECC circuit|
|US5440751||21 Jun 1991||8 Aug 1995||Compaq Computer Corp.||Burst data transfer to single cycle data transfer conversion and strobe signal conversion|
|US5465343||30 Apr 1993||7 Nov 1995||Quantum Corporation||Shared memory array for data block and control program storage in disk drive|
|US5487170||16 Dec 1993||23 Jan 1996||International Business Machines Corporation||Data processing system having dynamic priority task scheduling capabilities|
|US5488688||30 Mar 1994||30 Jan 1996||Motorola, Inc.||Data processor with real-time diagnostic capability|
|US5491701||18 Oct 1994||13 Feb 1996||Cirrus Logic, Inc.||Burst error corrector|
|US5500848||23 Jun 1993||19 Mar 1996||International Business Machines Corporation||Sector servo data recording disk having data regions without identification (ID) fields|
|US5506989||31 Jan 1990||9 Apr 1996||Ibm Corporation||Arbitration system limiting high priority successive grants|
|US5507005||17 Mar 1992||9 Apr 1996||Hitachi, Ltd.||Data transferring system between host and I/O using a main buffer with sub-buffers where quantity of data in sub-buffers determine access requests|
|US5519837||29 Jul 1994||21 May 1996||International Business Machines Corporation||Pseudo-round-robin arbitration for a shared resource system providing fairness and high throughput|
|US5523903||23 Dec 1993||4 Jun 1996||International Business Machines Corporation||Sector architecture for fixed block disk drive|
|US5544180||12 May 1995||6 Aug 1996||Qlogic Corporation||Error-tolerant byte synchronization recovery scheme|
|US5544346||9 Dec 1994||6 Aug 1996||International Business Machines Corporation||System having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a bus|
|US5546545||9 Dec 1994||13 Aug 1996||International Business Machines Corporation||Rotating priority selection logic circuit|
|US5546548||31 Mar 1993||13 Aug 1996||Intel Corporation||Arbiter and arbitration process for a dynamic and flexible prioritization|
|US5563896||7 Jun 1995||8 Oct 1996||Fujitsu Limited||Error correction processor and an error correcting method|
|US5572148||22 Mar 1995||5 Nov 1996||Altera Corporation||Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory|
|US5574867||8 Jul 1994||12 Nov 1996||Intel Corporation||Fast first-come first served arbitration method|
|US5581715||22 Jun 1994||3 Dec 1996||Oak Technologies, Inc.||IDE/ATA CD drive controller having a digital signal processor interface, dynamic random access memory, data error detection and correction, and a host interface|
|US5583999||8 Dec 1994||10 Dec 1996||Fujitsu Limited||Bus arbiter and bus arbitrating method|
|US5592404||16 Sep 1994||7 Jan 1997||Cirrus Logic, Inc.||Versatile error correction system|
|US5600662||28 Mar 1995||4 Feb 1997||Cirrus Logic, Inc.||Error correction method and apparatus for headers|
|US5602857||18 Oct 1994||11 Feb 1997||Cirrus Logic, Inc.||Error correction method and apparatus|
|US5615190||6 Jun 1995||25 Mar 1997||International Business Machines Corporation||Fixed- block architecture embedded servo disk drive without data identification (ID) regions|
|US6781911 *||9 Apr 2002||24 Aug 2004||Intel Corporation||Early power-down digital memory device and method|
|US6977685 *||25 Feb 2000||20 Dec 2005||Massachusetts Institute Of Technology||Single-chip imager system with programmable dynamic range|
|US20030118047 *||15 Nov 2002||26 Jun 2003||William Collette||Fibre channel frame batching for IP transmission|
|US20060083134 *||19 Nov 2003||20 Apr 2006||Katsumi Matsuno||Disk device, method for controlling disk devic, and program for disk device controlling method|
|US20060230300 *||6 Jun 2006||12 Oct 2006||Seiko Epson Corporation||Selective power-down for high performance CPU/system|
|US20060288160 *||24 Aug 2006||21 Dec 2006||Krantz Arie L||Disk controller configured to perform out of order execution of write operations|
|1||Blahut R. Digital Transmission of Information (Dec. 4, 1990), pp. 429-430.|
|2||Hwang, Kai and Briggs, Faye A., "Computer Architecture and Parallel Processing" pp. 156-164.|
|3||P.M. Bland et. al. Shared Storage Bus Circuitry, IBM Technical Disclosure Bulletin, vol. 25, No. 4, Sep. 1982, pp. 2223-2224.|
|4||PCT International Search Report, Doc. No. PCT/US00/15084, Dated Nov. 15, 2000, 2 Pages.|
|5||PCT search report for PCT/US00/07780 mailed Aug. 2, 2000, 4 Pages.|
|6||PCT search report for PCT/US01/22404, mailed Jan. 29, 2003, 4 Pages.|
|7||Zeidman, Bob, "Interleaving DRAMS for faster access", System Design ASIC & EDA, pp. 24-34 (Nov. 1993).|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8312313 *||5 Jan 2010||13 Nov 2012||Canon Kabushiki Kaisha||Information processing apparatus, method for controlling the information processing apparatus, and storage medium|
|US8433937 *||30 Jun 2010||30 Apr 2013||Western Digital Technologies, Inc.||Automated transitions power modes while continuously powering a power controller and powering down a media controller for at least one of the power modes|
|US9058834||10 Nov 2014||16 Jun 2015||Western Digital Technologies, Inc.||Power architecture for low power modes in storage devices|
|US20100174940 *||5 Jan 2010||8 Jul 2010||Canon Kabushiki Kaisha||Information processing apparatus, method for controlling the information processing apparatus, and storage medium|
|U.S. Classification||711/112, 713/300|
|Cooperative Classification||Y02B60/32, Y02B60/1282, G06F1/3228, G06F1/3287, Y02B60/1221, G06F1/3203, G06F1/3237|
|European Classification||G06F1/32P1D, G06F1/32P5C, G06F1/32P5S, G06F1/32P|
|12 Oct 2004||AS||Assignment|
Owner name: QLOGIC CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PEROZO, ANGEL G.;WHITE, THEODORE C.;DENNIN, WILLIAM W.;AND OTHERS;REEL/FRAME:015900/0384
Effective date: 20041011
|15 Nov 2005||AS||Assignment|
Owner name: MARVELL INTERNATIONAL LTD., BERMUDA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:QLOGIC CORPORATION;REEL/FRAME:017017/0747
Effective date: 20051104
|7 Oct 2008||CC||Certificate of correction|
|12 Dec 2011||FPAY||Fee payment|
Year of fee payment: 4