US7251468B2 - Dynamically matched mixer system with improved in-phase and quadrature (I/Q) balance and second order intercept point (IP2) performance - Google Patents
Dynamically matched mixer system with improved in-phase and quadrature (I/Q) balance and second order intercept point (IP2) performance Download PDFInfo
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- US7251468B2 US7251468B2 US10/890,691 US89069104A US7251468B2 US 7251468 B2 US7251468 B2 US 7251468B2 US 89069104 A US89069104 A US 89069104A US 7251468 B2 US7251468 B2 US 7251468B2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1441—Balanced arrangements with transistors using field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1458—Double balanced arrangements, i.e. where both input signals are differential
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1483—Balanced arrangements with transistors comprising components for selecting a particular frequency component of the output
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/16—Multiple-frequency-changing
- H03D7/165—Multiple-frequency-changing at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature
Definitions
- This invention relates in general to radio frequency (RF) mixers and more particularly to a system and method for mitigating signal spur interference between input signals in an RF mixer.
- RF radio frequency
- DCR direct conversion receiver
- LO local oscillator
- mitigation frequency reference signal is generated by using odd integer dividers to generate odd integer sub-multiples of the voltage controlled oscillator (VCO) frequency.
- VCO voltage controlled oscillator
- the LO frequency is generated by dividing down the VCO frequency by an even multiple for an even integer divider or by an odd multiple for an odd multiple divider.
- I and Q directly influences sideband suppression which, in turn, directly affects the generation of sub-audible signaling distortion products.
- I and Q mismatch can degrade second order intercept point (IP 2 ) performance which bears directly on the receiver's interference blocking performance.
- Prior art dynamically matched mixer systems include U.S. Pat. No. 6,125,272 to Bautista et al. that teaches a method and apparatus for providing improved intermodulation distortion protection.
- U.S. Pat. No. 6,125,272 is herein incorporated by reference.
- the prior art techniques involve the use of dynamic matching to transform coefficients of the IM 2 distortion from constant values into functions of time where they may be handled by known rejection techniques. This involves using odd and even integer dividers used to divide down from a single VCO source so that an even division multiple is used with the LO and the odd division multiple is used for quadrature generation.
- Bautista et al. limits the overall benefit of this dynamically matched mixer design since it decreases the receiver's IP 2 performance by randomizing the second order distortion product.
- Bautista et al. fail to address system level implementation issues that can degrade I/Q channel matching due to mitigation coupling between the LO quadrature generation circuitry and reference signal mitigation circuitry.
- the prior art dynamically matched differential I channel mixer 100 is illustrated in prior art FIG. 1 , where reference oscillator 101 and PLL 103 represent a phase locked loop that provides a stable radio frequency (RF) source at some predetermined frequency.
- the PLL 103 provides differential inputs to a plurality of frequency harmonic dividers namely N even divider 105 and N odd divider 107 .
- Each respective harmonic divider provides a means to provide an even or odd multiple harmonic frequency from the source provided by PLL 103 .
- the output of the N even divider 105 provides local oscillator (LO) differential inputs (F LO+ and F LO ⁇ ) to a mixer 109 while the output of the N odd divider 107 supplies a mitigation signal (F 1 ) to both the dynamic matching network 111 and the dynamic matching network 113 .
- LO local oscillator
- the mixer 109 is a standard Gilbert cell mixer which enables differential RF input signals (I RF + and I RF ⁇ ) to be mixed with both the LO differential signal (F LO+ and F LO ⁇ ) and mitigation signal F 1 .
- the dynamic matching network 111 and dynamic matching network 113 are essentially a switching network. These switching networks switch between transistor components within the in-phase (I) or quadrature (Q) mixer branches so as to average imperfections in the mixer's components to provide substantially enhanced mixer linearity.
- a plurality of alternating current (AC) couplers 115 , 116 are used to couple the mixer 109 and dynamic matching network 113 which helps to eliminate temperature compensating direct current (DC) mismatch, improves system common mode rejection of the dynamic mixer and eliminates the use of an 1/f noise adder by the LO.
- the differential baseband output signals (I BB + and I BB ⁇ ) for either an in-phase or quadrature channel is provided at an output of the dynamic matching network 113 .
- the circuit topology of prior art FIG. 1 creates a spur which causes problems depending on what harmonics are used at the LO and the mitigation signal F 1 .
- prior art FIG. 1 shows a differential I-channel mixer while a differential Q-channel mixer will be similarly configured.
- a direct conversion receiver architecture incorporating a dynamically matched mixer where the local oscillator and mitigation signal frequency are generated from non-integer related sources.
- This can include either two independent frequency generation units or using a direct digital synthesizer (DDS) with multiple independent outputs derived from a digital-to-time converter.
- DDS direct digital synthesizer
- This enables a single high frequency and high stability reference oscillator to drive a series of delay line structures of sufficient quantity to provide resolution in generating the targeted frequency.
- the DDS with digital-to-time conversion provides performance benefits in terms of flexibility, signal quality, integration, die area and current drain.
- the advantages of the invention include eliminating the need for a single frequency generation unit (FGU) to drive both the LO and mitigation frequency reference sources, real time variation of mitigation frequency to eliminate interference and increased flexibility in the selection of the mitigation frequency relative to the LO. This allows fractional selection of the mitigation rate.
- the architecture incorporates a single high frequency reference for generating multiple frequency sources to drive a differential DCR mixing structure.
- FIG. 1 is a prior art block diagram illustrating a dynamically matched balance mixer known in the prior art.
- FIG. 2 is a block diagram illustrating a dynamically matched mixer system according to the preferred embodiment of the invention.
- FIG. 3 is a block diagram shown a dynamically matched mixer system according to an alternative embodiment of the invention.
- FIG. 4 is a block diagram of a multiple frequency generation unit as utilized in the preferred embodiment of the invention.
- the dynamically matched mixer system with improved I/Q balance and IP 2 performance 200 includes a reference oscillator 201 coupled to a phase locked loop (PLL) 203 that generates a high frequency reference signal F ref .
- This F ref signal provides an input to the direct digital synthesizer (DDS) 205 .
- the DDS 205 employs a delay locked loop that allows for the generation of multiple independent output frequencies, namely, differential local oscillator signals (F LO + and F LO ⁇ ) and a first mitigation reference signal F 1 and a second mitigation reference signal F 2 . These outputs are non-integer related to one another and the F ref .
- the F ref signal PLL 203 and the DDS 205 form a highly stable and versatile frequency generation unit (FGU).
- FGU highly stable and versatile frequency generation unit
- the DDS 205 operates to mitigate spur interference through the intelligent selection of the first mitigation frequency signal F 1 and the second mitigation frequency signal F 2 . This is accomplished by using a digital processing circuit ( FIG.
- F LO(+ and ⁇ ) F ref /N 1
- F 1 F ref /N 2
- F 2 F ref /N 3 where N 1, N 2 and N 3 are real numbers.
- VLIF Very Low Frequency Intermediate Frequency
- the VLIF strategy is a specialized application of DCR where the RF, LO and mitigation frequencies are selected such that the output I BB+ and I BB ⁇ are typically 100's of kHz.
- VLIF strategies are typically used in global system for mobile communication (GSM) receiver mixers where the receiving protocol does not utilize contiguous occupied channels.
- GSM global system for mobile communication
- the GSM protocol specifies that certain adjacent frequency channels may be “open” or unoccupied.
- the F LO +/ ⁇ or a mitigation signal as described herein may be selected such that any spurious response falls in the unoccupied channel spectrum thus mitigating any undesired interference. This creates a great deal of extra flexibility in the intermediate frequency selection of the GSM mixer.
- the dynamically matched mixer system 200 includes the differential local oscillator signals (F LO + and F LO ⁇ ) that are provided to a mixer 209 .
- a first mitigation reference signal F 1 is supplied from the DDS 205 to the input dynamic matching network 211 .
- the dynamic matching network 211 provides a differential input signal (I RF + and I RF ⁇ ) to the mixer 209 which is then coupled through AC couplers 215 , 216 to the output dynamic matching network 213 .
- a second mitigation reference signal F 2 is supplied from the DDS 205 to the output dynamic matching network 213 .
- the differential output signals (I BB + or I BB ⁇ ) of the output dynamic matching network 213 represent either an in-phase or quadrature baseband output signal depending upon which type of mixer is used for the representative digital channel.
- FIG. 3 illustrates a block diagram of the dynamically matched mixer system 300 according to an alternative embodiment of the invention.
- the reference oscillator (F ref ) 205 the PLL 203 and the DDS 205 work to provide a differential local oscillator signal (F LO + and F LO ⁇ ) as well as a mitigation signal F 1 .
- This embodiment differs from that of FIG. 2 , through the use of a state selection manager 301 .
- the state select manager 301 operates to control the input dynamic matching network 211 in order to preset the state of the switch to a “low” or “high” state. This fixes the state of the switch without any time dependence that would occur with the use of a mitigation signal.
- the use of the state select manager 301 permits the input signal to no longer be dynamically matched to the input stage to the mixer 209 .
- the embodiment as shown in FIG. 3 while using only one switching network, namely, output dynamic switching network 213 allows substantially the similar performance to the dual switching network topology shown in FIG. 2 if the local oscillator frequency (F LO + and F LO ⁇ ) and mitigation signal frequency (F 1 ) are carefully selected.
- FIG. 4 illustrates a block diagram showing details of a multiple frequency generation unit (FGU) 400 used in accordance with the dynamic match mixers as describer herein.
- a reference oscillator 201 supplies a reference signal to a voltage controlled oscillator (VCO) which is a high stable PLL oscillator producing an F ref signal.
- VCO voltage controlled oscillator
- the F ref is supplied to the direct digital synthesizer (DDS) 205 .
- the DDS 205 is comprised of a digital processor 407 and a digital-to-time converter 409 .
- the multiple frequency generation unit 400 utilizes a DDS synthesizer 205 where each output (F 1 to FN) is independent yet is derived from a signal high frequency reference (F ref ).
- a principal benefit of this topology is that only the single VCO 203 is required.
- An output signal is constructed when the digital processor 407 selects taps from the digital-to-time converter 409 which is a tapped delay line.
- the use of this system and method of frequency generation yields a number of benefits, namely, high frequency resolution, broad frequency tuning range and low current drain, as compared with other DDS synthesizers.
- the DDS 205 also enables the system to provide both quadrature and differential signals.
- a major benefit in using the DDS 205 is spur mitigation through the intelligent selection of the mitigation frequency signal (F 2 ).
- the present invention provides a fractional non-harmonic frequency generation architecture with independent mitigation and LO frequency paths.
- the non-harmonic fractional relationship between the mitigation and LO frequencies enhances I/Q matching and IP 2 performance over a wide range of RF bandwidths.
- the digital nature of the frequency synthesizer allows for “dithering” or spreading capabilities of the mitigation frequency to reduce discrete harmonic spurious content that would otherwise be mixed into the base band signal.
- agile interference rejection enhancement allows very fast adjustment of the mitigation frequency in real time relative to the LO.
- spurious interference can be detected, e.g., degraded bit error rate (BER) in strong signal conditions where the mitigation frequency can be adjusted to a new frequency unrelated to the local oscillator while still receiving the desired signal in an attempt to eliminate the interference.
- BER degraded bit error rate
Abstract
Description
F LO(+ and −) =F ref /N1
F1=F ref /N2; and
F2=F ref /N3 where N1, N2 and N3 are real numbers.
F LO(+ or −) =F RF and N3=N2; and
-
- Where N3≠N2 then
F LO (+ or −) =F RF then F VLIF=(F2−F3); and
F LO ≠F RF, then F VLIF =+/−F RF −/+{F LO+/−(F2−F3)}
- Where N3≠N2 then
Claims (20)
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Cited By (16)
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---|---|---|---|---|
US20070189419A1 (en) * | 2006-02-10 | 2007-08-16 | Filipovic Daniel F | Conversion of multiple analog signals in an analog to digital converter |
US20080119158A1 (en) * | 2006-11-21 | 2008-05-22 | Filipovic Daniel F | Frequency changer circuits |
US20090079497A1 (en) * | 2007-09-21 | 2009-03-26 | Nanoamp Solutions, Inc. (Cayman) | Phase tuning techniques |
US20090197552A1 (en) * | 2008-01-07 | 2009-08-06 | Peter Kurahashi | Bandwidth tunable mixer-filter using lo duty-cycle control |
US20100112973A1 (en) * | 2008-11-04 | 2010-05-06 | Motorola, Inc. | Generation of a composite mitigation signalwith a desired spectral energy distrubution |
US7809349B1 (en) * | 2006-10-18 | 2010-10-05 | Rf Micro Devices, Inc. | Radio frequency filter using intermediate frequency impedance translation |
US20110076976A1 (en) * | 2008-05-23 | 2011-03-31 | Motorola, Inc. | Radio frequency receiver, wireless communication unit and method of operation |
US20130052975A1 (en) * | 2007-06-29 | 2013-02-28 | Aslamali A. Rafi | Rotating Harmonic Rejection Mixer |
US8768281B2 (en) | 2007-06-29 | 2014-07-01 | Silicon Laboratories Inc. | Method and apparatus for controlling a harmonic rejection mixer |
US8805396B1 (en) | 2013-03-15 | 2014-08-12 | Blackberry Limited | Statistical weighting and adjustment of state variables in a radio |
US8811538B1 (en) | 2013-03-15 | 2014-08-19 | Blackberry Limited | IQ error correction |
US8942656B2 (en) | 2013-03-15 | 2015-01-27 | Blackberry Limited | Reduction of second order distortion in real time |
US8983486B2 (en) | 2013-03-15 | 2015-03-17 | Blackberry Limited | Statistical weighting and adjustment of state variables in a radio |
CN104579335A (en) * | 2014-09-26 | 2015-04-29 | 中国人民解放军总参谋部第六十三研究所 | Frequency design method for frequency synthesizer |
US9197279B2 (en) | 2013-03-15 | 2015-11-24 | Blackberry Limited | Estimation and reduction of second order distortion in real time |
US10317535B2 (en) | 2016-03-31 | 2019-06-11 | Samsung Electronics Co., Ltd | Method and apparatus for second order intercept point (IP2) calibration |
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US7983371B2 (en) * | 2004-11-30 | 2011-07-19 | Freescale Semiconductor, Inc. | System and method for using programmable frequency offsets in a data network |
US7801504B2 (en) * | 2005-12-08 | 2010-09-21 | Qualcomm Incorporated | Common-gate common-source transconductance stage for RF downconversion mixer |
DE102009011795A1 (en) | 2009-03-05 | 2010-09-09 | Rohde & Schwarz Gmbh & Co. Kg | Synthesizer with adjustable, stable and reproducible phase and frequency |
EP2573936A1 (en) | 2011-09-23 | 2013-03-27 | Telefonaktiebolaget LM Ericsson (publ) | Mixer unit |
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Cited By (24)
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---|---|---|---|---|
US20070189419A1 (en) * | 2006-02-10 | 2007-08-16 | Filipovic Daniel F | Conversion of multiple analog signals in an analog to digital converter |
US8059758B2 (en) | 2006-02-10 | 2011-11-15 | Qualcomm, Incorporated | Conversion of multiple analog signals in an analog to digital converter |
US7809349B1 (en) * | 2006-10-18 | 2010-10-05 | Rf Micro Devices, Inc. | Radio frequency filter using intermediate frequency impedance translation |
US20080119158A1 (en) * | 2006-11-21 | 2008-05-22 | Filipovic Daniel F | Frequency changer circuits |
US8099072B2 (en) * | 2006-11-21 | 2012-01-17 | Qualcomm Incorporated | Frequency changer circuits |
US20130052975A1 (en) * | 2007-06-29 | 2013-02-28 | Aslamali A. Rafi | Rotating Harmonic Rejection Mixer |
US8774750B2 (en) | 2007-06-29 | 2014-07-08 | Silicon Laboratories Inc. | Method and apparatus for controlling a harmonic rejection mixer |
US8768281B2 (en) | 2007-06-29 | 2014-07-01 | Silicon Laboratories Inc. | Method and apparatus for controlling a harmonic rejection mixer |
US8725099B2 (en) * | 2007-06-29 | 2014-05-13 | Silicon Laboratories Inc. | Rotating harmonic rejection mixer |
US20090079497A1 (en) * | 2007-09-21 | 2009-03-26 | Nanoamp Solutions, Inc. (Cayman) | Phase tuning techniques |
US20090197552A1 (en) * | 2008-01-07 | 2009-08-06 | Peter Kurahashi | Bandwidth tunable mixer-filter using lo duty-cycle control |
US20110076976A1 (en) * | 2008-05-23 | 2011-03-31 | Motorola, Inc. | Radio frequency receiver, wireless communication unit and method of operation |
US8224280B2 (en) * | 2008-05-23 | 2012-07-17 | Motorola Solutions, Inc. | Radio frequency receiver, wireless communication unit and method of operation |
US8155615B2 (en) * | 2008-11-04 | 2012-04-10 | Motorola Solutions, Inc. | Generation of a composite mitigation signal with a desired spectral energy distrubution |
US20100112973A1 (en) * | 2008-11-04 | 2010-05-06 | Motorola, Inc. | Generation of a composite mitigation signalwith a desired spectral energy distrubution |
US8805396B1 (en) | 2013-03-15 | 2014-08-12 | Blackberry Limited | Statistical weighting and adjustment of state variables in a radio |
US8811538B1 (en) | 2013-03-15 | 2014-08-19 | Blackberry Limited | IQ error correction |
US8942656B2 (en) | 2013-03-15 | 2015-01-27 | Blackberry Limited | Reduction of second order distortion in real time |
US8983486B2 (en) | 2013-03-15 | 2015-03-17 | Blackberry Limited | Statistical weighting and adjustment of state variables in a radio |
US9197279B2 (en) | 2013-03-15 | 2015-11-24 | Blackberry Limited | Estimation and reduction of second order distortion in real time |
CN104579335A (en) * | 2014-09-26 | 2015-04-29 | 中国人民解放军总参谋部第六十三研究所 | Frequency design method for frequency synthesizer |
US10317535B2 (en) | 2016-03-31 | 2019-06-11 | Samsung Electronics Co., Ltd | Method and apparatus for second order intercept point (IP2) calibration |
US10775512B2 (en) | 2016-03-31 | 2020-09-15 | Samsung Electronics Co., Ltd | Method and apparatus for second order intercept point (IP2) calibration |
US11067702B2 (en) | 2016-03-31 | 2021-07-20 | Samsung Electronics Co., Ltd | Method and apparatus for second order intercept point (IP2) calibration |
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