|Publication number||US7106025 B1|
|Application number||US 11/068,196|
|Publication date||12 Sep 2006|
|Filing date||28 Feb 2005|
|Priority date||28 Feb 2005|
|Also published as||EP1696550A2, EP1696550A3, US20060192520|
|Publication number||068196, 11068196, US 7106025 B1, US 7106025B1, US-B1-7106025, US7106025 B1, US7106025B1|
|Inventors||Qiang Yin, Russel J. Kerkman, Richard A. Lukaszewski|
|Original Assignee||Rockwell Automation Technologies, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (13), Non-Patent Citations (2), Referenced by (40), Classifications (10), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The field of the invention is control systems for controlling the operation of AC motors.
A well known type of AC drive includes an AC-to-DC converter including a boost rectifier for converting three-phase AC source voltages to DC voltages on a DC bus. The DC bus interfaces the AC-to-DC converter to a DC-to-AC inverter, which is typically a three-phase bridge network of solid state switches, which are switched at high frequency to generate pulse width modulation (PWM) or other types of modulated low frequency power signals which are supplied to an AC motor. These systems generate a common mode voltage measured between a neutral in the motor and an electrical ground. These also generate common mode currents in part the result of parasitic capacitances between mechanical parts in the motor and ground, and between mechanical parts in the motor and the stator windings. It is desirable to attenuate or eliminate these common mode voltages to prevent interference that might trip fault protection devices and to reduce common mode currents in motor bearings that might reduce their service life. Passive circuits including filters and transformers have been employed to correct this problem, but with increased production costs and increased installation costs. A number of prior art publications have suggested modifications to inverter modulation methods to control the inverter common mode voltages. This approach has cost and manufacturing advantages over passive circuits.
The inverter switching states can be modeled with the aid of a space vector PWM (SVPWM) theory and diagram more fully described below. Two of the vectors in this theory are zero-voltage switching vectors (V0 and V7). Some prior art methods skip these vectors by using two active vectors that are 180 degrees out of phase. However, these modified modulation schemes require that dwell time (on time for the inverter switches) be calculated in real time.
The dead-time effect, where there is time delay between one phase voltage being turned on or off and the next phase being switched to the opposite state, has been investigated while using different modified modulation schemes. A null state switching sequence without zero-voltage switching vectors has been described in the art to be the optimal common-mode voltage reduction PWM technique. Also, a method to cope with the dead-time effects at the transition of two sectors in the direct-digital SVPWM switching sequence has been described in the art.
It would be advantageous to provide other common-mode voltage reduction methods for a PWM carrier-based modulation that remove the effects of dead time.
The present invention relates generally to methods for reducing the common mode voltage generated by a rectifier/inverter variable frequency drive system. This invention is more particularly applied in a preferred embodiment to modulation techniques based on carrier-based pulse width modulation (PWM) for common mode voltage reduction. The proposed common mode voltage reduction methods can be applied to carrier-based PWM without calculating the dwell time.
The invention more particularly comprises comparing respective pairs of the phase voltages to each other for selected time periods to determine a voltage difference, δ, and the voltage difference δ, is limited to an amount calculated by the expression:
where δ is a voltage difference function limit,
where Vbus is the dc link voltage and is also equal to the peak-to-peak amplitude of a carrier wave,
where Psw is a period of the carrier wave, and
where Td is a dead time that is predetermined for the switches in a power conversion device. Gating signals to switches for the three phases in the power conversion device are then delayed to produce the voltage difference and reduce the dead time effects in facilitating common mode voltages in a motor.
In a more specific embodiment, the invention can be carried out by a microelectronic CPU under control of a stored program routine.
The invention will enable one to reduce the peak-to-peak common mode voltage using a lower cost solution than the prior art.
The invention is applicable to power conversion devices, which include DC-to-AC inverters, AC-to-DC converters and active filter devices.
These and other objects and advantages of the invention will be apparent from the description that follows and from the drawings which illustrate embodiments of the invention, and which are incorporated herein by reference.
The controller 10 includes a microelectronic CPU 16 operating according to instructions in a control program 17 stored in memory. The program 17 includes instructions for performing regulation of a DC bus voltage and regulation of current supplied to the motor 15. The controller provides gating signals 19 to control the switching of the switches SW1–SW6 in the inverter 14.
The common mode voltage (CMV) is defined in expression 1) below as the voltage difference between a neutral point “n”, for example in the motor 15, and the ground “g” for the AC voltage supply 12. It is the sum of the voltage Vno between the midpoint “o” of the DC bus and a neutral point “n”, for example in the motor 15, and the voltage Vog between the midpoint “o” of the DC bus 13 and ground “g” for the AC voltage supply 12. The voltages Vno and Vog are three-phase voltages summed from the individual phase voltages of the motor 18 and the AC voltage supply 12 as shown in expressions 2) and 3) below.
CMV=V ng =V no +V og 1)
V no=(V uo +V vo +V wo)/3 2)
V og=−(V ao +V bo +V co)/3 3)
The frequency and amplitude of Vog is determined by the AC supply mains, which produces a positive 180 Hz (or 150 Hz) ripple waveform and negative 180 Hz (or 150 Hz) ripple waveform in the common mode voltage. Another part of CMV, Vno, is related to the inverter modulation, and its amplitude is shown in Table 1 below.
Common mode voltages for diode front-end variable
frequency drive system
State (G1, G3, G5)
0, 0, 0
1, 0, 0
1, 1, 0
0, 1, 0
0, 1, 1
0, 0, 1
1, 0, 1
1, 1, 1
An example of the waveform of both CMV and Vno for diode front-end VFD system is shown in
According to the space vector PWM model, there are eight available output voltage vectors (V0–V7) for both the boost rectifier and inverter as shown in
It is known in the art that the peak-to-peak amplitude of the common mode voltage generated by active front-end variable frequency drive system can be limited to no more than 1.33Vdc, as seen in
Some modified modulators for diode front-end VFD system have included a switching pattern modifier that does not select zero-voltage switching vectors (V0, V7) for the switching pattern of inverter control. The virtual zero states are created by using two active vectors that are 180 degree out of phase. As a result, the peak-to-peak amplitude of the common mode voltage can be significantly reduced.
Several common mode voltage reduction schemes have been proposed for carrier-based PWM without calculating the dwell time, which can be applied to the modulator of the diode front-end VFD system or to an active front-end VFD system.
The modified carrier-based PWM can be applied to the inverter modulator of the diode front-end VFD system, to significantly reduce the peak-to-peak amplitude of the common mode voltage. Due to the effects of dead time, there will be unexpected high amplitude pulses 25 of the common mode voltage, as shown in
There are no unexpected pulses of high amplitude (as seen in
As shown in
The same analysis can be applied to the dead-time effect in area S6_1_6 (before the transition from sector 6 to sector 1), as shown in
Dead-time effect analysis for those small areas after the transition of two sectors (e.g. S1_2_2) is presented in
To cancel the dead-time effect caused by the modified carrier-based PWM, the original three phase reference voltage Vu
As seen in
In block 55, the routine proceeds to determine if the time period is in zone 30 preceding the transition between sectors of the diagram in
The routine will then be repeated for the other pairs of phase reference voltages, Vv
As shown in
This has been a description of several preferred embodiments of the invention. It will be apparent that various modifications and details can be varied without departing from the scope and spirit of the invention, and these are intended to come within the scope of the following claims.
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|U.S. Classification||318/811, 318/801, 363/41|
|International Classification||H02M1/00, H02M7/5387|
|Cooperative Classification||H02P27/08, H02M7/53873, H02M2001/385|
|European Classification||H02M7/5387C2, H02P27/08|
|28 Feb 2005||AS||Assignment|
Owner name: ROCKWELL AUTOMATION TECHNOLOGIES, INC., OHIO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YIN, QIANG;KERKMAN, RUSSEL J.;LUKASZEWSKI, RICHARD;REEL/FRAME:016350/0948
Effective date: 20050228
|12 Mar 2010||FPAY||Fee payment|
Year of fee payment: 4
|12 Mar 2014||FPAY||Fee payment|
Year of fee payment: 8