|Publication number||US6946920 B1|
|Application number||US 10/339,115|
|Publication date||20 Sep 2005|
|Filing date||9 Jan 2003|
|Priority date||23 Feb 2000|
|Publication number||10339115, 339115, US 6946920 B1, US 6946920B1, US-B1-6946920, US6946920 B1, US6946920B1|
|Inventors||Timothy J. Williams, Jeffrey D. Wick|
|Original Assignee||Cypress Semiconductor Corp.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (41), Non-Patent Citations (7), Referenced by (9), Classifications (17), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a continuation of U.S. Ser. No. 09/966,626 filed Sep. 28, 2001 now U.S. Pat. No. 6,525,616, which is a continuation of U.S. Ser. No. 09/511,020 filed Feb. 23, 2000, now U.S. Pat. No. 6,297,705.
The present application may relate to application Ser. No. 09/511,019, filed Feb. 23, 2000, now U.S. Pat. No. 6,407,641, which is hereby incorporated by reference in its entirety.
The present invention relates to a method and/or architecture for locking a data steam generally and, more particularly, to a method and/or architecture for locking an oscillator to a data stream.
Conventional approaches for locking a data stream use Phase Lock Loops (PLL) and/or Delay Lock Loops (DLL) to lock or match a clock to an incoming data stream.
Such approaches typically require a very long training sequence and/or a continuous stream of data. Either requirement is incompatible with data communication systems like the Universal Serial Bus (USB), where the data packets can be short and bursty. For USB devices in particular, data may be present for only a very small percentage of the time, which could be less than 1%.
Delay Lock Loops and/or Phase Lock Loops can also suffer from the requirement of (i) long training sequences, (ii) requiring continuous input (e.g., cannot handle bursty data), and/or (iii) may need a precision timing component.
The present invention concerns an apparatus comprising a control circuit and a first circuit. The first circuit may be configured to generate a calibration signal in response to an adjustment signal and a first control signal. The control circuit may be configured to generate (i) the first control signal, (ii) a second control signal and (iii) the adjustment signal in response to a rate of an input signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for locking an incoming data stream that may (i) precisely lock to a rate of the incoming data stream without an external precision timing element (e.g., without crystals, resonators, etc.), (ii) allow incoming data traffic to provide precision timing, (iii) provide multiple tuning phases during a single packet, and/or (iv) tune quickly (e.g., within one data packet).
These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:
The control circuit 102 generally comprises a control logic block (or circuit) 103 and a counter block (or circuit) 106. The control logic block 103 may have an output 118 that may present an adjustment signal (e.g., C/F) and an output 119 that may present a control signal (e.g., CNTRS/S). The counter 106 may have an input 120 that may receive the signal C/F and an input 122 that may receive the signal CNTRS/S.
The oscillator logic circuit 104 may have an input 126 that may receive the signal CNTR, an input 128 that may receive the signal FACTOR and an output 130 that may present the signal OUT. In one example, the signal FACTOR may be implemented as a correction signal. However, the signal FACTOR may be implemented as any appropriate signal in order to meet the criteria of a particular implementation. The circuit 100 may perform measurements on the incoming data stream DATA that may produce the correction (or adjustment) signal FACTOR. The signal FACTOR may alter the frequency of oscillation of the signal OUT to match a multiple of a rate of the incoming data stream DATA. The circuit 100 may be a building block in a system (or chip) designed to automatically modify and lock the frequency of oscillation of the signal OUT to a multiple of the rate of the incoming data signal DATA. An example of such an implementation may be found in applications such as the Universal Serial Bus (USB) (e.g., the Universal Serial Bus Specification 1.1, published Sep. 23, 1998, which is hereby incorporated by reference in its entirety).
The circuit 100 may tune the oscillator logic 104 to match a multiple of the data rate of the incoming signal DATA. The circuit 100 may be implemented without precision timing elements.
The oscillator control block 140 generally comprises an oscillator setting block 160 and an adder block 162. The adder block 162 may have an input 163 that may receive the signal FACTOR. The oscillator setting block 160 may have an input 164 that may receive the signal CNTR, an input 166 that may receive a signal (e.g., ADD) and an output 168 that may present a signal (e.g., ST) to an input 169 of the adder 162. The adder 162 may present the signal ADD in response to the signal FACTOR and the signal ST.
Certain data communication systems require a precise local clock for accurate transmission (e.g., 1.5% accuracy in USB applications) and proper reception of incoming data. The circuit 100 may be implemented with a look-up table (as compared with conventional circuits that use a PLL). The look-up table 152 generally stores a fixed table of known characters that may determine how to adjust the frequency of oscillation of the signal OUT. The signal FACTOR may be an offset value that may control an adjustment in the frequency of oscillation of the signal OUT.
The circuit 100 may be used for generating the oscillator update signal DIGOUT by using the counter circuit 150 to calibrate the rate of oscillation of the signal OUT in response to the data rate of the incoming data stream DATA. Packet information (in the example of USB applications) may be used to distinguish appropriate data packets and/or key transitions. The look-up table 152 may hold correction terms based on interval counts and may generate the signal FACTOR that may be used to tune the frequency of oscillation of the signal OUT. The circuit 100 may be used to determine and adjust the frequency of oscillation of the signal OUT to be fixed to a multiple of the data rate of the signal DATA. The circuit 100 may be used to recover data without the conventional requirement of a crystal based oscillator or other external precision timing element.
Edges in the signal DATA may be recognized by the control circuit 102 to start and end various events. For example, during the early part of a data packet of the signal DATA, a coarse tuning may be performed by the signal C/F. The coarse tuning may involve running the counter 150 for a pre-determined number of data edges (e.g., in the case of USB, this may be implemented to take place during the synchronizing phase where edges occur every bit time). After the target number of data bit times have passed, the counter circuit 150 is generally stopped.
If the clock signal OUT matches (e.g., is a multiple of) the rate of the signal DATA, the count will equal the oversampling rate of the signal OUT times the number of bit-times in the measurement. If the signal OUT is at the ideal value, the counter 150 will end at the target value, plus or minus an error due to such factors as jitter or phase error in the incoming data stream DATA, which may give an inherent ±1 count uncertainty.
The output of the counter 150 may be fed directly to the look-up table 152 to find a correction factor for the particular rate of oscillation of the signal OUT. The value of the signal FACTOR may then be added to the present setting to produce a coarsely corrected frequency of oscillation. The new setting may be applied to the oscillator 142 to generate the updated frequency of the signal OUT. The new setting may remain until a subsequent adjustment is made, if such a subsequent adjustment is made.
Such a process may be repeated over a longer portion of the packet in order to achieve greater resolution in the correction term. The control logic block 103 may use known edges in the incoming data signal DATA to start and stop the counter block 150 another time, in one example, over a longer time period. The output of the counter 150 may then be directed to a fine-tune portion of lookup tables 152. The value may then be added (or subtracted) from the oscillator frequency setting via the signal DIGOUT to produce the final frequency of oscillation of the signal OUT.
The control block 102 may also receive inputs from other circuitry that may provide useful information about the incoming data packets (e.g. whether a particular packet is erroneous or not, what portion of a particular packet is presently arriving, etc.) In one example, such information could be built into the control block 103. In the case of USB, the USB Serial Interface Engine (SIE), already present for USB processing, may be used to supply information to the control block 103.
Error checking may be performed during the coarse and or fine tuning to avoid false tuning on noisy signals. Tuning may be limited (e.g., by information from the SIE) to certain appropriate types of data packets. For example, in USB, the appropriate data packets may be limited to token packets addressed to the device. In one example, the coarse tuning may occur on various packets. However, the fine tuning may be implemented, in one example, to occur during a token packet addressed to the device.
The circuit 100 may be tuned quickly (e.g., within one data packet). The circuit 100 may enable circuits that receive the signal OUT to run without precision timing elements (e.g., without crystals, resonators, etc.). Various options may be implemented for the tuning phases of the circuit 100. For example, in place of the coarse/fine tuning described, the circuit 100 may be implemented with only one tuning phase with an increased accuracy. Alternatively, more than two tuning phases may be implemented to meet the design criteria of a particular implementation.
Additionally, in another example, some type of averaging may be implemented across several packets to reduce the number (or size) of particular frequency adjustments.
The present invention may provide a key block that may be used in connection with the oscillator logic block 104. The present invention may provide a system cost saving by eliminating precision timing components (e.g., crystal, resonator, etc.) in data communications systems. While particular aspects of the present invention have been described in the context of USB applications, other applications may also be implemented. The circuit 100 may be used to achieve demanding cost targets, such as designing low-cost mouse controllers.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4061987||22 Feb 1977||6 Dec 1977||Nippon Gakki Seizo Kabushiki Kaisha||Voltage-controlled type oscillator|
|US4272760||10 Apr 1979||9 Jun 1981||Burr-Brown Research Corporation||Self-calibrating digital to analog conversion system and method|
|US4344067||21 Nov 1979||10 Aug 1982||Motorola, Inc.||Analog to digital converter and method of calibrating same|
|US4689740||2 Nov 1981||25 Aug 1987||U.S. Philips Corporation||Two-wire bus-system comprising a clock wire and a data wire for interconnecting a number of stations|
|US4692718||31 Mar 1986||8 Sep 1987||U.S. Philips Corporation||Tunable astable multivibrator with buffer transistors|
|US4868525||23 Sep 1988||19 Sep 1989||Dallas Semiconductor Corporation||Temperature-stabilized oscillator|
|US4947169||24 Oct 1989||7 Aug 1990||Burr-Brown Corporation||Dummy/trim DAC for capacitor digital-to-analog converter|
|US5140197||13 Aug 1990||18 Aug 1992||Dallas Semiconductor Corporation||Filtered detection plus propagated timing window for stabilizing the switch from crystal to ring oscillator at power-down|
|US5150079||18 Jun 1991||22 Sep 1992||Dallas Semiconductor Corporation||Two-mode oscillator|
|US5175884||1 Jun 1990||29 Dec 1992||Motorola, Inc.||Voltage controlled oscillator with current control|
|US5200751||26 Jun 1989||6 Apr 1993||Dallas Semiconductor Corp.||Digital to analog converter using a programmable logic array|
|US5304955||19 Nov 1992||19 Apr 1994||Motorola, Inc.||Voltage controlled oscillator operating with digital controlled loads in a phase lock loop|
|US5319370||31 Aug 1992||7 Jun 1994||Crystal Semiconductor, Inc.||Analog-to-digital converter with a continuously calibrated voltage reference|
|US5428319||29 Nov 1993||27 Jun 1995||Motorola, Inc.||Method and apparatus for providing a modified temperature compensation signal in a TCXO circuit|
|US5440305||31 Aug 1992||8 Aug 1995||Crystal Semiconductor Corporation||Method and apparatus for calibration of a monolithic voltage reference|
|US5546433||21 Mar 1995||13 Aug 1996||National Semiconductor Corporation||Digital phase lock loop having frequency offset cancellation circuitry|
|US5552748||7 Jun 1995||3 Sep 1996||American Microsystems, Inc.||Digitally-tuned oscillator including a self-calibrating RC oscillator circuit|
|US5559502||14 Jan 1993||24 Sep 1996||Schutte; Herman||Two-wire bus system comprising a clock wire and a data wire for interconnecting a number of stations and allowing both long-format and short-format slave addresses|
|US5563553||15 Aug 1995||8 Oct 1996||Sigmatel Inc.||Method and apparatus for a controlled oscillation that may be used in a phase locked loop|
|US5565819||11 Jul 1995||15 Oct 1996||Microchip Technology Incorporated||Accurate RC oscillator having modified threshold voltages|
|US5583501||24 Aug 1994||10 Dec 1996||Crystal Semiconductor Corporation||Digital-to-analog converter with digital linearity correction|
|US5594612||24 Aug 1994||14 Jan 1997||Crystal Semiconductor Corporation||Analog-to-digital converter with digital linearity correction|
|US5604466||28 Nov 1994||18 Feb 1997||International Business Machines Corporation||On-chip voltage controlled oscillator|
|US5666118||30 Jul 1996||9 Sep 1997||International Business Machines Corporation||Self calibration segmented digital-to-analog converter|
|US5668506||23 May 1996||16 Sep 1997||Kabushiki Kaisha Meidensha||Temperature compensated crystal oscillator|
|US5670915||24 May 1996||23 Sep 1997||Microchip Technology Incorporated||Accurate RC oscillator having peak - to - peak voltage control|
|US5682049||2 Aug 1995||28 Oct 1997||Texas Instruments Incorporated||Method and apparatus for trimming an electrical value of a component of an integrated circuit|
|US5686863||29 Sep 1995||11 Nov 1997||Dallas Semiconductor Corp.||Tunable tone control circuit and a device and method for tuning the RC constants|
|US5689196||1 Dec 1995||18 Nov 1997||U.S. Philips Corporation||Circuit comprising a data communication bus|
|US5726597||30 Aug 1996||10 Mar 1998||Motorola, Inc.||Method and circuit for reducing offset voltages for a differential input stage|
|US5796312||24 May 1996||18 Aug 1998||Microchip Technology Incorporated||Microcontroller with firmware selectable oscillator trimming|
|US5818370||28 Sep 1993||6 Oct 1998||Crystal Semiconductor Corporation||Integrated CODEC with a self-calibrating ADC and DAC|
|US5825317||7 Apr 1997||20 Oct 1998||Motorola, Inc.||Digital-to-analog converter and method of calibrating|
|US5898345||14 Jul 1997||27 Apr 1999||Matsushita Electric Industrial Co., Ltd.||Oscillator circuit with first and second frequency control elements|
|US5933058||22 Nov 1996||3 Aug 1999||Zoran Corporation||Self-tuning clock recovery phase-locked loop circuit|
|US6191660||24 Mar 1999||20 Feb 2001||Cypress Semiconductor Corp.||Programmable oscillator scheme|
|US6407641||23 Feb 2000||18 Jun 2002||Cypress Semiconductor Corp.||Auto-locking oscillator for data communications|
|US6525616 *||28 Sep 2001||25 Feb 2003||Cypress Semiconductor Corp.||Circuit for locking an oscillator to a data stream|
|WO1996017305A2||8 Nov 1995||6 Jun 1996||Philips Electronics Nv||Circuit comprising a data communication bus|
|WO1998034376A2||12 Jan 1998||6 Aug 1998||Koninkl Philips Electronics Nv||Communications bus using different transmission rates|
|WO1999009712A2||17 Dec 1998||25 Feb 1999||Koninkl Philips Electronics Nv||Electronic apparatus with a bus|
|1||"Universal Serial Bus Specification", Revision 1.1, Sep. 23, 1998, pp. 1-311.|
|2||A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2-mum CMOS, By: Beomsup Kim et al., Journal of Solid-State Circuits, vol. 25, No. 6, Dec. 1990, pp. 1385-1394.|
|3||An Analog PLL-Based Clock and Data Recovery Circuit with High Input Jitter Tolerance, By: Sam Yinshang Sun, Reprinted from IEEE Journal of Solid-State Circuits, vol. SC-24, pp. 383-385, Apr. 1989.|
|4||Cy7C63221/31 enCoRe(TM) USB Low Speed USB Peripheral Controller, Cypress Semiconductor Corp., Feb. 2000-Revised Apr. 11, 2000, pp. 1-43.|
|5||CY7C63722/23 CY7C63742/43 enCoRe(TM) USB Combination Low-Speed USB & PS/2 Peripheral Controller, Cypress Semiconductor Corp., Feb. 2000- Revised Apr. 11, 2000, pp. 1-51.|
|6||Micropower CMOS Temperature Sensor with Digital Output, By: Anton Bakker et al., 1996 IEEE.|
|7||WP 3.5: An Integrated Time Reference, By: Robert A. Blauschild, ISSCC94/Session 3, Analog Techniques/Paper WP 3.5, 1994.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7350094 *||17 Sep 2004||25 Mar 2008||Genesys Logic, Inc.||Method and device for ultrawideband frequency tracking|
|US7809973||16 Nov 2005||5 Oct 2010||Cypress Semiconductor Corporation||Spread spectrum clock for USB|
|US8140882||18 Feb 2009||20 Mar 2012||Genesys Logic, Inc.||Serial bus clock frequency calibration system and method thereof|
|US8407508 *||16 Sep 2010||26 Mar 2013||Genesys Logic, Inc.||Serial bus clock frequency calibration system and method thereof|
|US8645598||14 Sep 2012||4 Feb 2014||Cypress Semiconductor Corp.||Downstream interface ports for connecting to USB capable devices|
|US20050057295 *||17 Sep 2004||17 Mar 2005||Wen-Fu Tsai||Method and device for ultrawideband frequency tracking|
|US20110016346 *||16 Sep 2010||20 Jan 2011||Genesys Logic, Inc.||Serial bus clock frequency calibration system and method thereof|
|US20120066418 *||20 May 2010||15 Mar 2012||Chronologic Pty. Ltd.||Synchronous network of superspeed and non-superspeed usb devices|
|EP2093926A1 *||1 Feb 2008||26 Aug 2009||Thomson Licensing||Method of receiving and method of sending data over a network|
|U.S. Classification||331/44, 331/1.00A, 331/17, 327/166, 331/34, 327/159|
|International Classification||H04L7/00, H04L7/033, G01R23/00, H04J3/06, H03L7/00|
|Cooperative Classification||H03L7/00, H04L7/0083, H04L7/033, H04J3/0632|
|European Classification||H04L7/00R2, H03L7/00|
|30 Mar 2009||REMI||Maintenance fee reminder mailed|
|5 Aug 2009||SULP||Surcharge for late payment|
|5 Aug 2009||FPAY||Fee payment|
Year of fee payment: 4
|7 Feb 2013||FPAY||Fee payment|
Year of fee payment: 8
|13 Jun 2014||AS||Assignment|
Owner name: CYPRESS SEMICONDUCTOR CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WILLIAMS, TIMOTHY J.;WICK, JEFFREY D.;REEL/FRAME:033103/0177
Effective date: 20000223
|21 Mar 2015||AS||Assignment|
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., NEW YORK
Free format text: SECURITY INTEREST;ASSIGNORS:CYPRESS SEMICONDUCTOR CORPORATION;SPANSION LLC;REEL/FRAME:035240/0429
Effective date: 20150312