US6933617B2 - Wafer interposer assembly - Google Patents
Wafer interposer assembly Download PDFInfo
- Publication number
- US6933617B2 US6933617B2 US10/373,413 US37341303A US6933617B2 US 6933617 B2 US6933617 B2 US 6933617B2 US 37341303 A US37341303 A US 37341303A US 6933617 B2 US6933617 B2 US 6933617B2
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- wafer
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- interposer assembly
- die
- redistribution layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/1147—Manufacturing methods using a lift-off mask
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L2924/01075—Rhenium [Re]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/31504—Composite [nonstructural laminate]
- Y10T428/31511—Of epoxy ether
Definitions
- the present invention relates generally to the field of integrated circuits, and more particularly, to a wafer interposer assembly and a system for building the same.
- this background of the present invention will be described with reference to building a semiconductor wafer-interposer, as an example.
- engineers have worked diligently to produce electronic devices that are smaller and more functional than the previous versions of the devices.
- Advances in manufacturing techniques allow more components to be integrated into a smaller semiconductor die.
- More components within the die enable engineers to design devices having greater efficiency and more convenient functions.
- increasing the number of components within the die can adversely affect the size and manufacturing costs of the device.
- space efficiency may be improved by using a semiconductor wafer-interposer, it is difficult to attached a separate interposer to a semiconductor wafer and maintain close dimensional tolerances. Close tolerance for package height is a requirement for many applications. Typically, thick packages are more reliable and have lower manufacturing costs. In contrast, thin packages may be required for applications where space and weight are at a premium. Additionally, manufacturing a thin package is usually costly because smaller components are more difficult to process and require more precise machinery.
- the footprint of the resulting semiconductor package is almost the size of the die, which is as small as the package can be without making a smaller die.
- the height of the package cannot be as accurately controlled because it varies according to the method used to construct the wafer-interposer.
- Another costly manufacturing process associated with assembling semiconductor packages having interposers is aligning the die with the interposer.
- the contact pads on the die and the interposer must be aligned and connected to result in a functional semiconductor package. Aligning minute contacts between the die and interposer is an expensive and time intensive process. Current available methods of alignment slow the manufacturing process and increase costs.
- the present invention overcomes the existing manufacturing limitations and inefficiencies in the art by providing a wafer interposer assembly and system for building the same.
- the wafer interposer assembly includes a semiconductor wafer having a die and a redistribution layer pad, electrically connected to the die.
- An epoxy layer is deposited on the surface of the redistribution layer pad and the die.
- An opening is positioned through the epoxy layer and an interposer pad is positioned in the opening in electrical contact with the redistribution layer pad.
- the semiconductor wafer of the wafer interposer assembly includes a plurality of die.
- the redistribution layer pad may comprise a material reflective to laser frequencies, a material compatible with solder, or a material compatible with conductive polymer.
- the epoxy layer may be disposed on the surface by a deposition process selected from the group consisting of spraying, rolling and vapor deposition.
- the epoxy layer may comprise a nonconductive material having a coefficient of thermal expansion similar to the wafer.
- the height of the cured epoxy layer may be at least the length of the redistribution layer pad.
- the curing may involve a processes selected from the group consisting of heat processes and chemical processes.
- the epoxy layer is trimmed by a laser process to achieve a flat surface and controlled height.
- the interposer pad may comprise a conductive material that is positioned in the opening which may be formed by a laser process. An epoxy coat is disposed on a backside of the wafer.
- the present invention is directed to a system for building a wafer interposer assembly.
- a depositor deposits an epoxy layer onto the surface of a semiconductor wafer having a plurality of die and a plurality of redistribution layer pads electrically connected to each die.
- a laser operates relative to the semiconductor wafer to trim the epoxy layer to a flat surface and controlled height and to bore a plurality of openings in alignment with the redistribution layer pads through the epoxy layer.
- a screener screens an interposer pad into the openings and into electrical contact with the redistribution layer pads.
- the depositor is selected from the group consisting of spraying depositors, rolling depositors and vapor depositors.
- the laser may operate under the control of a controller that comprises a computer-numerical-control machine that maneuvers and operates the laser in three dimensions.
- a curing means employing a heat process or chemical process may be employed for curing the epoxy layer.
- the screener may screen a conductive material into the openings to form the interposer pads.
- An alignment mark may be position on the semiconductor wafer to provide orientation to the laser.
- the depositor may deposit an epoxy coat on the backside of the semiconductor wafer and the laser may adjust the height of the epoxy coat.
- FIG. 1A is a perspective view of a semiconductor wafer in accordance with certain embodiments of the present invention.
- FIG. 1B is a cross-sectional view of the semiconductor wafer of FIG. 1A taken along line 1 B— 1 B.
- FIG. 2 is a cross-sectional view of a wafer-interposer assembly in accordance with certain embodiments of the present invention
- FIG. 3A is a cross-sectional view of a wafer-interposer assembly in accordance with certain embodiments of the present invention.
- FIG. 3B is a cross-sectional view of a wafer-interposer assembly in accordance with certain embodiments of the present invention.
- FIG. 4 is a cross-sectional view of a wafer-interposer assembly in accordance with certain embodiments of the present invention.
- FIG. 5 is a cross-sectional view of a wafer-interposer assembly in accordance with certain embodiments of the present invention.
- FIG. 6 is a cross-sectional view of a wafer-interposer assembly in accordance with certain embodiments of the present invention.
- Interposers allow greater freedom to die designers because the layout of a die and its contact pads can be defined according to the interaction of the functional elements of the die rather than according to the standardization requirements.
- the interposer can be designed with a standardized layout of contact pads on its upper surface and can electrically connect each die pad to a corresponding interposer contact pad without an interposer pad being directly above its corresponding die pad. Not only does the interposer provide for standardized interconnection, it also provides for the use of standard test hardware, software, cabling and connectors compatible with existing industry infrastructure.
- interposer An additional advantage of the interposer is that more than one interposer can be designed for each wafer. A manufacturer can then, by substituting a different interposer, modify the layout of the interposer pads to conform to a different layout or packaging standard. Alternatively, if the die and interposer are designed for modularity, a single interposer design may be useful on more than one chip design. A specific interposer design will typically be necessary for each unique die design.
- FIG. 1A depicts a semiconductor wafer 10 having a plurality of die including a die 11 , which may have many circuits within its structure.
- the wafer 10 may have several identical or different dice 11 , which eventually may be separated or diced into individual semiconductor chips. For clarity of illustration, dashed lines are used to represent the kerfs between die 11 .
- One or more die pads 12 electrically contact the circuits within die 11 .
- An underbump metalization may be deposited onto the die pads 12 .
- a redistribution layer (RDL) may then be deposited onto the wafer 10 .
- RDL redistribution layer
- One or more known semiconductor processes such as photolithography or etching for example, may be used to process the RDL into RDL pads 13 .
- the RDL pads 13 may then be connected to the die pads 12 by connectors 14 .
- the RDL pads 13 provide an interface between the circuits of the die 11 and an interposer.
- Each of the die pads 12 corresponds to a particular RDL pad 13 .
- the RDL pads 13 may be a material that is reflective to laser frequencies to facilitate subsequent processes of the present invention.
- the RDL pads 13 may also be made from a material that is compatible with solder or conductive polymer. Copper, for example, may be one suitable material for RDL pads 13 .
- Other materials that are electrically conductive and compatible with solder or conductive polymers may also be used for the RDL pads 13 and will be apparent to those having ordinary skill in the art.
- the layout and size of the RDL pads 13 may have the same configuration as the pad configuration of a finished semiconductor package. Designing the configuration of the RDL pads 13 to match the requirements of the finished package increases manufacturing efficiency. Multiple, identical dice 11 may be efficiently produced in large quantities and used in a variety of different applications by simply changing the configuration of the RDL pads 13 . Efficiency increases because the same die 11 may be used for multiple applications that require different semiconductor package configurations.
- the epoxy 20 may be applied using any of many semiconductor chip manufacturing techniques known in the art. Spraying, rolling or vapor deposition, for example, is used to apply the epoxy 20 to the wafer 10 .
- the epoxy 20 may be non-conductive and may have a coefficient of thermal expansion similar to the wafer 10 .
- the epoxy 20 may also be able to withstand the heat required to re-flow solder or other conductive material that is applied to the wafer 10 in subsequent processes.
- An epoxy material suitable for underfill, for example, may be used.
- the epoxy 20 should be applied or deposited to a height that exceeds the upper surface of the RDL pads 13 by at least the diameter of the RDL pads 13 .
- the epoxy 20 is then cured as required by the particular properties of the epoxy 20 .
- Some curing methods may include infrared heat or chemical processes, for example.
- the cured epoxy 20 may have a relatively rough or undulating surface, as best seen in FIG. 3 A. However, a desirable minimum thickness is one that extends past the upper surface of the RDL pads 13 by approximately the diameter of the RDL pads 13 .
- FIG. 3B depict a trimming process that may vaporize the top of the epoxy 20 to achieve a very flat surface and controlled height.
- An exaggerated surface of the epoxy 20 is shown in FIG. 3 A.
- the thinnest point of the epoxy 20 should be approximately at least as thick as the diameter 34 of the RDL pad 13 plus the height of the RDL pad 13 .
- a controller may be used to operate a laser 25 to vaporize selected areas of the epoxy 20 .
- the controller may be the type of controller utilized for computer-numerical-control (CNC) machining, which maneuvers and operates a tool in three dimensions.
- CNC computer-numerical-control
- the controller maneuvers the laser 25 about the wafer 10 and selectively vaporizes portions of the epoxy 20 .
- the process of removing the epoxy 20 will be described in further detail below.
- the laser 25 may be aimed at initial elevation 31 and generally parallel to the surface of the wafer 10 .
- This initial elevation 31 of the laser 25 may be slightly above the highest point of the epoxy 30 .
- the controller begins sweeping the laser 25 across the wafer 10 and slowly lowers the laser 25 through excess epoxy 30 to final elevation 32 .
- the laser 25 impinges on high points of the surface of the epoxy 20 and vaporizes the excess epoxy 30 as the laser 25 sweeps across the entire wafer 10 .
- the elevation 32 is at a point where the distance 33 between the surface of the epoxy 20 and the surface of the RDL pads 13 is approximately the diameter 34 of the RDL pads 13 .
- the distance 33 may be varied to optimize the aspect ratio for conductor screening, which will be described below.
- the laser 25 may also be used to create openings 40 , the locations of which are represent by dashed lines, in the epoxy 20 as depicted in FIG. 4 .
- the laser 25 is first oriented to the wafer 10 using alignment marks 35 on the wafer 10 . If the alignment marks 35 have been covered during the epoxy coating process, a rough alignment can be made using a flat spot or other reference point on the wafer 10 .
- the laser 25 may be used to etch away the epoxy 20 around the alignment marks 35 . After the alignment marks 35 are located, the location of RDL pads 13 can be very accurately determined by using the alignment marks 35 in conjunction with a coordinate map of the RDL pads 13 .
- the laser 25 creates the openings 40 by vaporizing the epoxy 30 .
- the laser 25 vaporizes the epoxy 20 down to the surface of the RDL pads 13 but does not affect the RDL pads 13 because of the reflective properties of the RDL pads 13 .
- This process is similar to using the laser 25 as a drill.
- the controller determines drilling locations, which are generally above the RDL pads 13 , by moving the laser 25 relative to the alignment marks 35 .
- the laser 25 may then be activated to vaporize the epoxy 20 and “drill” the openings 40 .
- the RDL pads 13 act as “drill stops” because the RDL pads 13 reflect the laser 25 instead of being vaporized by the laser 25 .
- FIG. 5 shows the openings 40 filled with a conductive material by screening, for example, to form interposer pads 50 .
- the aspect ratio of the openings 40 may be adjusted so that the conductive material easily flows into the openings 40 and adequately fills the openings without leaving any voids. Also, the aspect ratio facilitates the conductive material filling the openings 40 and contacting the RDL pads 13 .
- the conductive material may be solder, conductive polymer or any other suitable material and may be screened into the openings 40 .
- the conductive material forms a permanent and reliable electrical connection to RDL pads 13 .
- the conductive material is re-flowed or cured. After re-flowing or curing, the wafer-interposer is at minimum thickness. If a thicker package is required or if it is desirable to protect the backside of the die 11 , then an epoxy coat can be applied to the back of the wafer 10 , as best seen in FIG. 6 .
- the interposer pads 50 may be used as contacts for testing and burn-in of the wafer 10 .
- the interposer pads 50 may also be used to connect and attach the resulting device to a printed circuit board or other structure after the interposer is diced into individual circuits.
- FIG. 6 depicts the wafer-interposer having an additional layer of epoxy 60 , which may be added to the backside of the wafer 10 .
- the technique for applying the epoxy 60 , the composition of the epoxy 60 and the method for creating a dimensionally precise surface is similar to the process for the front side of the wafer 10 , which has been described above.
- the thickness 61 of the wafer-interposer may be adjusted by removing and leveling the epoxy 60 using the laser 25 . Because there are no electrical contacts on the backside of the wafer 10 , the thickness 61 may be adjusted without concern for maintaining a particular aspect ratio. After construction of the wafer-interposer is complete, testing and burn-in may be performed while all circuits are in wafer form. After final testing, the wafer-interposer may be diced into individual components.
Abstract
Description
Claims (29)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US10/373,413 US6933617B2 (en) | 2000-12-15 | 2003-02-24 | Wafer interposer assembly |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US09/738,228 US6524885B2 (en) | 2000-12-15 | 2000-12-15 | Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniques |
US10/373,413 US6933617B2 (en) | 2000-12-15 | 2003-02-24 | Wafer interposer assembly |
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US09/738,228 Division US6524885B2 (en) | 2000-12-15 | 2000-12-15 | Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniques |
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US20030148108A1 US20030148108A1 (en) | 2003-08-07 |
US6933617B2 true US6933617B2 (en) | 2005-08-23 |
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US09/738,228 Expired - Fee Related US6524885B2 (en) | 2000-12-15 | 2000-12-15 | Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniques |
US10/373,413 Expired - Lifetime US6933617B2 (en) | 2000-12-15 | 2003-02-24 | Wafer interposer assembly |
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Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050082682A1 (en) * | 2003-10-21 | 2005-04-21 | Advanced Semiconductor Engineering, Inc. | Prevention of contamination on bonding pads of wafer during SMT |
US20070004085A1 (en) * | 2005-06-29 | 2007-01-04 | Brusso Patricia A | Underfill device and method |
US20120206892A1 (en) * | 2011-02-10 | 2012-08-16 | Apple Inc. | Circular interposers |
US20120243092A1 (en) * | 2011-03-24 | 2012-09-27 | Moser Baer India Limited | Barrier layer and a method of manufacturing the barrier layer |
US20130148322A1 (en) * | 2011-02-10 | 2013-06-13 | Apple Inc. | Interposer connectors with alignment features |
US8791536B2 (en) | 2011-04-28 | 2014-07-29 | Aptina Imaging Corporation | Stacked sensor packaging structure and method |
US9033740B2 (en) | 2011-04-25 | 2015-05-19 | Apple Inc. | Interposer connectors |
US9041840B2 (en) | 2012-08-21 | 2015-05-26 | Semiconductor Components Industries, Llc | Backside illuminated image sensors with stacked dies |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6392428B1 (en) | 1999-11-16 | 2002-05-21 | Eaglestone Partners I, Llc | Wafer level interposer |
US6812048B1 (en) * | 2000-07-31 | 2004-11-02 | Eaglestone Partners I, Llc | Method for manufacturing a wafer-interposer assembly |
US6537831B1 (en) | 2000-07-31 | 2003-03-25 | Eaglestone Partners I, Llc | Method for selecting components for a matched set using a multi wafer interposer |
US6815712B1 (en) | 2000-10-02 | 2004-11-09 | Eaglestone Partners I, Llc | Method for selecting components for a matched set from a wafer-interposer assembly |
US6686657B1 (en) | 2000-11-07 | 2004-02-03 | Eaglestone Partners I, Llc | Interposer for improved handling of semiconductor wafers and method of use of same |
US6529022B2 (en) * | 2000-12-15 | 2003-03-04 | Eaglestone Pareners I, Llc | Wafer testing interposer for a conventional package |
US6673653B2 (en) | 2001-02-23 | 2004-01-06 | Eaglestone Partners I, Llc | Wafer-interposer using a ceramic substrate |
TWI232560B (en) * | 2002-04-23 | 2005-05-11 | Sanyo Electric Co | Semiconductor device and its manufacture |
TWI229435B (en) * | 2002-06-18 | 2005-03-11 | Sanyo Electric Co | Manufacture of semiconductor device |
TWI227550B (en) * | 2002-10-30 | 2005-02-01 | Sanyo Electric Co | Semiconductor device manufacturing method |
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US20030148108A1 (en) | 2003-08-07 |
US6524885B2 (en) | 2003-02-25 |
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