US6819622B2 - Write and erase protection in a synchronous memory - Google Patents
Write and erase protection in a synchronous memory Download PDFInfo
- Publication number
- US6819622B2 US6819622B2 US10/762,061 US76206104A US6819622B2 US 6819622 B2 US6819622 B2 US 6819622B2 US 76206104 A US76206104 A US 76206104A US 6819622 B2 US6819622 B2 US 6819622B2
- Authority
- US
- United States
- Prior art keywords
- memory
- register
- volatile
- data
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
- G11C16/225—Preventing erasure, programming or reading when power supply voltages are outside the required ranges
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- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Read Only Memory (AREA)
Abstract
Description
TABLE 1 |
BURST DEFINITION |
Order of Accesses Within a Burst |
Burst | Starting Column | Type = | Type = |
Length | Address | Sequential | Interleaved |
A0 | |||||
2 | 0 | 0-1 | 0-1 | ||
1 | 1-0 | 1-0 | |||
A1 | A0 | ||||
4 | 0 | 0 | 0-1-2-3 | 0-1-2-3 | |
0 | 1 | 1-2-3-0 | 1-0-3-2 | ||
1 | 0 | 2-3-0-1 | 2-3-0-1 | ||
1 | 1 | 3-0-1-2 | 3-2-1-0 | ||
A2 | A1 | A0 | |||
8 | 0 | 0 | 0 | 0-1-2-34-5-6-7 | 0-1-2-3-4-5-6-7 |
0 | 0 | 1 | 1-2-3-4-5-6-7-0 | 1-0-3-2-5-4-7-6 | |
0 | 1 | 0 | 2-3-4-5-6-7-0-1 | 2-3-0-1-6-7-4-5 | |
0 | 1 | 1 | 3-4-5-6-7-0-1-2 | 3-2-1-0-7-6-5-4 | |
1 | 0 | 0 | 4-5-6-7-0-1-2-3 | 4-5-6-7-0-1-2-3 | |
1 | 0 | 1 | 5-6-7-0-1-0-3-2 | 5-4-7-6-1-0-3-2 | |
1 | 1 | 0 | 6-7-0-1-2-3-4-5 | 6-7-4-5-2-3-0-1 | |
1 | 1 | 1 | 7-0-1-2-3-4-5-6 | 7-6-5-4-3-2-1-0 |
Full | n = A0-A7 | Cn, Cn+1, | Not supported |
Page | (location 0-255) | Cn+2 Cn+3, | |
256 | Cn+4 . . . | ||
Cn−1, Cn . . . | |||
TRUTH TABLE 1 |
Flash |
1st |
2nd |
3rd CYCLE |
A | A | A | A | A | A | ||||||||||
C | D | D | R | C | D | D | R | C | D | D | R | ||||
M | D | D | D | P | M | D | D | D | P | M | D | D | D | P | |
Operation | D | R | R | Q | # | D | R | R | Q | # | D | R | R | Q | # |
Protect | L | 6 | B | X | H | AC | R | B | X | H | W | X | B | 0 | H |
Block/ | |
0 | an | TI | o | an | RI | an | 1 | / | |||||
Confirm | R | H | k | VE | w | k | T | k | H | V | |||||
E | HH | ||||||||||||||
Protect | L | 6 | B | X | H | AC | X | B | X | H | W | X | B | F | V |
Device/ | |
0 | an | TI | an | RI | an | 1 | HH | ||||||
Confirm | R | H | k | VE | k | T | k | H | |||||||
E | |||||||||||||||
Unprotect | L | 6 | B | X | H | AC | X | B | X | H | W | X | B | D | H |
Blocks/ | |
0 | an | TI | an | RI | an | 0 | / | ||||||
Confirm | R | H | k | VE | k | T | k | H | V | ||||||
E | HH | ||||||||||||||
TABLE 2 |
STATUS REGISTER |
STATUS | STATUS | |
BIT# | REGISTER BIT | DESCRIPTION |
SR7 | ISM STATUS | The ISMS bit displays the |
1 = Ready | active status of the |
|
0 = Busy | machine when performing | |
WRITE or BLOCK ERASE. | ||
The controlling logic polls | ||
this bit to determine when | ||
the erase and write status | ||
bits are valid. | ||
SR6 | RESERVED | Reserved for future use. |
SR5 | ERASE/UNPROTECT | ES is set to 1 after the maxi- |
BLOCK STATUS | mum number of ERASE | |
1 = BLOCK ERASE or | cycles is executed by the ISM | |
BLOCK UNPROTECT error | without a successful verify. | |
0 = Successful BLOCK | This bit is also Set to 1 if a | |
ERASE or UNPROTECT | BLOCK UNPROTECT | |
operation is | ||
unsuccessful. ES is only | ||
cleared by a CLEAR | ||
STATUS REGISTER com- | ||
mand or by a RESET. | ||
SR4 | WRITE/PROTECT BLOCK | WS is set to 1 after the maxi- |
STATUS | mum number of |
|
1 = WRITE or BLOCK | cycles is executed by the ISM | |
PROTECT error | without a successful verify. | |
0 = Successful WRITE or | This bit is also set to 1 if a | |
BLOCK PROTECT | BLOCK or DEVICE | |
PROTECT operation is un- | ||
successful. WS is only cleared | ||
by a CLEAR STATUS | ||
REGISTER command or by a | ||
RESET. | ||
SR2 | BANKA1 ISM STATUS | When SR0 = 0, the bank |
SR1 | BANKA0 ISM STATUS | under ISM control can be |
decoded from BA0, | ||
BA1; [0,0] Bank0; [0,1] | ||
Bank1; [1,0] Bank2; | ||
[1,1] Bank3. | ||
SR3 | DEVICE PROTECT | DPS is set to 1 if an invalid |
STATUS | WRITE, ERASE, PROTECT | |
1 = Device protected, | BLOCK, PROTECT DEVICE | |
invalid operation attempted | or |
|
0 = Device unprotected or | BLOCKS is attempted. After | |
RP# condition met | one of these commands is | |
issued, the condition of | ||
RP#, the block protect bit and | ||
the device protect bit are | ||
compared to determine if the | ||
desired operation is | ||
allowed. Must be cleared by | ||
CLEAR STATUS REGISTER | ||
or by a RESET. | ||
SR0 | DEVICE/BANK ISM | DBS is set to 1 if the ISM |
STATUS | operation is a device- |
|
1 = Device level ISM | operation. A valid READ to | |
operation | any bank of the array can | |
0 = Bank level ISM operation | immediately follow the | |
registration of a device- | ||
level ISM WRITE operation. | ||
When DBS is set to 0, the | ||
ISM operation is a bank-level | ||
operation. A READ to the | ||
bank under ISM control may | ||
result in invalid data. SR2 | ||
and SR3 can be decoded to | ||
determine which bank is | ||
under ISM control. | ||
TABLE 3 |
DEVICE CONFIGURATION |
Device | |||
Configuration | Address | Data | CONDITION |
Block Protect Bit | xx0002H | DQ0 = 1 | Block protected |
xx0002H | DQ0 = 0 | Block unprotected | |
Device Protect Bit | 000003H | DQ0 = 1 | Block protect modification |
prevented | |||
000003H | DQ0 = 0 | Block protect modification | |
enabled | |||
TABLE 4 |
PROTECT OPERATIONS TRUTH TABLE |
CS | DQ | WE | DQ0- | |||||
FUNCTION | RP# | # | M | # | Address | Vccp | DQ7 | |
DEVICE UNPROTECTED | ||||||||
PROTECT SETUP | H | L | H | L | 60H | X | X | |
PROTECT BLOCK | H | L | H | | BA | H | 01H | |
PROTECT DEVICE | VHH | L | H | L | X | X | F1H | |
UNPROTECT ALL | H/VHH | L | H | L | X | H | D0H | |
BLOCKS | ||||||||
DEVICE PROTECTED | ||||||||
PROTECT SETUP | H or | L | H | L | 60H | X | X | |
VHH | ||||||||
PROTECT BLOCK | VHH | L | H | | BA | H | 01H | |
UNPROTECT ALL | VHH | L | H | L | X | H | D0H | |
BLOCKS | ||||||||
TABLE 5 |
STATUS REGISTER ERROR DECODE |
STATUS BITS |
SR5 | SR4 | | ERROR DESCRIPTION | |
0 | 0 | 0 | No |
|
0 | 1 | 0 | WRITE, BLOCK PROTECT or DEVICE | |
PROTECT |
||||
0 | 1 | 1 | Invalid BLOCK PROTECT or DEVICE PROTECT, | |
RP# not valid (VHH) | ||||
0 | 1 | 1 | Invalid BLOCK or DEVICE PROTECT, | |
RP# not valid | ||||
1 | 0 | 0 | ERASE or ALL |
|
1 | 0 | 1 | Invalid ALL BLOCK UNPROTECT, RP# | |
not valid (VHH) | ||||
1 | 1 | 0 | Command sequencing error | |
Claims (23)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US10/762,061 US6819622B2 (en) | 2000-08-25 | 2004-01-21 | Write and erase protection in a synchronous memory |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/648,508 US6711701B1 (en) | 2000-08-25 | 2000-08-25 | Write and erase protection in a synchronous memory |
US10/762,061 US6819622B2 (en) | 2000-08-25 | 2004-01-21 | Write and erase protection in a synchronous memory |
Related Parent Applications (1)
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US09/648,508 Continuation US6711701B1 (en) | 2000-08-25 | 2000-08-25 | Write and erase protection in a synchronous memory |
Publications (2)
Publication Number | Publication Date |
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US20040184343A1 US20040184343A1 (en) | 2004-09-23 |
US6819622B2 true US6819622B2 (en) | 2004-11-16 |
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US09/648,508 Expired - Lifetime US6711701B1 (en) | 2000-08-25 | 2000-08-25 | Write and erase protection in a synchronous memory |
US10/762,061 Expired - Lifetime US6819622B2 (en) | 2000-08-25 | 2004-01-21 | Write and erase protection in a synchronous memory |
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US20060095622A1 (en) * | 2004-10-28 | 2006-05-04 | Spansion, Llc | System and method for improved memory performance in a mobile device |
US20060215451A1 (en) * | 2004-11-30 | 2006-09-28 | Masaru Yano | Semiconductor device and method of controlling said semiconductor device |
US20090040843A1 (en) * | 2007-08-06 | 2009-02-12 | Sandisk Corporation, A Delaware Corporation | Enhanced write abort mechanism for non-volatile memory |
WO2009020845A1 (en) * | 2007-08-06 | 2009-02-12 | Sandisk Corporation | Enhanced write abort mechanism for non-volatile memory |
US20110246808A1 (en) * | 2005-09-15 | 2011-10-06 | Kerth Donald A | Receiver, System, and Memory with Memory Protection During Power Supply Transitions |
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TW201145003A (en) * | 2010-06-15 | 2011-12-16 | Wistron Corp | Method capable of preventing error data writing and computer system |
US8645716B1 (en) * | 2010-10-08 | 2014-02-04 | Marvell International Ltd. | Method and apparatus for overwriting an encryption key of a media drive |
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US9218030B2 (en) | 2012-02-23 | 2015-12-22 | Freescale Semiconductor, Inc. | Programming interface and method |
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US9575768B1 (en) | 2013-01-08 | 2017-02-21 | Marvell International Ltd. | Loading boot code from multiple memories |
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US9736801B1 (en) | 2013-05-20 | 2017-08-15 | Marvell International Ltd. | Methods and apparatus for synchronizing devices in a wireless data communication system |
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Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060095622A1 (en) * | 2004-10-28 | 2006-05-04 | Spansion, Llc | System and method for improved memory performance in a mobile device |
US20060215451A1 (en) * | 2004-11-30 | 2006-09-28 | Masaru Yano | Semiconductor device and method of controlling said semiconductor device |
US7286398B2 (en) * | 2004-11-30 | 2007-10-23 | Spansion Llc | Semiconductor device and method of controlling said semiconductor device |
US20110246808A1 (en) * | 2005-09-15 | 2011-10-06 | Kerth Donald A | Receiver, System, and Memory with Memory Protection During Power Supply Transitions |
US8489058B2 (en) * | 2005-09-15 | 2013-07-16 | Silicon Laboratories Inc. | Receiver, system, and memory with memory protection during power supply transitions |
US20090040843A1 (en) * | 2007-08-06 | 2009-02-12 | Sandisk Corporation, A Delaware Corporation | Enhanced write abort mechanism for non-volatile memory |
WO2009020845A1 (en) * | 2007-08-06 | 2009-02-12 | Sandisk Corporation | Enhanced write abort mechanism for non-volatile memory |
US7599241B2 (en) | 2007-08-06 | 2009-10-06 | Sandisk Corporation | Enhanced write abort mechanism for non-volatile memory |
Also Published As
Publication number | Publication date |
---|---|
US20040184343A1 (en) | 2004-09-23 |
US6711701B1 (en) | 2004-03-23 |
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