Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS6522584 B1
Publication typeGrant
Application numberUS 09/920,866
Publication date18 Feb 2003
Filing date2 Aug 2001
Priority date2 Aug 2001
Fee statusPaid
Also published asUS6845039, US7035145, US7085164, US7684249, US8102714, US20030026132, US20030103380, US20050078521, US20050078529, US20090046508, US20100142273
Publication number09920866, 920866, US 6522584 B1, US 6522584B1, US-B1-6522584, US6522584 B1, US6522584B1
InventorsChun Chen, Kirk D. Prall
Original AssigneeMicron Technology, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Programming methods for multi-level flash EEPROMs
US 6522584 B1
Abstract
A method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a selected constant drain-to-source bias voltage and a selected gate voltage.
Images(8)
Previous page
Next page
Claims(11)
We claim:
1. A method for programming a memory cell of an electrically erasable programmable read only memory, the memory cell fabricated on a substrate and comprising a source region, a drain region, a floating gate, and a control gate, the memory cell having a threshold voltage selectively configurable into one of at least three programming states, the method comprising:
generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region;
injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate, the gate voltage comprising at least one gate voltage pulse; and
applying the gate voltage for a period of time corresponding to a selected threshold voltage for the memory cell corresponding to a selected one of the programming states, wherein each selected threshold voltage corresponds to a different period of time.
2. The method of claim 1, wherein the gate voltage pulse has a pulse width of between approximately 1 ns and approximately 10 μs.
3. The method of claim 1, wherein a transistor comprising a transistor control gate is connected in series between the drain region of the memory cell and a drain voltage generator, whereby a control voltage applied to the transistor control gate adjusts a voltage applied to the drain region of the memory cell.
4. The method of claim 1, wherein a plurality of circuit segments are connected in parallel between the drain region of the memory cell and a drain voltage generator, each circuit segment comprising a resistor connected in series with a transistor having a transistor control gate, whereby selectively applying a control voltage to the transistor of at least one of the circuit segments adjusts a voltage applied to the drain region of the memory cell.
5. The method of claim 1, wherein the drain current has a substantially constant magnitude.
6. The method of claim 1, wherein a reverse back bias is applied between the substrate and the control gate.
7. The method of claim 1, wherein the gate voltage comprises a single gate voltage pulse having a pulse width, and the period of time corresponding to the selected threshold voltage equals the pulse width.
8. The method of claim 1, wherein the gate voltage comprises a plurality of gate voltage pulses each having a pulse width, and the period of time corresponding to the selected threshold voltage equals a sum of the pulse widths.
9. The method of claim 1, wherein the gate voltage is the same for each programming state.
10. The method of claim 9, wherein the magnitude of the gate voltage is the same for each programming state.
11. The method of claim 9, wherein the gate voltage comprises a plurality of gate voltage pulses each having the same magnitude.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to electrically reprogrammable nonvolatile memory devices and methods of utilizing the same. More particularly, the invention relates to processes and structures for programming erasable programmable read-only memories (EEPROMs).

2. Description of the Related Art

Memory devices such as erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), or flash erasable programmable read-only memories (FEPROMs) are erasable and reusable memory cells which are often used in digital cellular phones, digital cameras, LAN switches, cards for notebook computers, etc. A memory cell operates by storing electric charge (representing either a binary “1” or “0” state of one data bit) on an electrically isolated floating gate, which is incorporated into a transistor. This stored charge affects the threshold voltage (VT) of the transistor, thereby providing a way to read the memory element. It is therefore crucial that the memory cell be able to maintain the stored charge over time, so that charge leakage does not cause data errors by converting the data bit from one binary state to another.

A memory cell typically consists of a transistor, a floating gate, and a control gate above the floating gate in a stacked gate structure. The floating gate, typically composed of polycrystalline silicon (i.e., “polysilicon”), is electrically isolated from the underlying semiconductor substrate by a thin dielectric layer, which is typically formed of an insulating oxide, and more particularly, silicon oxide. This dielectric layer is often referred to as a “tunnel oxide” layer, and is typically approximately 100 Å thick. Properties of the tunnel oxide layer must be strictly controlled to ensure the ability to read and write by transferring electrons across the tunnel oxide layer, while avoiding data loss through charge trapping or leakage. The control gate is positioned above the floating gate, and is electrically isolated from the floating gate by a storage dielectric layer, such as oxide-nitride-oxide (ONO). Electrical access to the floating gate is therefore only through capacitors.

A programmed memory cell has its VT increased by increasing the amount of negative charge stored on the floating gate, i.e., for given source and drain voltages, the control gate voltage which allows a current to flow between the source and the drain of a programmed memory cell is higher than that of a non-programmed memory cell. Therefore, the state of a memory cell is read by applying a control gate voltage below the predetermined level corresponding to the programmed state, but sufficiently high to allow a current between the source and the drain in a non-programmed memory cell. If a current is detected, then the memory cell is read to be not programmed.

One method to erase a memory cell (i.e., return the cell to its non-programmed state) is by exposing the floating gate to ultraviolet light, which excites the stored electrons out of the floating gate. The erasure of an EEPROM or FEPROM cell can also be accomplished via Fowler-Nordheim tunneling of charge from the floating gate, across the tunnel oxide, to the substrate, thereby reducing the stored charge in the floating gate. Under this mechanism for discharging the floating gate, for example, a large negative voltage (e.g., −10 V) is applied to the control gate, and a positive voltage (e.g., 5-6 V) is applied to the source while the drain is left floating. Electrons then tunnel from the floating gate through the tunnel oxide, and are accelerated into the source.

In an attempt to increase the storage density of an array of memory cells, efforts have been made to utilize multilevel memory cells, which are capable of representing more than two states by specifying more than one predetermined VT level. In such multilevel memory cells, each range of levels defined by the predetermined VT levels corresponds to a separate state. Therefore, to reliably distinguish between the various states, the multilevel memory cells must be programmed with narrow VT distributions within the ranges defined by the predetermined VT levels. Traditionally, these narrow VT distributions have been achieved using short programming pulses interleaved with verification read pulses in order to closely monitor the programmed level of a given cell. Examples of such multilevel memory cell programming are disclosed by Kucera, et al., U.S. Pat. No. 6,091,631; Fazio, et al., U.S. Pat. No. 5,892,710; and Harari, U.S. Pat. No. 5,293,560.

Such use of verification steps has two potential drawbacks. First, the circuitry needed to confirm that a particular cell has been properly programmed takes up valuable space on the semiconductor die. Second, the frequent verification steps take a substantial amount of time, thereby prolonging the programming process.

SUMMARY OF THE INVENTION

By eliminating the verification steps, the present invention achieves faster multilevel programming of flash memory devices. In accordance with one aspect of the present invention, a method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method comprises generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further comprises injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a selected constant drain-to-source bias voltage.

In accordance with another aspect of the present invention, a method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method comprises generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The drain-to-source bias voltage comprises at least one voltage pulse. The method further comprises injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a selected drain-to-source bias voltage.

In accordance with yet another aspect of the present invention, a method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method comprises generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The drain-to-source bias voltage comprises at least one voltage pulse. The method further comprises injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a selected gate voltage.

In accordance with yet another aspect of the present invention, a method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method comprises generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further comprises injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. The gate voltage comprises at least one voltage pulse. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a selected gate voltage.

In accordance with yet another aspect of the present invention, a method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method comprises generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further comprises injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. The gate voltage is ramped from an initial magnitude to a final magnitude greater than the initial magnitude, and the gate voltage is ramped with a ramping rate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a gate voltage with a selected final magnitude.

In accordance with yet another aspect of the present invention, a method is provided for programming a memory cell of an electrically erasable programmable read only memory. The method comprises selectively configuring the memory cell into one of at least three programming states without a verification step.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically illustrates a semiconductor substrate with a memory cell compatible with the present invention.

FIG. 2 schematically illustrates channel hot-electron (CHE) injection as a method of charge transfer to the floating gate.

FIG. 3 schematically illustrates an array of NOR-type flash memories.

FIG. 4 schematically illustrates Fowler-Nordheim (FN) tunneling as a method of charge transfer to the floating gate.

FIG. 5 schematically illustrates an array of NAND-type flash memories.

FIG. 6 schematically illustrates the variation of floating gate charge as a function of time upon applying voltages corresponding to CHE injection to the memory cell.

FIG. 7A schematically illustrates the multilevel states achieved by using different drain voltages during the CHE injection operation.

FIG. 7B schematically illustrates the threshold voltage achieved as a function of time by applying different drain voltages during the CHE injection operation.

FIG. 8 schematically illustrates the multilevel states achieved by using different gate voltages during the CHE injection operation.

FIG. 9 schematically illustrates the multilevel states achieved by using different pulse widths on the voltages during the CHE injection operation.

FIG. 10 schematically illustrates the variation of the drain current as a function of time upon applying a ramped gate voltage as compared to a constant gate voltage.

FIG. 11 schematically illustrates the multilevel states achieved by using different ramping rates on the gate voltage.

FIG. 12 schematically illustrates the drain region of a memory cell connected to a transistor.

FIG. 13 schematically illustrates the drain region of a memory cell connected to a plurality of pairs of transistors and resistors, the pairs connected in parallel.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 schematically illustrates a semiconductor substrate 10 with a memory cell 20 compatible with the present invention. The memory cell 20 includes a transistor 30, a floating gate 40, and a control gate 50 above the floating gate 40 in a stacked gate structure. The transistor 30 comprises a source region 32, a drain region 34, and a channel 36 between the source region 32 and the drain region 34. The floating gate 40, typically composed of polycrystalline silicon (i.e., “polysilicon”), is electrically isolated from the underlying semiconductor substrate 10 by a tunnel dielectric layer 60, which is a thin dielectric layer, typically formed of an insulating oxide, and more particularly, silicon oxide, and is typically approximately 100 Å thick. The control gate 50 is positioned above the floating gate 40, and is electrically isolated from the floating gate 40 by a storage dielectric layer 70, such as oxide-nitride-oxide (ONO). Electrical access to the floating gate 40 is therefore only through capacitors. It should be noted that the materials mentioned herein are merely exemplary.

An array of memory cells can be programmed by transferring charge from the semiconductor substrate to the floating gates of selected memory cells. One method of achieving this charge transfer is via channel hot-electron (CHE) injection, which is a three-terminal process, schematically illustrated by FIG. 2. CHE injection utilizes a high positive voltage (e.g., approximately 10 V) applied to the control gate 50, grounding the source region 32 of the transistor 30, and applying a high positive voltage (e.g., approximately 5 V) to the drain region 34 of the transistor 30, thereby creating a high drain-to-source bias voltage (e.g., approximately 5 V). An inversion region is created in the channel 36 between the source 32 and drain 34 regions by the gate voltage, and electrons 80 are accelerated from the source region 32 to the drain region 34 by the drain-to-source bias voltage, thereby creating a drain current between the source region 32 and drain region 34. Some fraction 82 of the electrons 80 will have sufficient energy to surmount the barrier height of the tunnel dielectric 60 and reach the floating gate 40, thereby charging the floating gate 40. By collecting and storing a sufficient amount of charge on the floating gate 40, the VT of the transistor 30 is increased to be above a predetermined level corresponding to a programmed binary state (e.g., “0”). A memory cell 20 with no charge on its floating gate 40, and with a correspondingly lower VT, is in a non-programmed state (e.g., “1”).

CHE programming is typically used to program NOR-type flash memories, as schematically illustrated in FIG. 3. In NOR-type flash memories, the memory cells 20 are connected in parallel with the drain region 34 of each memory cell 20 connected to a respective bit-line 90 and with the source region 32 of each memory cell connected to a common source line (not shown). A select line 92 connects the control gates 50 of a column of memory cells 20, one on each bit-line 90, allowing several memory cells 20, such as a byte or a word, to be accessed in parallel. While NOR-type flash memories provide fast random access, its parallel structure reduces its memory density.

Another method of storing charge on the floating gate 40 is via Fowler-Nordheim (FN) tunneling, schematically illustrated in FIG. 4, which is a two-terminal process and does not utilize a drain current 80 between the source 32 and drain 34 regions of the transistor 20. By applying a high positive voltage (e.g., approximately 10 V) to the control gate 50, a high negative voltage (e.g., approximately −10 V) to the p-well substrate 10 containing the flash memory cell 20, and floating the source 32 and drain 34 regions, an electric field is created which is sufficient for electrons 84 to tunnel through the tunnel dielectric 60 from the p-well substrate 10 and to enter the floating gate 40, thereby programming the memory cell 20. FN tunneling can occur in any two terminal device (such as a capacitor) and does not require a drain-to-source bias voltage. Compared to CHE programming, FN programming requires higher voltages and has slower programming speeds (typically requiring greater than 1 ms to program as compared to a few μs for CHE programming). However, the lower current densities of FN programming make it easier to use as a method of programming many flash memory cells at the same time (i.e., in parallel).

FN tunneling is typically used to program NAND-type flash memories, as schematically illustrated in FIG. 5. In NAND-type flash memories, the memory cells 20 are connected serially to form strings 96 of memory cells 20, with each string 96 having a string select gate 98 at one end which connects the string 96 to a bit-line 100 and a ground select gate at the opposite end of the string which connects the string to ground (not shown). A select line 102 connects the control gates 50 of a column of memory cells 20, one on each string 96. Because no outside contact is needed within a string 96 of memory cells 20, NAND-type flash memories provide increased memory density. However, because selected memory cells 20 must be accessed through the other unselected memory cells 20 of the string 96, the reading speed is limited.

As described above, the traditional programming method for multilevel memory cells has been to program the memory cell using short programming pulses of the control gate voltage and drain voltage. To achieve the narrow VT distributions, the short programming pulses are typically interleaved with verification read pulses in order to closely monitor the programmed level of a given cell. The short programming pulses and frequent verification steps make the program operation very time consuming.

In addition, use of CHE injection to program flash EPROM devices has the disadvantage of requiring rather high drain currents in order to generate the charge which is stored on the floating gate 40. Because the total current available to program the memory cells is limited at any one time, the high drain currents constrain the number of memory cells 20 which can be programmed in parallel to typically a few hundred cells maximum. One way to reduce the peak programming current, as disclosed by Keeney, et al. in U.S. Pat. Nos. 5,553,020 and 5,487,033, is to step the gate voltage of the memory cell 20 as it is being programmed, in increments from an initial minimum value to a maximum value based upon the number of levels to program in the memory cell 20. Each step of the gate voltage is accompanied by a corresponding pulse of the drain voltage and a verifying pulse until the desired threshold voltage is reached on the floating gate. In this way, the drain current can be reduced; however, there is a corresponding increase in the time required to charge the floating gate 40 to a given level.

Similarly, while use of FN tunneling to program flash EPROM devices does not utilize drain current, stepping up the gate voltage of the memory cell 20 as it is being programmed reduces the tunneling current and significantly increases the time required to program the memory cell 20. The programming current can be further reduced by applying a reverse back bias between the substrate 10 and the control gate 50 to increase the gate current efficiency, as is described by Hu, et al., in “Substrate-Current-Induced Hot Electron (SCIHE) Injection: A New Convergence Scheme For Flash Memory,” IEDM Tech. Dig., pp. 283-286, 1995, which is incorporated by reference herein.

The charge Q applied to the floating gate 40 varies with time during the charging from an initial value of Q0 (equal to zero prior to applying the voltages corresponding to CHE injection at t0) to a saturation value Q1 at a later time t. FIG. 6 schematically illustrates the variation of floating gate charge Q as a function of time upon applying voltages corresponding to CHE injection to the memory cell 20. As more charge is built up in the floating gate 40, the electric field which attracts the hot electrons in the channel 36 toward the floating gate 40 is lessened. Once the floating gate 40 has the saturation charge Q1, the hot electrons in the channel 36 are shielded from the gate voltage VG and no more hot electrons reach the floating gate 40. The amount of saturation charge Q1 is dependent on the gate voltage VG, as is apparent from FIG. 6, which shows three different saturation charge levels for three different gate voltages. The time to reach the saturation charge Q1 does not exhibit a large dependency on the gate voltage VG, but it is typically between approximately 100 ns and 10 μs. The threshold voltage VT is dependent on the amount of charge applied to the floating gate 40.

In certain embodiments of the present invention, the memory cell 20 is programmed using CHE injection by applying a constant drain-to-source bias voltage between the drain region 34 and source region 32 and a gate voltage to the control gate 50 without verification read pulses. Selected threshold voltages for the memory cell 20 corresponding to a selected one of the multilevel programming states are generated by applying different selected drain-to-source bias voltages during the CHE injection operation. In one such embodiment, schematically illustrated in FIG. 7A, each cell has two bits, and hence four states: (00), (01), (10), and (11). In certain embodiments, one of the four states (e.g., (00)) corresponds to the cell after erase. The magnitude of the drain voltage VD is selected to provide a selected threshold voltage corresponding to one of the three other possible states: (01), (10), and (11), with the gate voltage VG and the source voltage VS set at constant values (e.g., VG is set to approximately +10 V, VS is set to approximately 0 V). The amount of charge injected onto the floating gate 40 corresponds to the potential difference between the source region 32 and the drain region 34, i.e., the drain-to-source bias voltage. For example, referring to FIG. 7A, to apply a charge to the floating gate 40 of a memory cell 20 so that the threshold voltage corresponds to a (01) state, the drain voltage VD is set to a voltage substantially equal to VD1. Similarly, the (10) state is achieved by applying a drain voltage that is substantially equal to VD2, and the (11) state is achieved by applying a drain voltage that is substantially equal to VD3.

Referring to FIG. 7B, various values of the drain voltage VD (e.g., VD1=4 V; VD2=5 V; VD3=6V) produce different threshold voltages Vt after a fixed program time. By halting the programming of a cell after a fixed time, embodiments of the present invention achieve selected multilevel programming states while avoiding the verification steps of the prior art.

In other embodiments of the present invention, selected threshold voltages corresponding to selected multilevel programming states are generated by applying different gate voltages during the CHE injection operation. As schematically illustrated in FIG. 8, the memory cell 20 is programmed using CHE injection by setting the drain voltage and the source voltage to constant values (e.g., VD of approximately +5 V and VS of approximately 0 V). The magnitude of the gate voltage VG is selected to provide a selected threshold voltage corresponding to one of the four possible multilevel states. The amount of charge injected onto the floating gate 40 corresponds to the gate voltage. For example, referring to FIG. 8, to apply a charge to the floating gate 40 of a memory cell 20 so that the threshold voltage corresponds to a (01) state, the gate voltage VG is set to a voltage substantially equal to VG1 (e.g., VG1=6 V). Similarly, the (10) state is achieved by applying a gate voltage substantially equal to VG2 (e.g., VG2=8 V), and the (11) state is achieved by applying a gate voltage substantially equal to VG3 (e.g., VG3=10 V).

In still other embodiments of the present invention, the time profile of the applied voltages, as schematically illustrated in FIG. 9, is utilized to set the threshold voltage to one of the four possible states. A selected threshold voltage corresponding to a selected multilevel programming state is generated by applying voltages comprising at least one voltage pulse, with a selected pulse period during the CHE injection operation. For example, referring to FIG. 9, to apply a charge to the floating gate 40 of a memory cell 20 so that the threshold voltage corresponds to a (01) state, a single gate voltage pulse VG with a magnitude of approximately 10 V and a period of approximately (t1−t0) is applied to the control gate 50 while the source voltage and drain voltage are set at constant values (e.g., VS of approximately 0 V, VD of approximately 5 V). Similarly, the (10) state is achieved by applying a voltage pulse with a period approximately equal to (t2−t0), and the (11) state is achieved by applying a voltage pulse with a period approximately equal to (t3−t0). In certain embodiments, the total time in which the appropriate voltages for CHE injection are applied to the memory cell 20 are distributed among a plurality of pulses (i.e., the sum of the pulse periods of the plurality of pulses has the required time duration to achieve the desired state of the memory cell 20). The voltage pulse of the gate voltage VG preferably has a period of between approximately 1 ns and approximately 10 μs. For example, VG can be applied for 2 ns to program the (01) state, 0.1 μs to program the (10) state, and 2 μs to program the (11) state.

Alternatively, in other embodiments, the drain voltage VD can be pulsed and the gate voltage VG selected to generate a selected threshold voltage corresponding to a selected multilevel programming state. For example, VD can be applied for 2 ns to program the (01) state, 0.1 μs to program the (10) state, and 2 μs to program the (11) state. The voltage pulse of the drain voltage VD preferably has a period of between approximately 1 ns and approximately 10 μs. Alternatively, in still other embodiments, the drain voltage VD can be pulsed, the source voltage VS can be pulsed, or any combination of the gate voltage VG, drain voltage VD, and source voltage VS can be pulsed to set the threshold voltage to one of the four possible states.

In still other embodiments of the present invention, selected threshold voltages corresponding to selected multilevel programming states are generated by ramping the voltages applied to the memory cell 20 during the CHE injection operation without applying verification pulses. As described above, as charge accumulates in the floating gate 40, the hot electrons in the channel 36 are increasingly shielded from the gate voltage VG, thereby reducing the rate of charge injection and eventually reaching a saturation level corresponding to a saturation threshold voltage. When applying a constant gate voltage VG, as schematically illustrated in FIG. 10, there will be a high drain current at the beginning of the programming, due to the large potential difference between the floating gate 40 and the channel 36. By ramping the gate voltage VG during the CHE injection from an initial magnitude to a final magnitude greater than the initial magnitude, the drain current will be constant over an extended period of time, at a lower level, as schematically illustrated in FIG. 10. The saturation threshold will be determined by both the drain voltage, and the final gate voltage at the end of the ramp.

In certain embodiments, a ramped gate voltage VG is used with different values of the drain voltage VD, the values of the applied drain voltage VD selected to generate selected threshold voltages for the memory cell 20 corresponding to selected multilevel programming states. Such embodiments are similar to those discussed in relation to FIG. 7, but with lessened drain currents due to the ramping of the gate voltage VG, so that a large number of cells can be programmed in parallel. In certain other embodiments, a ramped gate voltage VG is used with different pulse periods of the drain voltage VD, the pulse periods selected to generate selected threshold voltages corresponding to selected multilevel programming states of the memory cell 20. Such embodiments are similar to those discussed in relation to FIG. 9, but with lessened drain currents due to the ramping of the gate voltage VG, so that a large number of cells can be programmed in parallel. In still other embodiments, the value of the final gate voltage VG during the ramping is selected to generate selected threshold voltages corresponding to selected multilevel programming states of the memory cell 20. Such embodiments are similar to those discussed in relation to FIG. 8, but with lessened drain currents due to the ramping of the gate voltage VG, and again a large number of cells can be programmed at the same time. For example, 7 V, 9 V, and 11 V can be used as the final gate voltage for programmed states (01), (10), and (11), respectively.

As schematically illustrated in FIG. 11, by selecting the rate of ramping of the gate voltage VG, selected threshold voltages corresponding to selected multilevel programming states of the memory cell 20 can be generated. The amount of charge on the floating gate 40 after CHE injection for a time (t1−t0) is dependent on the ramping rate of the gate voltage VG. Slower ramping rates correspond to slower charge injection on the floating gate 40, and less charge on the floating gate 40 after a known time (t1−t0). Therefore, the ramping rate of VG can be selected to yield a particular amount of charge on the floating gate 40 after a known charging time, thereby setting the threshold voltage to one of the four possible states. For example, within 1 ms, the gate voltage can be ramped from 0 V to 6 V, 8 V, and 10 V for programmed states (01), (10), and (11), respectively. In certain embodiments, the injection of charge is performed for the known time (t1−t0) by pulsing the voltages applied to the memory cell 20 (e.g., pulsing the drain voltage VD, the source voltage VS, the gate voltage VG, or any combination of the gate voltage VG, drain voltage VD, and source voltage VS).

In certain other embodiments, where the drain voltage does not have a constant magnitude, the drain region 34 can be connected to a constant current source. In this way, the drain current is maintained to have a substantially constant magnitude throughout the charging operation. The amount of charge injected onto the floating gate 40 varies with the amount of drain current, so multilevel states are generated by using different drain currents during the CHE injection operation. Such a constant drain current can be utilized with any of the above-described embodiments.

In still other embodiments, a reverse back bias can be applied between the substrate 10 and control gate 50 to increase the fraction of hot electrons which are injected from the channel 36 to the floating gate 40. When combined with the above-described embodiments, the reverse back bias improves the programming efficiency and yields faster convergence to the desired saturation threshold voltage. Values of the back bias compatible with embodiments of the present invention range from approximately 0 V to approximately −4 V.

Different voltages on the drain region 34 can be achieved by connecting a transistor 110 in series between the drain region 34 of the memory cell 20 and a drain voltage generator (not shown). For example, as schematically illustrated in FIG. 12, a transistor 110 is connected on a bit line in series to the drain region 34, the transistor 110 having a transistor control gate 112. Multilevel states are achieved by using different control voltages on the transistor control gate 112 during the programnming operation to adjust a voltage applied to the drain region 34 of the memory cell 20. Such a transistor 110 can be utilized with any of the above-described embodiments.

In alternative embodiments, as schematically illustrated in FIG. 13, a plurality of pairs of transistors 120 and resistors 124, in which each transistor 120 has a transistor control gate 122 and is in series with a corresponding resistor 124, are connected in parallel between the drain region 34 of the memory cell 20 and a drain voltage generator (not shown). The resistors 124 each have a different resistance, and multilevel states are achieved by selectively applying a control voltage to at least one transistor 120, thereby applying different voltages to the drain region 34 during the programming operation. Such a plurality of pairs of transistors 120 and resistors 122 can be utilized with any of the above-described embodiments.

In the embodiments described above, the memory cells are initially discharged or erased, and the appropriate amount of charge is applied to the floating gate 40 to correspond to one of the multilevel programming states. In still other embodiments compatible with the present invention, the memory cells are initially charged to a selected value, and then discharged by a selected amount, resulting in the appropriate amount of charge on the floating gate 40 to correspond to one of the multilevel programming states.

Although described above in connection with particular embodiments of the present invention, it should be understood the descriptions of the embodiments are illustrative of the invention and are not intended to be limiting. Various modifications and applications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined in the appended claims.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US504394017 Jul 198927 Aug 1991Eliyahou HarariFlash EEPROM memory systems having multistate storage cells
US5293560 *3 Nov 19928 Mar 1994Eliyahou HarariMulti-state flash EEPROM system using incremental programing and erasing methods
US54187436 Dec 199323 May 1995Nippon Steel CorporationMethod of writing into non-volatile semiconductor memory
US5424978 *14 Mar 199413 Jun 1995Nippon Steel CorporationNon-volatile semiconductor memory cell capable of storing more than two different data and method of using the same
US544050521 Jan 19948 Aug 1995Intel CorporationMethod and circuitry for storing discrete amounts of charge in a single memory element
US547748522 Feb 199519 Dec 1995National Semiconductor CorporationMethod for programming a single EPROM or FLASH memory cell to store multiple levels of data that utilizes a floating substrate
US548703328 Jun 199423 Jan 1996Intel CorporationStructure and method for low current programming of flash EEPROMS
US551102122 Feb 199523 Apr 1996National Semiconductor CorporationMethod for programming a single EPROM or flash memory cell to store multiple levels of data that utilizes a forward-biased source-to-substrate junction
US5553020 *31 Aug 19953 Sep 1996Intel CorporationStructure and method for low current programming of flash EEPROMs
US55575676 Apr 199517 Sep 1996National Semiconductor Corp.Method for programming an AMG EPROM or flash memory when cells of the array are formed to store multiple bits of data
US558794927 Apr 199524 Dec 1996National Semiconductor CorporationMethod for programming an ETOX EPROM or flash memory when cells of the array are formed to store multiple bits of data
US559468513 Apr 199514 Jan 1997National Semiconductor CorporationMethod for programming a single EPROM or flash memory cell to store multiple bits of data that utilizes a punchthrough current
US57086001 Oct 199613 Jan 1998Sharp Kabushiki KaishaMethod for writing multiple value into nonvolatile memory in an equal time
US58089377 Feb 199715 Sep 1998National Semiconductor CorporationSelf-convergent method for programming FLASH and EEPROM memory cells that moves the threshold voltage from an erased threshold voltage range to one of a plurality of programmed threshold voltage ranges
US58319018 Nov 19963 Nov 1998Advanced Micro Devices, Inc.Method of programming a memory cell to contain multiple values
US589271013 Aug 19976 Apr 1999Intel CorporationMethod and circuitry for storing discrete amounts of charge in a single memory element
US5912488 *24 Jun 199715 Jun 1999Samsung Electronics Co., LtdStacked-gate flash EEPROM memory devices having mid-channel injection characteristics for high speed programming
US5923585 *10 Jan 199713 Jul 1999Invox TechnologySource biasing in non-volatile memory having row-based sectors
US595989627 Feb 199828 Sep 1999Micron Technology Inc.Multi-state flash memory cell and method for programming single electron differences
US6011722 *13 Oct 19984 Jan 2000Lucent Technologies Inc.Method for erasing and programming memory devices
US60916311 Jul 199818 Jul 2000Advanced Micro Devices, Inc.Program/verify technique for multi-level flash cells enabling different threshold levels to be simultaneously programmed
US6166955 *9 Jul 199926 Dec 2000Macronix International Co., Ltd.Apparatus and method for programming of flash EPROM memory
US6172908 *8 Oct 19989 Jan 2001Stmicroelectronics S.R.L.Controlled hot-electron writing method for non-volatile memory cells
US6243298 *14 Feb 20005 Jun 2001Azalea Microelectronics CorporationNon-volatile memory cell capable of being programmed and erased through substantially separate areas of one of its drain-side and source-side regions
JPH04351216A Title not available
Non-Patent Citations
Reference
1Bruno Riccò, et al., Nonvolatile Multilevel Memories for Digital Applications, Proceedings of the IEEE, vol. 86, No. 12, pp. 2399-2421, Dec. 1998.
2C.-Y. Hu, et al., Substrate-Current-Induced Hot Electron (SCIHE) injection: a new convergence scheme for flash memory, IEEE, IEDM Tech Dig., pp. 283-286, 1995.
3David Esseni, et al., A New and Flexible Scheme for Hot-Electron Programming of Nonvolatile Memory Cells, IEEE Transactions on Electron Devices, vol. 46, No. 1, pp. 125-133, Jan. 1999.
4David Esseni, et al., Trading-Off Programming Speed and Current Absorption in Flash Memories with the Ramped-Gate Programming Technique, IEEE Transactions on Electron Devices, vol. 47, No. 4, pp. 828-834, Apr. 2000.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6845039 *18 Dec 200218 Jan 2005Micron Technology, Inc.Programming methods for multi-level flash EEPROMS
US703514529 Nov 200425 Apr 2006Micron Technology, Inc.Programming methods for multi-level flash EEPROMs
US708516429 Nov 20041 Aug 2006Micron Technology, Inc.Programming methods for multi-level flash EEPROMs
US725311829 Aug 20057 Aug 2007Micron Technology, Inc.Pitch reduced patterns relative to photolithography features
US726805431 Jul 200611 Sep 2007Micron Technology, Inc.Methods for increasing photo-alignment margins
US729247631 Aug 20056 Nov 2007Micron Technology, Inc.Programming method for NAND EEPROM
US736156931 Jul 200622 Apr 2008Micron Technology, Inc.Methods for increasing photo-alignment margins
US73683628 Jun 20066 May 2008Micron Technology, Inc.Methods for increasing photo alignment margins
US739074625 Aug 200524 Jun 2008Micron Technology, Inc.Multiple deposition for integration of spacers in pitch multiplication process
US73937891 Sep 20051 Jul 2008Micron Technology, Inc.Protective coating for planarization
US73967819 Jun 20058 Jul 2008Micron Technology, Inc.Method and apparatus for adjusting feature size and position
US741398129 Jul 200519 Aug 2008Micron Technology, Inc.Pitch doubled circuit layout
US742953623 May 200530 Sep 2008Micron Technology, Inc.Methods for forming arrays of small, closely spaced features
US743553620 Jun 200614 Oct 2008Micron Technology, Inc.Method to align mask patterns
US745595626 Mar 200725 Nov 2008Micron Technology, Inc.Method to align mask patterns
US74769332 Mar 200613 Jan 2009Micron Technology, Inc.Vertical gated access transistor
US748868525 Apr 200610 Feb 2009Micron Technology, Inc.Process for improving critical dimension uniformity of integrated circuit arrays
US749933012 Sep 20073 Mar 2009Micron Technology, Inc.Programming method for NAND EEPROM
US753885811 Jan 200626 May 2009Micron Technology, Inc.Photolithographic systems and methods for producing sub-diffraction-limited features
US754163214 Jun 20052 Jun 2009Micron Technology, Inc.Relaxed-pitch method of aligning active area to digit line
US754764024 Jul 200616 Jun 2009Micron Technology, Inc.Method for integrated circuit fabrication using pitch multiplication
US75603902 Jun 200514 Jul 2009Micron Technology, Inc.Multiple spacer steps for pitch multiplication
US75725721 Sep 200511 Aug 2009Micron Technology, Inc.Methods for forming arrays of small, closely spaced features
US761194431 Aug 20053 Nov 2009Micron Technology, Inc.Integrated circuit fabrication
US761198030 Aug 20063 Nov 2009Micron Technology, Inc.Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
US762969324 Jul 20068 Dec 2009Micron Technology, IncMethod for integrated circuit fabrication using pitch multiplication
US764891920 Apr 200619 Jan 2010Tran Luan CIntegrated circuit fabrication
US76519511 Mar 200726 Jan 2010Micron Technology, Inc.Pitch reduced patterns relative to photolithography features
US76553872 Sep 20042 Feb 2010Micron Technology, Inc.Method to align mask patterns
US7656704 *20 Jul 20062 Feb 2010Winbond Electronics Corp.Multi-level operation in nitride storage memory cell
US76592086 Dec 20079 Feb 2010Micron Technology, IncMethod for forming high density patterns
US766657814 Sep 200623 Feb 2010Micron Technology, Inc.Efficient pitch multiplication process
US767995715 Apr 200516 Mar 2010Virage Logic CorporationRedundant non-volatile memory cell
US7684249 *1 Aug 200623 Mar 2010Round Rock Research, LlcProgramming methods for multi-level memory devices
US76873421 Sep 200530 Mar 2010Micron Technology, Inc.Method of manufacturing a memory device
US76874088 Mar 200730 Mar 2010Micron Technology, Inc.Method for integrated circuit fabrication using pitch multiplication
US769656731 Aug 200513 Apr 2010Micron Technology, IncSemiconductor memory device
US771523410 Jul 200811 May 2010Micron Technology, Inc.Reducing effects of program disturb in a memory device
US77152369 Mar 200611 May 2010Virage Logic CorporationFault tolerant non volatile memories and methods
US77185401 Feb 200718 May 2010Round Rock Research, LlcPitch reduced patterns relative to photolithography features
US771989630 Oct 200718 May 2010Virage Logic CorporationConfigurable single bit/dual bits memory
US772917116 Sep 20081 Jun 2010Micron Technology, Inc.Multiple select gate architecture with select gates of different lengths
US77323433 May 20078 Jun 2010Micron Technology, Inc.Simplified pitch doubling process flow
US773370513 Mar 20088 Jun 2010Micron Technology, Inc.Reduction of punch-through disturb during programming of a memory device
US773698026 Nov 200815 Jun 2010Micron Technology, Inc.Vertical gated access transistor
US77370391 Nov 200715 Jun 2010Micron Technology, Inc.Spacer process for on pitch contacts and related structures
US77591971 Sep 200520 Jul 2010Micron Technology, Inc.Method of forming isolated features using pitch multiplication
US77675734 Aug 20083 Aug 2010Round Rock Research, LlcLayout for high density conductive interconnects
US776805125 Jul 20053 Aug 2010Micron Technology, Inc.DRAM including a vertical surround gate transistor
US777668313 May 200817 Aug 2010Micron Technology, Inc.Integrated circuit fabrication
US77767441 Sep 200517 Aug 2010Micron Technology, Inc.Pitch multiplication spacers and methods of forming the same
US779053118 Dec 20077 Sep 2010Micron Technology, Inc.Methods for isolating portions of a loop of pitch-multiplied material and related structures
US779195015 May 20077 Sep 2010Virage Logic CorporationInverter non-volatile memory cell and array system
US77951491 Jun 200614 Sep 2010Micron Technology, Inc.Masking techniques and contact imprint reticles for dense semiconductor fabrication
US77964505 Feb 200814 Sep 2010Virage Logic CorporationRadio frequency (RFID) tag including configurable single bit/dual bits memory
US780882326 Jan 20085 Oct 2010Virage Logic CorporationRFID tag with redundant non-volatile memory cell
US781626230 Aug 200519 Oct 2010Micron Technology, Inc.Method and algorithm for random half pitched interconnect layout with constant spacing
US782926231 Aug 20059 Nov 2010Micron Technology, Inc.Method of forming pitch multipled contacts
US78425582 Mar 200630 Nov 2010Micron Technology, Inc.Masking process for simultaneously patterning separate regions
US788402219 Jan 20078 Feb 2011Round Rock Research, LlcMultiple deposition for integration of spacers in pitch multiplication process
US78887216 Jul 200515 Feb 2011Micron Technology, Inc.Surround gate access transistors with grown ultra-thin bodies
US789886124 Oct 20081 Mar 2011Micron Technology, Inc.Reducing effects of program disturb in a memory device
US79020747 Apr 20068 Mar 2011Micron Technology, Inc.Simplified pitch doubling process flow
US79102881 Sep 200422 Mar 2011Micron Technology, Inc.Mask material conversion
US79151164 May 200929 Mar 2011Micron Technology, Inc.Relaxed-pitch method of aligning active area to digit line
US79204232 May 20085 Apr 2011Synopsys, Inc.Non volatile memory circuit with tailored reliability
US79233734 Jun 200712 Apr 2011Micron Technology, Inc.Pitch multiplication using self-assembling materials
US792461914 Jul 200912 Apr 2011Micron Technology, Inc.Programming method to reduce word line to word line breakdown for NAND flash
US793599922 Feb 20103 May 2011Micron Technology, Inc.Memory device
US793940922 Jul 200810 May 2011Micron Technology, Inc.Peripheral gate stacks and recessed array gates
US79772362 Jun 200912 Jul 2011Micron Technology, Inc.Method of forming a transistor gate of a recessed access device, method of forming a recessed transistor gate and a non-recessed transistor gate, and method of fabricating an integrated circuit
US800331024 Apr 200623 Aug 2011Micron Technology, Inc.Masking techniques and templates for dense semiconductor fabrication
US800354222 Jun 200923 Aug 2011Micron Technology, Inc.Multiple spacer steps for pitch multiplication
US801109019 May 20086 Sep 2011Micron Technology, Inc.Method for forming and planarizing adjacent regions of an integrated circuit
US801267413 Jan 20106 Sep 2011Micron Technology, Inc.Efficient pitch multiplication process
US802332920 Apr 201020 Sep 2011Micron Technology, Inc.Reducing effects of program disturb in a memory device
US803021730 Apr 20104 Oct 2011Micron Technology, Inc.Simplified pitch doubling process flow
US803021821 Mar 20084 Oct 2011Micron Technology, Inc.Method for selectively modifying spacing between pitch multiplied structures
US803022231 Jul 20064 Oct 2011Round Rock Research, LlcStructures with increased photo-alignment margins
US803934824 May 201018 Oct 2011Micron Technology, Inc.Vertical gated access transistor
US804391510 Jun 201025 Oct 2011Micron Technology, Inc.Pitch multiplied mask patterns for isolated features
US804881228 Apr 20101 Nov 2011Round Rock Research, LlcPitch reduced patterns relative to photolithography features
US80762083 Jul 200813 Dec 2011Micron Technology, Inc.Method for forming transistor with high breakdown voltage using pitch multiplication technique
US810149711 Sep 200824 Jan 2012Micron Technology, Inc.Self-aligned trench formation
US810199219 Nov 201024 Jan 2012Micron Technology, Inc.Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
US8102714 *3 Feb 201024 Jan 2012Round Rock Research, LlcProgramming methods for multi-level memory devices
US81145739 Apr 201014 Feb 2012Micron Technology, Inc.Topography based patterning
US811524314 Feb 201114 Feb 2012Micron Technology, Inc.Surround gate access transistors with grown ultra-thin bodies
US811953511 Dec 200921 Feb 2012Round Rock Research, LlcPitch reduced patterns relative to photolithography features
US81239684 Mar 200828 Feb 2012Round Rock Research, LlcMultiple deposition for integration of spacers in pitch multiplication process
US81292895 Oct 20066 Mar 2012Micron Technology, Inc.Method to deposit conformal low temperature SiO2
US814824718 Oct 20103 Apr 2012Micron Technology, Inc.Method and algorithm for random half pitched interconnect layout with constant spacing
US81584764 Aug 201017 Apr 2012Micron Technology, Inc.Integrated circuit fabrication
US81598798 Feb 201117 Apr 2012Micron Technology, Inc.Reducing effects of program disturb in a memory device
US816495012 May 201024 Apr 2012Micron Technology, Inc.Reduction of punch-through disturb during programming of a memory device
US817355011 Jul 20118 May 2012Micron Technology, Inc.Method for positioning spacers for pitch multiplication
US820757631 Jan 200726 Jun 2012Round Rock Research, LlcPitch reduced patterns relative to photolithography features
US82075835 Nov 201026 Jun 2012Micron Technology, Inc.Memory device comprising an array portion and a logic portion
US82076145 Aug 200826 Jun 2012Micron Technology, Inc.Methods for forming arrays of small, closely spaced features
US821180317 May 20103 Jul 2012Micron Technology, Inc.Spacer process for on pitch contacts and related structures
US821694917 Feb 201010 Jul 2012Round Rock Research, LlcMethod for integrated circuit fabrication using pitch multiplication
US822210510 Feb 201017 Jul 2012Micron Technology, Inc.Methods of fabricating a memory device
US822730517 Mar 201124 Jul 2012Micron Technology, Inc.Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
US825264611 Apr 201128 Aug 2012Micron Technology, Inc.Peripheral gate stacks and recessed array gates
US82640106 Jul 201011 Sep 2012Round Rock Research, LlcLayout for high density conductive interconnects
US82665587 Jul 200911 Sep 2012Micron Technology, Inc.Methods for forming arrays of small, closely spaced features
US832410713 Jan 20104 Dec 2012Micron Technology, Inc.Method for forming high density patterns
US832552023 Mar 20124 Dec 2012Micron Technology, Inc.Reducing effects of program disturb in a memory device
US833421127 Jan 200918 Dec 2012Micron Technology, Inc.Process for improving critical dimension uniformity of integrated circuit arrays
US833808511 Dec 200925 Dec 2012Micron Technology, Inc.Method to align mask patterns
US833895912 Sep 201125 Dec 2012Micron Technology, Inc.Simplified pitch doubling process flow
US834387510 Jan 20121 Jan 2013Micron Technology, Inc.Methods of forming an integrated circuit with self-aligned trench formation
US835032018 Jan 20128 Jan 2013Micron Technology, Inc.Memory array and memory device
US835431710 Mar 201115 Jan 2013Micron Technology, Inc.Relaxed-pitch method of aligning active area to digit line
US839003428 Jul 20105 Mar 2013Micron Technology, Inc.Methods for isolating portions of a loop of pitch-multiplied material and related structures
US842611830 Sep 201023 Apr 2013Micron Technology, Inc.Method of forming pitch multiplied contacts
US843197119 Sep 201130 Apr 2013Micron Technology, Inc.Pitch multiplied mask patterns for isolated features
US844980524 Jun 201028 May 2013Micron Technology, Inc.Masking techniques and contact imprint reticles for dense semiconductor fabrication
US84508294 Aug 201128 May 2013Micron Technology, Inc.Efficient pitch multiplication process
US847938411 Aug 20119 Jul 2013Micron Technology, Inc.Methods for integrated circuit fabrication with protective coating for planarization
US848138511 May 20129 Jul 2013Micron Technology, Inc.Methods of fabricating a memory device
US84866109 Feb 201116 Jul 2013Micron Technology, Inc.Mask material conversion
US849228224 Aug 200923 Jul 2013Micron Technology, Inc.Methods of forming a masking pattern for integrated circuits
US850734112 Apr 201213 Aug 2013Micron Technology, Inc.Integrated circuit fabrication
US850738421 Sep 201113 Aug 2013Micron Technology, Inc.Method for selectively modifying spacing between pitch multiplied structures
US85462151 Mar 20131 Oct 2013Micron Technology, Inc.Methods of fabricating a memory device
US855252621 Dec 20128 Oct 2013Micron Technology, Inc.Self-aligned semiconductor trench structures
US855770412 Oct 200915 Oct 2013Micron Technology, Inc.Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
US856322931 Jul 200722 Oct 2013Micron Technology, Inc.Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
US859289813 Oct 201126 Nov 2013Micron Technology, Inc.Vertical gated access transistor
US859294016 Jan 201226 Nov 2013Micron Technology, Inc.Topography based patterning
US859804116 Apr 20123 Dec 2013Micron Technology, Inc.Method for positioning spacers in pitch multiplication
US859863222 Jun 20123 Dec 2013Round Rock Research LlcIntegrated circuit having pitch reduced patterns relative to photoithography features
US860141012 Jul 20123 Dec 2013Micron Technology, Inc.Methods for forming arrays of small, closely spaced features
US860932428 Mar 201317 Dec 2013Micron Technology, Inc.Method of forming pitch multiplied contacts
US86095235 Dec 201217 Dec 2013Micron Technology, Inc.Method of making a memory array with surrounding gate access transistors and capacitors with global staggered local bit lines
US863736213 Jul 201228 Jan 2014Micron Technology, Inc.Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
US86635326 May 20134 Mar 2014Micron Technology, Inc.Masking techniques and contact imprint reticles for dense semiconductor fabrication
US867451221 Dec 201218 Mar 2014Micron Technology, Inc.Method to align mask patterns
US868585926 Sep 20131 Apr 2014Micron Technology, Inc.Self-aligned semiconductor trench structures
US870361619 May 200822 Apr 2014Round Rock Research, LlcMethod for adjusting feature size and position
US877216619 Jun 20128 Jul 2014Micron Technology, Inc.Spacer process for on pitch contacts and related structures
US877284018 Jun 20128 Jul 2014Micron Technology, Inc.Memory device comprising an array portion and a logic portion
US88593628 Aug 201314 Oct 2014Micron Technology, Inc.Integrated circuit fabrication
US88655982 Dec 201321 Oct 2014Micron Technology, Inc.Method for positioning spacers in pitch multiplication
US887164622 Jul 201328 Oct 2014Micron Technology, Inc.Methods of forming a masking pattern for integrated circuits
US887164830 Nov 201228 Oct 2014Micron Technology, Inc.Method for forming high density patterns
US887763928 Mar 20124 Nov 2014Micron Technology, Inc.Method and algorithm for random half pitched interconnect layout with constant spacing
US888364414 Oct 201311 Nov 2014Micron Technology, Inc.Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
US888902017 Dec 201218 Nov 2014Micron Technology, Inc.Process for improving critical dimension uniformity of integrated circuit arrays
US889523212 Jul 201325 Nov 2014Micron Technology, Inc.Mask material conversion
US892811122 Nov 20116 Jan 2015Micron Technology, Inc.Transistor with high breakdown voltage having separated drain extensions
US893296026 Feb 201313 Jan 2015Micron Technology, Inc.Methods for isolating portions of a loop of pitch-multiplied material and related structures
US90036515 Jul 201314 Apr 2015Micron Technology, Inc.Methods for integrated circuit fabrication with protective coating for planarization
US903541624 May 201319 May 2015Micron Technology, Inc.Efficient pitch multiplication process
US90481949 Aug 20132 Jun 2015Micron Technology, Inc.Method for selectively modifying spacing between pitch multiplied structures
US907688821 Dec 20067 Jul 2015Micron Technology, Inc.Silicided recessed silicon
US90828292 Dec 201314 Jul 2015Micron Technology, Inc.Methods for forming arrays of small, closely spaced features
US909931430 Jun 20104 Aug 2015Micron Technology, Inc.Pitch multiplication spacers and methods of forming the same
US909940218 May 20124 Aug 2015Micron Technology, Inc.Integrated circuit structure having arrays of small, closely spaced features
US911776630 Sep 201425 Aug 2015Micron Technology, Inc.Method for positioning spacers in pitch multiplication
US914760815 Sep 201429 Sep 2015Micron Technology, Inc.Integrated circuit fabrication
US918415921 Dec 201210 Nov 2015Micron Technology, Inc.Simplified pitch doubling process flow
US918416121 Nov 201310 Nov 2015Micron Technology, Inc.Vertical gated access transistor
US941259117 Oct 20139 Aug 2016Micron Technology, Inc.Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
US941259416 Sep 20159 Aug 2016Micron Technology, Inc.Integrated circuit fabrication
US947849730 Oct 201425 Oct 2016Micron Technology, Inc.Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
US955308217 Oct 201424 Jan 2017Micron Technology, Inc.Process for improving critical dimension uniformity of integrated circuit arrays
US96666958 Jan 201530 May 2017Micron Technology, Inc.Methods for isolating portions of a loop of pitch-multiplied material and related structures
US967978113 Apr 201513 Jun 2017Micron Technology, Inc.Methods for integrated circuit fabrication with protective coating for planarization
US971123010 Oct 201418 Jul 2017Stmicroelectronics (Rousset) SasMethod for writing into and reading a multi-levels EEPROM and corresponding memory device
US20050078521 *29 Nov 200414 Apr 2005Chun ChenProgramming methods for multi-level flash EEPROMs
US20050078529 *29 Nov 200414 Apr 2005Chun ChenProgramming methods for multi-level flash EEPROMs
US20060046200 *1 Sep 20042 Mar 2006Abatchev Mirzafer KMask material conversion
US20060046201 *2 Sep 20042 Mar 2006Sandhu Gurtej SMethod to align mask patterns
US20060139496 *22 Dec 200529 Jun 2006Sanyo Electric Co., Ltd.Video signal processing apparatus
US20060211260 *29 Aug 200521 Sep 2006Luan TranPitch reduced patterns relative to photolithography features
US20060216923 *31 Aug 200528 Sep 2006Tran Luan CIntegrated circuit fabrication
US20060220639 *9 Mar 20065 Oct 2006Impinj, Inc.Fault tolerant non volatile memories and methods
US20060228854 *8 Jun 200612 Oct 2006Luan TranMethods for increasing photo alignment margins
US20060240362 *20 Jun 200626 Oct 2006Sandhu Gurtej SMethod to align mask patterns
US20060258162 *24 Jul 200616 Nov 2006Abatchev Mirzafer KMethod for integrated circuit fabrication using pitch multiplication
US20060262511 *24 Jul 200623 Nov 2006Abatchev Mirzafer KMethod for integrated circuit fabrication using pitch multiplication
US20060263699 *23 May 200523 Nov 2006Mirzafer AbatchevMethods for forming arrays of a small, closely spaced features
US20060264000 *31 Jul 200623 Nov 2006Luan TranMethods for increasing photo-alignment margins
US20060273456 *2 Jun 20057 Dec 2006Micron Technology, Inc., A CorporationMultiple spacer steps for pitch multiplication
US20060278911 *14 Jun 200514 Dec 2006Eppich Anton PRelaxed-pitch method of aligning active area to digit line
US20060281266 *9 Jun 200514 Dec 2006Wells David HMethod and apparatus for adjusting feature size and position
US20070018206 *6 Jul 200525 Jan 2007Leonard ForbesSurround gate access transistors with grown ultra-thin bodies
US20070018223 *31 Jul 200625 Jan 2007Micron Technology Inc.Dram including a vertical surround gate transistor
US20070026672 *29 Jul 20051 Feb 2007Micron Technology, Inc.Pitch doubled circuit layout
US20070045712 *1 Sep 20051 Mar 2007Haller Gordon AMemory cell layout and process flow
US20070047314 *31 Aug 20051 Mar 2007Micron Technology, Inc.Programming method for NAND EEPROM
US20070048674 *1 Sep 20051 Mar 2007Wells David HMethods for forming arrays of small, closely spaced features
US20070049030 *1 Sep 20051 Mar 2007Sandhu Gurtej SPitch multiplication spacers and methods of forming the same
US20070049032 *1 Sep 20051 Mar 2007Mirzafer AbatchevProtective coating for planarization
US20070050748 *30 Aug 20051 Mar 2007Micron Technology, Inc., A CorporationMethod and algorithm for random half pitched interconnect layout with constant spacing
US20070051997 *31 Aug 20058 Mar 2007Gordon HallerSemiconductor memory device
US20070090363 *25 Jul 200526 Apr 2007Abbott Todd RDram including a vertical surround gate transistor
US20070105357 *21 Dec 200610 May 2007Micron Technology, Inc.Silicided recessed silicon
US20070114576 *11 Jan 200724 May 2007Leonard ForbesSurround gate access transistors with grown ultra-thin bodies
US20070128856 *1 Feb 20077 Jun 2007Micron Technology, Inc.Pitch reduced patterns relative to photolithography features
US20070138526 *31 Jan 200721 Jun 2007Micron Technology, Inc.Pitch reduced patterns relative to photolithography features
US20070159617 *11 Jan 200612 Jul 2007Mackey Jeffrey LPhotolithographic systems and methods for producing sub-diffraction-limited features
US20070190463 *26 Mar 200716 Aug 2007Micron Technology, Inc.Method to align mask patterns
US20070205438 *2 Mar 20066 Sep 2007Werner JuenglingMasking process for simultaneously patterning separate regions
US20070205443 *2 Mar 20066 Sep 2007Werner JuenglingVertical gated access transistor
US20070238299 *3 May 200711 Oct 2007Micron Technology, Inc.Simplified pitch doubling process flow
US20070238308 *7 Apr 200611 Oct 2007Ardavan NiroomandSimplified pitch doubling process flow
US20070249170 *25 Apr 200625 Oct 2007David KewleyProcess for improving critical dimension uniformity of integrated circuit arrays
US20070261016 *24 Apr 20068 Nov 2007Sandhu Gurtej SMasking techniques and templates for dense semiconductor fabrication
US20070281219 *1 Jun 20066 Dec 2007Sandhu Gurtej SMasking techniques and contact imprint reticles for dense semiconductor fabrication
US20080008006 *12 Sep 200710 Jan 2008Micron Technology, Inc.Programming method for NAND EEPROM
US20080019181 *20 Jul 200624 Jan 2008Winbond Electronics Corp.Multi-level operation in nitride storage memory cell
US20080057692 *30 Aug 20066 Mar 2008Wells David HSingle spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
US20080070165 *14 Sep 200620 Mar 2008Mark FischerEfficient pitch multiplication process
US20080085612 *5 Oct 200610 Apr 2008Micron Technology, Inc.Method to deposit conformal low temperature SiO2
US20080149593 *4 Mar 200826 Jun 2008Micron Technology, Inc.Multiple deposition for integration of spacers in pitch multiplication process
US20080227293 *13 May 200818 Sep 2008Micron Technology, Inc.Integrated circuit fabrication
US20080254627 *19 May 200816 Oct 2008Micron Technology, Inc.Method for adjusting feature size and position
US20080261349 *19 May 200823 Oct 2008Micron Technology, Inc.Protective coating for planarization
US20080290374 *4 Aug 200827 Nov 2008Micron Technology, Inc.Layout for high density conductive interconnects
US20080291730 *10 Jul 200827 Nov 2008Micron Technology, Inc.Reducing effects of program disturb in a memory device
US20080299753 *22 Jul 20084 Dec 2008Figura Thomas APeripheral Gate Stacks and Recessed Array Gates
US20080299774 *4 Jun 20074 Dec 2008Micron Technology, Inc.Pitch multiplication using self-assembling materials
US20090011560 *16 Sep 20088 Jan 2009Seiichi AritomeMultiple select gate architecture with select gates of different lengths
US20090035665 *31 Jul 20075 Feb 2009Micron Technology, Inc.Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
US20090046507 *24 Oct 200819 Feb 2009Micron Technology, Inc.Reducing effects of program disturb in a memory device
US20090046508 *1 Aug 200619 Feb 2009Chun ChenProgramming methods for multi-level flash EEPROMs
US20090104744 *26 Nov 200823 Apr 2009Micron Technology, Inc.Vertical gated access transistor
US20090130852 *27 Jan 200921 May 2009Micron Technology, Inc.Process for improving critical dimension uniformity of integrated circuit arrays
US20090152645 *18 Dec 200718 Jun 2009Micron Technology, Inc.Methods for isolating portions of a loop of pitch-multiplied material and related structures
US20090203216 *15 Apr 200913 Aug 2009Micron Technology, Inc.Photolithographic systems and methods for producing sub-diffraction-limited features
US20090215236 *4 May 200927 Aug 2009Micron Technology, Inc.Relaxed-pitch method of aligning active area to digit line
US20090239366 *2 Jun 200924 Sep 2009Hasan NejadMethod Of Forming A Transistor Gate Of A Recessed Access Device, Method Of Forming A Recessed Transistor Gate And A Non-Recessed Transistor Gate, And Method Of Fabricating An Integrated Circuit
US20090258492 *22 Jun 200915 Oct 2009Micron Technology, Inc.Multiple spacer steps for pitch multiplication
US20090271758 *7 Jul 200929 Oct 2009Micron Technology, Inc.Methods for forming arrays of small, closely spaced features
US20090273979 *14 Jul 20095 Nov 2009Micron Technology, Inc.Programming method to reduce word line to word line breakdown for nand flash
US20100029081 *12 Oct 20094 Feb 2010Micron Technology, Inc.Single spacer process for multiplying pitch by a factor greater than two and related intermediate ic structures
US20100062579 *11 Sep 200811 Mar 2010Micron Technology, Inc.Self-aligned trench formation
US20100092890 *11 Dec 200915 Apr 2010Micron Technology, Inc.Method to align mask patterns
US20100092891 *11 Dec 200915 Apr 2010Micron Technology, Inc.Pitch reduced patterns relative to photolithography features
US20100112489 *13 Jan 20106 May 2010Micron Technology, Inc.Efficient pitch multiplication process
US20100130016 *24 Aug 200927 May 2010Micron Technology, Inc.Methods of forming a masking pattern for integrated circuits
US20100142273 *3 Feb 201010 Jun 2010Round Rock Research, LlcProgramming methods for multi-level memory devices
US20100144107 *10 Feb 201010 Jun 2010Micron Technology, Inc.Semiconductor Memory Device
US20100148249 *22 Feb 201017 Jun 2010Micron Technology, Inc.Method Of Manufacturing A Memory Device
US20100202210 *20 Apr 201012 Aug 2010Micron Technology, Inc.Reducing effects of program disturb in a memory device
US20100203727 *17 Feb 201012 Aug 2010Micron Technology, Inc.Method for integrated circuit fabrication using pitch multiplication
US20100210111 *28 Apr 201019 Aug 2010Round Rock Research, LlcPitch reduced patterns relative to photolithography features
US20100230733 *24 May 201016 Sep 2010Micron Technology, Inc.Vertical gated access transistor
US20100243161 *10 Jun 201030 Sep 2010Micron Technology, Inc.Pitch multiplied mask patterns for isolated features
US20100258966 *24 Jun 201014 Oct 2010Micron Technology, Inc.Masking techniques and contact imprint reticles for dense semiconductor fabrication
US20100267240 *30 Jun 201021 Oct 2010Micron Technology, Inc.Pitch multiplication spacers and methods of forming the same
US20100289070 *28 Jul 201018 Nov 2010Micron Technology, Inc.Methods for isolating portions of a loop of pitch-multiplied material and related structures
US20110006347 *6 Jul 201013 Jan 2011Round Rock Research, LlcLayout for high density conductive interconnects
US20110014574 *30 Sep 201020 Jan 2011Micron Technology, Inc.Method of forming pitch multipled contacts
US20110034024 *18 Oct 201010 Feb 2011Micron Technology, Inc.Method and algorithm for random half pitched interconnect layout with constant spacing
US20110042755 *5 Nov 201024 Feb 2011Micron Technology, Inc.Memory device comprising an array portion and a logic portion
US20110116311 *12 May 201019 May 2011Micron Technology, Inc.Reduction of punch-through disturb during programming of a memory device
US20110117743 *21 Jan 201119 May 2011Round Rock Research, LlcMultiple deposition for integration of spacers in pitch multiplication process
US20110121383 *19 Nov 201026 May 2011Micron Technology, Inc.Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
US20110122689 *8 Feb 201126 May 2011Micron Technology, Inc.Reducing effects of program disturb in a memory device
US20110140184 *14 Feb 201116 Jun 2011Leonard ForbesSurround gate access transistors with grown ultra-thin bodies
US20110156116 *10 Mar 201130 Jun 2011Micron Technology, Inc.Relaxed-pitch method of aligning active area to digit line
US20110165744 *17 Mar 20117 Jul 2011Micron TechnologyMemory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
US20110183507 *11 Apr 201128 Jul 2011Micron Technology Inc.Peripheral Gate Stacks and Recessed Array Gates
CN100587843C1 Nov 20063 Feb 2010华邦电子股份有限公司Programmed method for multi-level nitride memory unit and multi-level flash memory element
Classifications
U.S. Classification365/185.18, 365/185.28, 365/185.33, 365/185.24, 365/185.26, 365/185.03
International ClassificationG11C11/34, G11C11/56, G11C16/04, G11C7/00
Cooperative ClassificationG11C16/0483, G11C11/5628
European ClassificationG11C16/04N, G11C11/56D2
Legal Events
DateCodeEventDescription
2 Aug 2001ASAssignment
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, CHUN;PRALL, KIRK D.;REEL/FRAME:012060/0781
Effective date: 20010706
21 Jul 2006FPAYFee payment
Year of fee payment: 4
4 Jan 2010ASAssignment
Owner name: ROUND ROCK RESEARCH, LLC,NEW YORK
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416
Effective date: 20091223
Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416
Effective date: 20091223
21 Jul 2010FPAYFee payment
Year of fee payment: 8
23 Jul 2014FPAYFee payment
Year of fee payment: 12