US6324636B1 - Memory management system and method - Google Patents
Memory management system and method Download PDFInfo
- Publication number
- US6324636B1 US6324636B1 US09/419,217 US41921799A US6324636B1 US 6324636 B1 US6324636 B1 US 6324636B1 US 41921799 A US41921799 A US 41921799A US 6324636 B1 US6324636 B1 US 6324636B1
- Authority
- US
- United States
- Prior art keywords
- address
- confirmer
- pointer
- store
- addresses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000015654 memory Effects 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims description 43
- 238000010586 diagram Methods 0.000 description 20
- 238000007726 management method Methods 0.000 description 15
- 230000004075 alteration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 239000000872 buffer Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000013523 data management Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000135 prohibitive effect Effects 0.000 description 1
- 238000010845 search algorithm Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/90—Details of database functions independent of the retrieved data types
- G06F16/903—Querying
- G06F16/90335—Query processing
- G06F16/90339—Query processing by using parallel associative memories or content-addressable memories
Definitions
- the present invention relates generally to the field of computer memories and more particularly to a memory management system and method.
- RAM Random Access Memory
- CPU Central Processing Unit
- CAM Content Addressable Memory
- the CPU provides a data element to the CAM and the CAM determines an address for the data element.
- CAMs are architecturally the inverse of RAMS. CAMs have typically been used in applications requiring high bandwidth and low latency requirements. CAMs provide significant improvements over alternative RAM-based search algorithms such as binary/tree searches or look-aside tag buffers. CAMs are hardware devices and as a result require the designer to determine the exact maximum key width and depth. Typical commercial CAM semiconductor chips are 64 bits wide and 1024 bits deep. As a result, applications requiring more than a few thousand entries are prohibitive in cost, power consumption and on-board real-estate.
- associative memories Another data management scheme is associative memories.
- associative memories use hash tables that return an arbitrary memory location for a data element. Hashing tables are commonly used in large database applications. Unfortunately, hashing tables suffer from a large number of collisions as the memory store approaches 70% full. The collision management requires external memory management schemes that require extra processing and memory space.
- FIG. 1 is a block diagram of a memory management system in accordance with one embodiment of the invention.
- FIG. 2 is a schematic diagram of a memory store in accordance with one embodiment of the invention.
- FIG. 3 is a schematic diagram of a memory store in accordance with one embodiment of the invention.
- FIG. 4 is a schematic diagram of a memory store in accordance with one embodiment of the invention.
- FIG. 5 is a schematic diagram of a memory store in accordance with one embodiment of the invention.
- FIG. 6 is a schematic diagram of a memory store in accordance with one embodiment of the invention.
- FIG. 7 is a schematic diagram of a memory store in accordance with one embodiment of the invention.
- FIG. 8 is a schematic diagram of a memory store in accordance with one embodiment of the invention.
- FIG. 9 is a schematic diagram of a memory store in accordance with one embodiment of the invention.
- FIG. 10 is a schematic diagram of a memory store in accordance with one embodiment of the invention.
- the memory management system includes a transform generator capable of generating an address and a confirmer from a key.
- a controller is connected to the transform generator and sends the key to the transform generator and receives the address and the confirmer.
- a store is connected to the controller and has a plurality of addresses. Each of the plurality of addresses has a confirmer location, a forward pointer location, a primary flag, an allocated flag and an association location.
- the transform generator is a linear feedback shift register (polynomial code).
- the transform generator is Cyclical Redundancy Code (CRC) generator. A portion of the result from the generator is used as the address and a second portion is used as the confirmer.
- CRC Cyclical Redundancy Code
- the memory management system described above provides fast lookup capabilities since the data element (key) determines the address of the association. In addition, the probability of collisions is very low or nonexistent. This means that extended linked lists do not have to be searched.
- the memory management system can be implemented in software or in hardware. As a result the number of entries and the width of the entries can be easily adjusted. The memory management system can handle from a few entries to tens of millions of entries with similar performance characteristics.
- FIG. 1 is a block diagram of a memory management system 20 in accordance with one embodiment of the invention.
- the memory management system 20 has three main elements: a transform generator 22 ; a controller 24 and a store (memory) 26 .
- the transform generator determines an address 28 and a confirmer 30 from a key.
- the key is how the data is stored and looked up. For instance, a telephone information service would want a list of all the customer's names and telephone numbers. An operator would look up a telephone by a customer's name. The customer's name is the key and the telephone number may be the association.
- the transform generator 22 receives the key and performs a mathematical process that returns the address 28 and confirmer 30 .
- the address 28 and confirmer 30 together are called the icon or transform of the key.
- the ideal mathematical operation provides an even distribution of addresses even when the keys are not evenly distributed. In addition, the ideal mathematical operation does not result in a collision (same address and same confirmer) for different keys. Any mathematical operation that meets these criteria is acceptable. However, other mathematical operations may also be acceptable.
- One polynomial code that performs well against these criteria is (1E543279765927881).
- the controller 24 stores or looks up an association 32 based on the address 28 and confirmer 30 .
- the store 26 contains the confirmer location 30 , a forward pointer location 34 , a primary flag 36 and an allocated flag 38 .
- a lookup command requires the controller to determine a first address (lookup address) and first confirmer (lookup confirmer) upon receiving a first key. The controller then determines if an allocated flag is set. When the allocated flag is set, the controller compares the first confirmer to a stored confirmer at the first address. When the stored confirmer and the first confirmer are the same the controller reads a stored association. The purpose of these locations will be explained in more detail with respect to FIGS. 2-8.
- FIG. 2 is a schematic diagram of a memory store 50 in accordance with one embodiment of the invention.
- the store 50 shows an example with sixteen addresses. Generally, the number of address available will be based on a factor of two, for instance, 8 , 16 , 32 , etc.
- the store 50 is merely a simple example to demonstrate how a store is initialized.
- the confirmer locations 52 contain a reverse pointer 54 .
- the confirmer location 52 for address one is shown as zero.
- the forward pointer locations 56 each contain a forward pointer 58 .
- the primary flag locations 60 are shown as zero's (unset). However, the primary flag locations 60 are free until an entry has been stored at the address.
- the allocated flag locations 62 are initialized to zero (unset).
- the association locations 64 are free and have no entries in this example. Note that an association is not required for the invention.
- the reverse pointer 54 is stored in a combination of free locations 52 , 60 , 64 .
- the free locations upon initialization are the confirmer location 52 , the primary flag location 60 and the association location 64 .
- the initialization process requires specifying a store 50 having a plurality of addresses 66 .
- a confirm location 52 is defined for the each of the plurality of addresses 66 .
- a forward pointer location 56 for each of the addresses is defined.
- a forward address pointer 58 is entered for the forward pointer location for each of the plurality of addresses.
- the primary flag location 60 and allocated flag location 62 are defined for each of the addresses 66 .
- An association location 64 is defined for each of the addresses.
- a reverse address pointer 54 is then entered in a free location for each of the addresses 66 . As a result we have a doubly linked free list (forward and reverse pointers).
- FIG. 3 is a schematic diagram of a memory store 50 in accordance with one embodiment of the invention.
- the figure illustrates a store at address five 70 assuming an initial state shown in FIG. 2 .
- the controller receives a store request, it sends a key to the transform generator.
- the transform generator returns an address (store address) and a confirmer (store confirmer).
- the controller then proceeds to store an association and confirmer at the address.
- the storing process requires that the controller first determines if the allocate flag 62 is set at the one of the plurality of address returned by the transform generator. When the allocated flag is not set, the controller moves to a reverse address indicated by the reverse pointer address. In the figures we see that the allocated flag 72 is not set for address five (first address) 70 in FIG. 2 .
- the reverse address pointer 74 at address five 70 is address four 76 .
- address four (reverse address) 76 we move to address four (reverse address) 76 and update the forward pointer at address four 76 to equal the forward pointer at address five 70 .
- the forward pointer 78 (FIG. 3) at address four 76 is six.
- Address six is the next (forward) free address.
- the controller moves to the forward address 80 pointed to by the forward pointer 82 at the address five 70 (See FIG. 2 ).
- At address six (forward address) 80 we set the reverse pointer 84 equal to the reverse pointer 74 at address five 70 .
- confirmer (C 1 , first confirmer) 86 is entered at confirmer location 52 for the address five 70 .
- the forward pointer 88 is set to point to address five.
- the primary flag 90 and the allocated flag 92 are set.
- the association (A 1 ) 94 is stored in the association location for address five.
- the store 50 of FIG. 3 shows an example of the state of store 50 after a store operation at address five.
- FIG. 4 is a schematic diagram of a memory store 50 in accordance with one embodiment of the invention.
- FIG. 4 shows the state of store 50 after a collision store at address five.
- FIG. 4 assumes that the initial state of the store 50 before the collision store is shown in FIG. 3 . Note that collisions are extremely rare when the appropriate polynomial code is selected. However, collisions cannot be ruled out in all cases.
- the controller receives a key and association for store.
- the transform generator returns an address of five.
- the controller checks if the allocated flag 92 is set at address five 70 . When the allocated flag 92 is set, the controller determines if the primary flag 90 is set. When the primary flag 90 is set, the controller moves to a next free address. The next address can be found by forward searching or backwards searching.
- FIG. 4 shows an example where forward searching is used.
- the controller moves to the next address (second address) 80 and determines if the allocated flag is set. When the allocated flag is not set, then the address is the next free address.
- the next free address 80 is address six.
- the forward pointer 88 at address five is set to address six.
- the forward pointer 78 at address four is updated to equal the forward pointer at address six 80 (i.e., seven).
- the reverse pointer 100 at address seven 102 is set equal to reverse pointer 84 at address six 80 .
- the confirmer (C 2 , second confirmer) 104 can then be stored at address six 60 .
- the forward pointer 106 is set equal to five.
- the allocated flag 108 is set and the association (A 2 ) 110 is stored.
- FIG. 5 is a schematic diagram of a memory store 50 in accordance with one embodiment of the invention.
- FIG. 5 shows the state the store 50 after “secondary collision” store at address six assuming that FIG. 4 represents the initial condition of the store 50 .
- the controller receives a key and an association for store.
- the transform generator returns the address six 80 .
- the controller checks the allocated flag 108 (FIG. 4) and determines that address six 80 is allocated.
- the controller checks the primary flag 60 at address six 80 and determines that the primary flag is not set. This tells the controller that the store at address six 80 is a collision store, not a primary store.
- the controller finds a free address (i.e, address seven 102 ).
- a free address is an address in which the allocated flag 62 is not set.
- the information stored at address six 80 needs to be moved to address seven 102 .
- First the reverse pointer 120 at address eight 122 has to be updated to equal the reverse pointer at address seven 102 (FIG. 4 ).
- Next the forward pointer 78 at address four 76 has to be updated to be equal to the forward pointer at address seven 102 (FIG. 4 ).
- the contents (first confirmer, assocition) of address six 80 can now be moved to address seven 102 .
- the confirmer (C 3 ) 124 and the association (A 3 ) 126 are stored at address six 80 .
- the forward pointer at address six 80 is update to be address six.
- the primary flag and the allocated flag are set at address six.
- the forward pointer of address five 70 is updated to read address seven 102 .
- FIG. 6 is a schematic diagram of a memory store 50 in accordance with one embodiment of the invention.
- FIG. 6 shows the state of the store 50 after a delete of the entry at address six assuming that FIG. 5 shows the initial state of the store.
- the controller receives a delete command and a key.
- the transform generator determines a delete address (address six) and delete confirmer.
- the controller compares the delete confirmer to the stored confirmer (C 3 ) at address six 80 .
- the stored confirmer (C 3 ) is the same as the delete confirmer, the stored confirmer 124 and the stored association 126 are deleted.
- the allocated flag 130 and the primary flag 132 are unset.
- the controller searches for a next free address. In this case the next free address is address eight 122 .
- the forward pointer 88 at the delete address 80 (address six) is updated to the next free address 122 .
- the reverse address pointer 134 at the delete address 80 is set equal to the reverse address at the next free address 122 .
- the reverse address 136 at the next free address 122 is set equal to the delete address (i.e, address six).
- the previous free address is found using the reverse address 120 (FIG. 5) at the next free address 122 .
- the forward pointer 138 at the previous free address is updated to equal the delete address 80 .
- the doubly linked free list now completely updated.
- FIG. 7 is a schematic diagram of a memory store 50 in accordance with one embodiment of the invention.
- FIG. 7 shows the state of the store 50 after a delete of the entry at address seven 102 assuming that FIG. 5 shows the initial state of the store.
- the controller receives a delete command and a key.
- the transform generator determines a delete address (address seven) and delete confirmer.
- the controller compares the delete confirmer to the stored confirmer (C 2 ) at address seven 102 .
- the stored confirmer (C 2 ) is the same as the delete confirmer, the stored confirmer 104 and the stored association (A 2 ) are deleted.
- the allocated flag 140 is unset.
- the controller searches for a next free address (i.e., address eight 122 ).
- the controller then updates the reverse pointer 142 for the free address to equal the reverse pointer 120 at the next free address 122 .
- the controller then updates the forward pointer 144 at the delete address to equal the next free address.
- the reverse pointer 146 of the next free address 122 is updated to equal the delete address.
- a reverse address (address four 76 ) has its forward address 148 updated to equal the delete address. The delete operation is complete.
- FIG. 8 is a schematic diagram of a memory store 50 in accordance with one embodiment of the invention.
- FIG. 8 shows the state of the store 50 after a delete of the entry at address five 70 assuming that FIG. 5 shows the initial state of the store.
- the controller receives a delete command and a key.
- the transform generator determines a delete address (address five) and delete confirmer.
- the controller compares the delete confirmer to the stored confirmer (C 1 ) at address five 70 .
- the controller determines if the forward pointer 78 points to the delete address 70 .
- the controller moves the confirmer (C 2 ) and association (A 2 ) at the forward pointer address 102 to the delete address 70 .
- the forward pointer 150 at the delete address 70 is updated to equal the delete address 70 .
- a reverse pointer 152 at the forward pointer address 102 is updated using the next free address 122 reverse pointer 120 .
- the forward pointer 154 at the forward pointer address 102 is set equal to the next free address 122 .
- the forward pointer 156 at the reverse address 76 is set equal to the forward pointer address 102 .
- FIG. 9 is a schematic diagram of a memory store 200 in accordance with one embodiment of the invention.
- FIGS. 9 & 10 illustrate the versatility of the store to handle different numbers of entries.
- FIG. 9 shows an example of a store of the memory management system, when the required number of entries (addresses) is 100 Million.
- the system uses a transform that has sixty-four bits (first number of bits). A portion of the sixty-four bits is used as the address and the other portion is used as the confirmer.
- the controller determines that the required number of entries requires an address 202 having an address number of bits equal to 27 bits.
- the forward pointer location 204 is set to have a forward pointer number of bits (twenty-seven) equal to the address number of bits.
- the confirmer location 206 is set to have a confirmer number of bits equal (thirty-seven) to the first number of bits (sixty-four—transform) less the forward pointer number of bits (twenty-seven). Note that the transform has to be large enough to cover the required number of entries. Ideally, the transform will be large enough (range of numbers) to cover more than the required number of entries.
- the primary flag location 208 and the allocation flag location 210 each requires one bit.
- the association 212 is optional, but in this example is shown as having thirty bits. Note that just to list all the potential transforms would require sixty-four bits.
- the store 200 without the optional association only requires sixty-six bits to store the entries or two more bits than listing all the transforms.
- FIG. 10 is a schematic diagram of a memory store 200 in accordance with one embodiment of the invention.
- the store 200 needs to be able to handle 10 billion entries.
- the address 202 is thirty-four bits.
- the forward pointer 204 is also set to thirty-four bits.
- the confirmer 206 is therefore set to have thirty bits. The size of the confirmer and forward pointer are traded to best accommodate and required number of entries. Note that the overall store is still ninety-six bits wide.
- the memory management system is capable trading the confirmer size and forward pointer size to accommodate almost any number or entries.
- the methods described herein can be implemented as computer-readable instructions stored on a computer-readable storage medium that when executed by a computer will perform the methods described herein.
Abstract
Description
Claims (36)
Priority Applications (11)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/419,217 US6324636B1 (en) | 1999-10-15 | 1999-10-15 | Memory management system and method |
US09/672,754 US6493813B1 (en) | 1999-10-15 | 2000-09-28 | Method for forming a hashing code |
BR0014863-6A BR0014863A (en) | 1999-10-15 | 2000-10-11 | Memory management system and method |
CA002387790A CA2387790A1 (en) | 1999-10-15 | 2000-10-11 | Memory management system and method |
JP2001532398A JP2003512672A (en) | 1999-10-15 | 2000-10-11 | Memory management system and method |
AU78780/00A AU7878000A (en) | 1999-10-15 | 2000-10-11 | Memory management system and method |
EP00968939A EP1240588A4 (en) | 1999-10-15 | 2000-10-11 | Memory management system and method |
CN00816867A CN1408086A (en) | 1999-10-15 | 2000-10-11 | Memory management system and method |
PCT/US2000/028043 WO2001029671A1 (en) | 1999-10-15 | 2000-10-11 | Memory management system and method |
MXPA02003778A MXPA02003778A (en) | 1999-10-15 | 2000-10-11 | Memory management system and method. |
US09/966,350 US20020038413A1 (en) | 1999-10-15 | 2001-09-28 | Memory management system and method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/419,217 US6324636B1 (en) | 1999-10-15 | 1999-10-15 | Memory management system and method |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/672,754 Continuation-In-Part US6493813B1 (en) | 1999-10-15 | 2000-09-28 | Method for forming a hashing code |
US09/966,350 Continuation US20020038413A1 (en) | 1999-10-15 | 2001-09-28 | Memory management system and method |
Publications (1)
Publication Number | Publication Date |
---|---|
US6324636B1 true US6324636B1 (en) | 2001-11-27 |
Family
ID=23661297
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/419,217 Expired - Fee Related US6324636B1 (en) | 1999-10-15 | 1999-10-15 | Memory management system and method |
US09/966,350 Abandoned US20020038413A1 (en) | 1999-10-15 | 2001-09-28 | Memory management system and method |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/966,350 Abandoned US20020038413A1 (en) | 1999-10-15 | 2001-09-28 | Memory management system and method |
Country Status (9)
Country | Link |
---|---|
US (2) | US6324636B1 (en) |
EP (1) | EP1240588A4 (en) |
JP (1) | JP2003512672A (en) |
CN (1) | CN1408086A (en) |
AU (1) | AU7878000A (en) |
BR (1) | BR0014863A (en) |
CA (1) | CA2387790A1 (en) |
MX (1) | MXPA02003778A (en) |
WO (1) | WO2001029671A1 (en) |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4527239A (en) * | 1983-11-28 | 1985-07-02 | Brandin Christopher L | Digital data storage methods and apparatus |
US5249265A (en) * | 1989-10-24 | 1993-09-28 | International Business Machines Corporation | Structure storage management in a graphics display device |
US5287499A (en) * | 1989-03-22 | 1994-02-15 | Bell Communications Research, Inc. | Methods and apparatus for information storage and retrieval utilizing a method of hashing and different collision avoidance schemes depending upon clustering in the hash table |
US5339398A (en) * | 1989-07-31 | 1994-08-16 | North American Philips Corporation | Memory architecture and method of data organization optimized for hashing |
US5414704A (en) * | 1992-10-22 | 1995-05-09 | Digital Equipment Corporation | Address lookup in packet data communications link, using hashing and content-addressable memory |
US5717916A (en) * | 1994-09-30 | 1998-02-10 | Vlsi Technology, Inc. | Method for providing an improved fully associative cache memory having a finite state machine and linked list structure |
-
1999
- 1999-10-15 US US09/419,217 patent/US6324636B1/en not_active Expired - Fee Related
-
2000
- 2000-10-11 MX MXPA02003778A patent/MXPA02003778A/en unknown
- 2000-10-11 AU AU78780/00A patent/AU7878000A/en not_active Abandoned
- 2000-10-11 WO PCT/US2000/028043 patent/WO2001029671A1/en not_active Application Discontinuation
- 2000-10-11 CN CN00816867A patent/CN1408086A/en active Pending
- 2000-10-11 EP EP00968939A patent/EP1240588A4/en not_active Withdrawn
- 2000-10-11 JP JP2001532398A patent/JP2003512672A/en active Pending
- 2000-10-11 BR BR0014863-6A patent/BR0014863A/en not_active Application Discontinuation
- 2000-10-11 CA CA002387790A patent/CA2387790A1/en not_active Abandoned
-
2001
- 2001-09-28 US US09/966,350 patent/US20020038413A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4527239A (en) * | 1983-11-28 | 1985-07-02 | Brandin Christopher L | Digital data storage methods and apparatus |
US5287499A (en) * | 1989-03-22 | 1994-02-15 | Bell Communications Research, Inc. | Methods and apparatus for information storage and retrieval utilizing a method of hashing and different collision avoidance schemes depending upon clustering in the hash table |
US5339398A (en) * | 1989-07-31 | 1994-08-16 | North American Philips Corporation | Memory architecture and method of data organization optimized for hashing |
US5249265A (en) * | 1989-10-24 | 1993-09-28 | International Business Machines Corporation | Structure storage management in a graphics display device |
US5414704A (en) * | 1992-10-22 | 1995-05-09 | Digital Equipment Corporation | Address lookup in packet data communications link, using hashing and content-addressable memory |
US5717916A (en) * | 1994-09-30 | 1998-02-10 | Vlsi Technology, Inc. | Method for providing an improved fully associative cache memory having a finite state machine and linked list structure |
Non-Patent Citations (1)
Title |
---|
Schneider et al., "Concepts in Data Structures and Software Development", West Publishing Co., pp. 111, 115, 118-131, 137-145, and 314-329, 1991. * |
Also Published As
Publication number | Publication date |
---|---|
US20020038413A1 (en) | 2002-03-28 |
CA2387790A1 (en) | 2001-04-26 |
BR0014863A (en) | 2003-04-29 |
AU7878000A (en) | 2001-04-30 |
JP2003512672A (en) | 2003-04-02 |
MXPA02003778A (en) | 2004-05-05 |
EP1240588A1 (en) | 2002-09-18 |
CN1408086A (en) | 2003-04-02 |
WO2001029671A1 (en) | 2001-04-26 |
EP1240588A4 (en) | 2004-08-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6353873B1 (en) | Apparatus and method to determine a longest prefix match in a content addressable memory | |
US7373514B2 (en) | High-performance hashing system | |
US6434662B1 (en) | System and method for searching an associative memory utilizing first and second hash functions | |
US7499912B2 (en) | Search method using coded keys | |
Bender et al. | Bloom filters, adaptivity, and the dictionary problem | |
US7043494B1 (en) | Fast, deterministic exact match look-ups in large tables | |
US8295286B2 (en) | Apparatus and method using hashing for efficiently implementing an IP lookup solution in hardware | |
US7590625B1 (en) | Method and system for network load balancing with a compound data structure | |
US20020138648A1 (en) | Hash compensation architecture and method for network address lookup | |
US7873041B2 (en) | Method and apparatus for searching forwarding table | |
US5634110A (en) | Cache coherency using flexible directory bit vectors | |
JPH0749812A (en) | Memory address controller using hash address tag in page table | |
KR101434065B1 (en) | Method and device for improving scalabilty of longest prefix match | |
US20080281773A1 (en) | Data storage method and data storage structure | |
US7478109B1 (en) | Identification of a longest matching prefix based on a search of intervals corresponding to the prefixes | |
KR20210027625A (en) | Method for managing of memory address mapping table for data storage device | |
US7483426B2 (en) | Look-up table expansion method | |
US6493813B1 (en) | Method for forming a hashing code | |
US6324636B1 (en) | Memory management system and method | |
US11899985B1 (en) | Virtual modules in TCAM | |
EP0563282B1 (en) | Paging process using extension tables | |
CN113342706A (en) | Write-optimized extensible hash index structure based on nonvolatile memory and inserting, refreshing and deleting methods | |
US20020053002A1 (en) | System for associative processing | |
US8219538B2 (en) | Search device and search method | |
JP2001051856A (en) | Common memory and common memory managing device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: NEO-CORE, LLC, COLORADO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BRANDIN, CHRISTOPHER LOCKTON;REEL/FRAME:010325/0108 Effective date: 19991014 |
|
AS | Assignment |
Owner name: NEOCORE INC. A DELAWARE CORPORATION, COLORADO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEO-CORE, LLC A COLORADO LIMITED LIABILITY CORPORATION;REEL/FRAME:011700/0767 Effective date: 20010330 |
|
AS | Assignment |
Owner name: BAKER COMMUNICATIONS FUND II (O.P) L.P., NEW YORK Free format text: SECURITY INTEREST;ASSIGNOR:NEOCORE INC.;REEL/FRAME:013563/0179 Effective date: 20020826 |
|
AS | Assignment |
Owner name: XPRIORI, LLC, COLORADO Free format text: PURCHASE AGREEMENT;ASSIGNOR:NEOCORE, INC.;REEL/FRAME:016160/0280 Effective date: 20030911 |
|
REMI | Maintenance fee reminder mailed | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
SULP | Surcharge for late payment | ||
AS | Assignment |
Owner name: TRUST OF FRANCIS A. O'DONNELL, COLORADO Free format text: SECURITY AGREEMENT;ASSIGNOR:XPRIORI, LLC;REEL/FRAME:021018/0419 Effective date: 20080410 Owner name: O'DONNELL, RICHARD, COLORADO Free format text: SECURITY AGREEMENT;ASSIGNOR:XPRIORI, LLC;REEL/FRAME:021018/0419 Effective date: 20080410 Owner name: POLLAK, JOHN H., CALIFORNIA Free format text: SECURITY AGREEMENT;ASSIGNOR:XPRIORI, LLC;REEL/FRAME:021018/0419 Effective date: 20080410 Owner name: CHANDLER, BILL, COLORADO Free format text: SECURITY AGREEMENT;ASSIGNOR:XPRIORI, LLC;REEL/FRAME:021018/0419 Effective date: 20080410 Owner name: HOSSEINIOUN, ABOL, CALIFORNIA Free format text: SECURITY AGREEMENT;ASSIGNOR:XPRIORI, LLC;REEL/FRAME:021018/0419 Effective date: 20080410 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20091127 |