US5970240A - Method and apparatus for configurable memory emulation - Google Patents
Method and apparatus for configurable memory emulation Download PDFInfo
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- US5970240A US5970240A US08/883,025 US88302597A US5970240A US 5970240 A US5970240 A US 5970240A US 88302597 A US88302597 A US 88302597A US 5970240 A US5970240 A US 5970240A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
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Description
______________________________________ Time Slot/ Single Multiple Port Space Slot Instance Instances Configuration ______________________________________ 1/1 2K × 512 16 × (2K × 32) single port 2/1 4K × 256 8 × (4K × 32) 2-port 4/1 8K × 128 4 × (8K × 32) 4-port 8/1 16K × 64 2 × (16K × 32) 8-port 16/1 32K × 32 1 × (32K × 32) 16-port ______________________________________
______________________________________ Instance A 2K × 68 one write, one read ports Instance B 4K × 8 one write, two read ports Instance C 16K × 8 one write, one read ports ______________________________________
______________________________________ Data input signals 102 DI0.sub.-- [0:31] to DI15.sub.-- [0:31] Address input signals 104 and 104a A0.sub.-- [0:14] to A15.sub.-- [0:14] Write enablesignals 108 WE[0:15]Data output signals 106 DO0.sub.-- [0:31] to DO15.sub.-- [0:31] ______________________________________
______________________________________RAM address signals 114 RAM.sub.-- A[0:14]RAM data signals 120 RAM.sub.-- DQ[0:31] RAM output enable 132 RAM.sub.-- OE RAM write enables 118 RAM.sub.-- WE[0:3]RAM control signals 130 RAM.sub.-- CTRL[0:3] ______________________________________
______________________________________ User Memory Instance Pins Controller Pins ______________________________________ data inputs (InstA.sub.-- DI[0:31]) Port 6 data (DI6.sub.-- [0:31] [0:31] inputs [0:31] data inputs (InstA.sub.-- DI[32:63]) Port 7 data (DI7.sub.-- [0:31] [32:63] inputs [0:31] data inputs (InstA.sub.-- DI[64:67]) Port 8 data (DI8.sub.-- [0:3] [64:67] inputs [0:3] data outputs (InstA.sub.-- DO[0:31]) Port 0 data (DO0.sub.-- [0:31]) [0:31] outputs [0:31] data outputs (InstA.sub.-- DO[32:63]) Port 1 data (DO1.sub.-- [0:31]) [32:63] outputs [0:31] data outputs (InstA.sub.-- DO[64:67]) Port 2 data (DO2.sub.-- 0:3]) [64:67] outputs [0:3] read address InstA.sub.-- RA[0:10]) Port 0 address (A0.sub.-- [0:10]) inputs [0:10} inputs [0:10] Port 1 address (A1.sub.-- [0:10]) inputs [0:10] Port 2 address (A2.sub.-- [0:10]) inputs [0:10] write address (instA.sub.-- WA[0:10]) Port 6 address (A6.sub.-- [0:10]) inputs [0:10] inputs [0:10] Port 7 address (A7.sub.-- [0:10]) inputs [0:10] Port 8 address (A8.sub.-- [0:10]) inputs [0:10] write enable input (InstA.sub.-- WE) Port 6 write (WE6) enable input Port 7 write (WE7) enable input Port 8 write (WE8) enable input ______________________________________
______________________________________ User Memory Instance Pins Controller Pins ______________________________________ data inputs (InstB.sub.-- DI[0:7]) Port 9 data (DI9.sub.-- [0:7] [0:7] inputs [0:7] read port 1 (InstB.sub.-- D01[0:7]) Port 3 data (DO3.sub.-- [0:7] outputs [0:7] outputs [0:7] read port 2 (InstB.sub.-- D02[0:7]) Port 4 data (DO4.sub.-- 0:7] outputs [0:7] outputs [0:7] read address 1 (instB.sub.-- RA1[0:11]) Port 3 address (A3.sub.-- [0:11]) inputs [0:11] inputs [0:11] read address 2 (instB.sub.-- RA2[0:11]) Port 4 address (A4.sub.-- [0:11]) inputs [0:11] inputs [0:11] write address (InstB.sub.-- WA[0:11]) Port 9 address (A9.sub.-- [0:11]) inputs [0:11] inputs [0:11] write enable (InstB.sub.-- WE) Port 9 write (WE9) input enable input ______________________________________
______________________________________ User Memory Instance Pins Controller Pins ______________________________________ data inputs (InstC.sub.-- DI[0:7])Port 10 data (DI10.sub.-- [0:7] [0:7] inputs [0:7] data outputs (InstC.sub.-- D0[0:7]) Port 5 data (DO5.sub.-- [0:7] [0:7] outputs [0:7] read address (InstC.sub.-- RA[0:13]) Port 5 address (A5.sub.-- [0:13] inputs [0:13] inputs [0:13] write address (InstC.sub.-- WA[0:13])Port 10 address (A10.sub.-- [0:13]) inputs [0:13] inputs [0:13] write enable (InstC.sub.-- WE)Port 10 write (WE10) input enable input ______________________________________
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US08/883,025 US5970240A (en) | 1997-06-25 | 1997-06-25 | Method and apparatus for configurable memory emulation |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6255848B1 (en) * | 1999-04-05 | 2001-07-03 | Xilinx, Inc. | Method and structure for reading, modifying and writing selected configuration memory cells of an FPGA |
US6262596B1 (en) * | 1999-04-05 | 2001-07-17 | Xilinx, Inc. | Configuration bus interface circuit for FPGAS |
US6286088B1 (en) | 1999-06-28 | 2001-09-04 | Hewlett-Packard Company | Memory management system and method for relocating memory |
US20030074503A1 (en) * | 2001-10-15 | 2003-04-17 | Echartea Jesus Palomino | Bus frame protocol |
US20030088396A1 (en) * | 2001-11-06 | 2003-05-08 | Kuan Chou Chen | Apparatus in an ICE system |
US6581188B1 (en) * | 1999-07-29 | 2003-06-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of designing the same |
US20030188278A1 (en) * | 2002-03-26 | 2003-10-02 | Carrie Susan Elizabeth | Method and apparatus for accelerating digital logic simulations |
US20040043094A1 (en) * | 2002-08-30 | 2004-03-04 | Wengermanufacturing, Inc. | Method and apparatus for extrusion of food products including back pressure valve/diverter |
US6779170B1 (en) * | 2002-12-11 | 2004-08-17 | Nvidia Corporation | Method and apparatus for performing logic emulation |
US20040254780A1 (en) * | 2003-06-10 | 2004-12-16 | Mentor Graphics Corporation | Emulation of circuits with in-circuit memory |
US20050097230A1 (en) * | 2003-11-04 | 2005-05-05 | Chun-Pin Hsu | Circuit and system for expandably connecting electronic devices |
US20050267732A1 (en) * | 2004-06-01 | 2005-12-01 | Quickturn Design Systems, Inc. | Method of visualization in processor based emulation system |
US20060123202A1 (en) * | 2004-12-03 | 2006-06-08 | Alcatel | Memory based cross compare for cross checked systems |
US20060184721A1 (en) * | 2005-02-16 | 2006-08-17 | Chen Ben W | Configurable flash memory controller and method of use |
US20060200785A1 (en) * | 2003-01-17 | 2006-09-07 | Drazen Borkovic | Method and apparatus for the design and analysis of digital circuits with time division multiplexing |
US20070036005A1 (en) * | 2005-08-11 | 2007-02-15 | Samsung Electronics Co., Ltd. | Wrapper circuit and method for interfacing between non-muxed type memory controller and muxed type memory |
US7197438B1 (en) * | 2001-10-18 | 2007-03-27 | Virage Logic Corp. | System and method for memory compiler characterization |
US20070094534A1 (en) * | 2005-10-24 | 2007-04-26 | Andreev Alexander E | RRAM memory error emulation |
US20070285124A1 (en) * | 2004-11-08 | 2007-12-13 | Herman Schmit | Embedding Memory Between Tile Arrangement of a Configurable IC |
US20080100336A1 (en) * | 2005-03-15 | 2008-05-01 | Brad Hutchings | Hybrid Logic/Interconnect Circuit in a Configurable IC |
US20090204383A1 (en) * | 2008-02-07 | 2009-08-13 | Alexander Weiss | Procedure and Device for Emulating a Programmable Unit Providing System Integrity Control |
US7587697B1 (en) * | 2006-12-12 | 2009-09-08 | Tabula, Inc. | System and method of mapping memory blocks in a configurable integrated circuit |
US7652499B2 (en) | 2004-11-08 | 2010-01-26 | Tabula, Inc. | Embedding memory within tile arrangement of an integrated circuit |
US7797497B1 (en) | 2006-03-08 | 2010-09-14 | Tabula, Inc. | System and method for providing more logical memory ports than physical memory ports |
US7804730B2 (en) | 2005-03-15 | 2010-09-28 | Tabula, Inc. | Method and apparatus for accessing contents of memory cells |
US7825685B2 (en) | 2007-09-06 | 2010-11-02 | Tabula, Inc. | Configuration context switcher with a clocked storage element |
US7825684B2 (en) | 2005-03-15 | 2010-11-02 | Tabula, Inc. | Variable width management for a memory of a configurable IC |
US7825687B2 (en) | 2004-11-08 | 2010-11-02 | Tabula, Inc. | Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements |
US7839166B2 (en) | 2004-06-30 | 2010-11-23 | Tabula, Inc. | Configurable IC with logic resources with offset connections |
US7872496B2 (en) | 2004-02-14 | 2011-01-18 | Tabula, Inc. | Method of mapping a user design defined for a user design cycle to an IC with multiple sub-cycle reconfigurable circuits |
US20110029830A1 (en) * | 2007-09-19 | 2011-02-03 | Marc Miller | integrated circuit (ic) with primary and secondary networks and device containing such an ic |
US7930666B1 (en) | 2006-12-12 | 2011-04-19 | Tabula, Inc. | System and method of providing a memory hierarchy |
US7948266B2 (en) | 2004-02-14 | 2011-05-24 | Tabula, Inc. | Non-sequentially configurable IC |
US7962705B2 (en) | 2006-03-08 | 2011-06-14 | Tabula, Inc. | System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture |
US20110307233A1 (en) * | 1998-08-31 | 2011-12-15 | Tseng Ping-Sheng | Common shared memory in a verification system |
US8112468B1 (en) | 2007-03-22 | 2012-02-07 | Tabula, Inc. | Method and apparatus for performing an operation with a plurality of sub-operations in a configurable IC |
US8183882B2 (en) | 2004-11-08 | 2012-05-22 | Tabula, Inc. | Reconfigurable IC that has sections running at different reconfiguration rates |
US8244512B1 (en) * | 1998-08-31 | 2012-08-14 | Cadence Design Systems, Inc. | Method and apparatus for simulating a circuit using timing insensitive glitch-free (TIGF) logic |
US8726213B2 (en) | 2005-03-15 | 2014-05-13 | Tabula, Inc. | Method and apparatus for decomposing functions in a configurable IC |
US8755484B2 (en) | 2008-08-04 | 2014-06-17 | Tabula, Inc. | Trigger circuits and event counters for an IC |
US8760194B2 (en) | 2005-07-15 | 2014-06-24 | Tabula, Inc. | Runtime loading of configuration data in a configurable IC |
US8797062B2 (en) | 2004-11-08 | 2014-08-05 | Tabula, Inc. | Configurable IC's with large carry chains |
US8935640B2 (en) | 2007-06-27 | 2015-01-13 | Tabula, Inc. | Transport network |
US9154137B2 (en) | 2013-07-04 | 2015-10-06 | Altera Corporation | Non-intrusive monitoring and control of integrated circuits |
US9583190B2 (en) | 2011-11-11 | 2017-02-28 | Altera Corporation | Content addressable memory in integrated circuit |
CN112948324A (en) * | 2021-04-16 | 2021-06-11 | 山东高云半导体科技有限公司 | Memory mapping processing method and device and FPGA chip |
Citations (164)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB218220A (en) | 1923-10-31 | 1924-07-03 | Minimax G.M.B.H. | |
US3106698A (en) * | 1958-04-25 | 1963-10-08 | Bell Telephone Labor Inc | Parallel data processing apparatus |
US3287702A (en) * | 1962-12-04 | 1966-11-22 | Westinghouse Electric Corp | Computer control |
US3287703A (en) * | 1962-12-04 | 1966-11-22 | Westinghouse Electric Corp | Computer |
US3473160A (en) * | 1966-10-10 | 1969-10-14 | Stanford Research Inst | Electronically controlled microelectronic cellular logic array |
US3810577A (en) * | 1971-11-25 | 1974-05-14 | Ibm | Error testing and error localization in a modular data processing system |
US3928730A (en) * | 1974-07-01 | 1975-12-23 | Philips Corp | Matrix module and switching network |
US3955180A (en) * | 1974-01-02 | 1976-05-04 | Honeywell Information Systems Inc. | Table driven emulation system |
GB1444084A (en) | 1972-06-21 | 1976-07-28 | Honeywell Inf Systems | Generalized logic device |
US4020469A (en) * | 1975-04-09 | 1977-04-26 | Frank Manning | Programmable arrays |
US4032899A (en) * | 1975-05-05 | 1977-06-28 | International Business Machines Corporation | Apparatus and method for switching of data |
US4306286A (en) * | 1979-06-29 | 1981-12-15 | International Business Machines Corporation | Logic simulation machine |
US4315315A (en) * | 1971-03-09 | 1982-02-09 | The Johns Hopkins University | Graphical automatic programming |
US4357678A (en) * | 1979-12-26 | 1982-11-02 | International Business Machines Corporation | Programmable sequential logic array mechanism |
US4386403A (en) * | 1979-12-31 | 1983-05-31 | International Business Machines Corp. | System and method for LSI circuit analysis |
US4404635A (en) * | 1981-03-27 | 1983-09-13 | International Business Machines Corporation | Programmable integrated circuit and method of testing the circuit before it is programmed |
US4459694A (en) * | 1980-12-23 | 1984-07-10 | Fujitsu Limited | Field programmable device with circuitry for detecting poor insulation between adjacent word lines |
US4488354A (en) * | 1981-11-16 | 1984-12-18 | Ncr Corporation | Method for simulating and testing an integrated circuit chip |
US4503386A (en) * | 1982-04-20 | 1985-03-05 | International Business Machines Corporation | Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks |
US4510602A (en) * | 1981-06-24 | 1985-04-09 | Fordahl S.A.R.L. | Programmable logic apparatus for entering, processing and transmitting data |
US4524240A (en) * | 1983-08-17 | 1985-06-18 | Lucasfilm Ltd. | Universal circuit prototyping board |
US4525789A (en) * | 1982-07-16 | 1985-06-25 | At&T Bell Laboratories | Programmable network tester with data formatter |
US4527249A (en) * | 1982-10-22 | 1985-07-02 | Control Data Corporation | Simulator system for logic design validation |
US4527115A (en) * | 1982-12-22 | 1985-07-02 | Raytheon Company | Configurable logic gate array |
US4539564A (en) * | 1982-08-04 | 1985-09-03 | Smithson G Ronald | Electronically controlled interconnection system |
US4541071A (en) * | 1982-07-16 | 1985-09-10 | Nec Corporation | Dynamic gate array whereby an assembly of gates is simulated by logic operations on variables selected according to the gates |
US4577276A (en) * | 1983-09-12 | 1986-03-18 | At&T Bell Laboratories | Placement of components on circuit substrates |
US4578761A (en) * | 1983-03-25 | 1986-03-25 | At&T Bell Laboratories | Separating an equivalent circuit into components to detect terminating networks |
US4583169A (en) * | 1983-04-29 | 1986-04-15 | The Boeing Company | Method for emulating a Boolean network system |
US4587625A (en) * | 1983-07-05 | 1986-05-06 | Motorola Inc. | Processor for simulating digital structures |
US4593363A (en) * | 1983-08-12 | 1986-06-03 | International Business Machines Corporation | Simultaneous placement and wiring for VLSI chips |
US4600846A (en) * | 1983-10-06 | 1986-07-15 | Sanders Associates, Inc. | Universal logic circuit modules |
US4612618A (en) * | 1983-06-10 | 1986-09-16 | Rca Corporation | Hierarchical, computerized design of integrated circuits |
US4613940A (en) * | 1982-11-09 | 1986-09-23 | International Microelectronic Products | Method and structure for use in designing and building electronic systems in integrated circuits |
US4621339A (en) * | 1983-06-13 | 1986-11-04 | Duke University | SIMD machine using cube connected cycles network architecture for vector processing |
US4642487A (en) * | 1984-09-26 | 1987-02-10 | Xilinx, Inc. | Special interconnect for configurable logic array |
US4656580A (en) * | 1982-06-11 | 1987-04-07 | International Business Machines Corporation | Logic simulation machine |
US4656592A (en) * | 1983-10-14 | 1987-04-07 | U.S. Philips Corporation | Very large scale integrated circuit subdivided into isochronous regions, method for the machine-aided design of such a circuit, and method for the machine-aided testing of such a circuit |
EP0217291A2 (en) | 1985-09-27 | 1987-04-08 | Hitachi, Ltd. | Circuit translator |
US4674089A (en) * | 1985-04-16 | 1987-06-16 | Intel Corporation | In-circuit emulator |
US4675832A (en) * | 1983-10-13 | 1987-06-23 | Cirrus Computers Ltd. | Visual display logic simulation system |
US4695968A (en) * | 1983-11-03 | 1987-09-22 | Prime Computer, Inc. | Digital system simulation method and apparatus having improved sampling |
US4695950A (en) * | 1984-09-17 | 1987-09-22 | International Business Machines Corporation | Fast two-level dynamic address translation method and means |
US4695999A (en) * | 1984-06-27 | 1987-09-22 | International Business Machines Corporation | Cross-point switch of multiple autonomous planes |
US4695740A (en) * | 1984-09-26 | 1987-09-22 | Xilinx, Inc. | Bidirectional buffer amplifier |
US4697241A (en) * | 1985-03-01 | 1987-09-29 | Simulog, Inc. | Hardware logic simulator |
US4700187A (en) * | 1985-12-02 | 1987-10-13 | Concurrent Logic, Inc. | Programmable, asynchronous logic cell and array |
US4706216A (en) * | 1985-02-27 | 1987-11-10 | Xilinx, Inc. | Configurable logic element |
US4713557A (en) * | 1984-09-26 | 1987-12-15 | Xilinx, Inc. | Bidirectional buffer amplifier |
US4722084A (en) * | 1985-10-02 | 1988-01-26 | Itt Corporation | Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits |
US4725835A (en) * | 1985-09-13 | 1988-02-16 | T-Bar Incorporated | Time multiplexed bus matrix switching system |
US4736338A (en) * | 1986-10-07 | 1988-04-05 | Silicon Solutions Corporation | Programmable look up system |
US4740919A (en) * | 1985-06-04 | 1988-04-26 | Texas Instruments Incorporated | Electrically programmable logic array |
US4744084A (en) * | 1986-02-27 | 1988-05-10 | Mentor Graphics Corporation | Hardware modeling system and method for simulating portions of electrical circuits |
US4747102A (en) * | 1985-03-30 | 1988-05-24 | Nec Corporation | Method of controlling a logical simulation at a high speed |
US4752887A (en) * | 1985-03-01 | 1988-06-21 | Nec Corporation | Routing method for use in wiring design |
US4758745A (en) * | 1986-09-19 | 1988-07-19 | Actel Corporation | User programmable integrated circuit interconnect architecture and test method |
US4761768A (en) * | 1985-03-04 | 1988-08-02 | Lattice Semiconductor Corporation | Programmable logic device |
US4766569A (en) * | 1985-03-04 | 1988-08-23 | Lattice Semiconductor Corporation | Programmable logic array |
US4768196A (en) * | 1986-10-28 | 1988-08-30 | Silc Technologies, Inc. | Programmable logic array |
US4769817A (en) * | 1986-01-31 | 1988-09-06 | Zycad Corporation | Concurrent fault simulation for logic designs |
US4777606A (en) * | 1986-06-05 | 1988-10-11 | Northern Telecom Limited | Method for deriving an interconnection route between elements in an interconnection medium |
US4782440A (en) * | 1984-08-03 | 1988-11-01 | Nec Corporation | Logic simulator using small capacity memories for storing logic states, connection patterns, and logic functions |
US4782461A (en) * | 1984-06-21 | 1988-11-01 | Step Engineering | Logical grouping of facilities within a computer development system |
US4787061A (en) * | 1986-06-25 | 1988-11-22 | Ikos Systems, Inc. | Dual delay mode pipelined logic simulator |
US4787062A (en) * | 1986-06-26 | 1988-11-22 | Ikos Systems, Inc. | Glitch detection by forcing the output of a simulated logic device to an undefined state |
US4786904A (en) * | 1986-12-15 | 1988-11-22 | Zoran Corporation | Electronically programmable gate array having programmable interconnect lines |
US4791602A (en) * | 1983-04-14 | 1988-12-13 | Control Data Corporation | Soft programmable logic array |
US4811214A (en) * | 1986-11-14 | 1989-03-07 | Princeton University | Multinode reconfigurable pipeline computer |
US4815003A (en) * | 1987-06-19 | 1989-03-21 | General Electric Company | Structured design method for high density standard cell and macrocell layout of VLSI chips |
US4819150A (en) * | 1985-04-05 | 1989-04-04 | Unisys Corporation | Array for simulating computer functions for large computer systems |
US4823276A (en) * | 1986-03-20 | 1989-04-18 | Kabushiki Kaisha Toshiba | Computer-aided automatic wiring method for semiconductor integrated circuit device |
US4827427A (en) * | 1987-03-05 | 1989-05-02 | Hyduke Stanley M | Instantaneous incremental compiler for producing logic circuit designs |
US4829202A (en) * | 1986-09-04 | 1989-05-09 | Pilkington Micro-Electronics Limited | Semiconductor integrated bipolar switching circuit for controlling passage of signals |
US4835705A (en) * | 1986-02-17 | 1989-05-30 | Mitsubishi Denki Kabushiki Kaisha | Interconnection area decision processor |
US4845633A (en) * | 1985-12-02 | 1989-07-04 | Apple Computer Inc. | System for programming graphically a programmable, asynchronous logic cell and array |
US4849904A (en) * | 1987-06-19 | 1989-07-18 | International Business Machines Corporation | Macro structural arrangement and method for generating macros for VLSI semiconductor circuit devices |
US4849928A (en) * | 1987-01-28 | 1989-07-18 | Hauck Lane T | Logic array programmer |
US4855669A (en) * | 1987-10-07 | 1989-08-08 | Xilinx, Inc. | System for scan testing of logic circuit networks |
US4854039A (en) * | 1988-05-04 | 1989-08-08 | The Technology Congress, Ltd. | Prototype circuit board and method of testing |
US4862347A (en) * | 1986-04-22 | 1989-08-29 | International Business Machine Corporation | System for simulating memory arrays in a logic simulation machine |
US4864165A (en) * | 1985-03-22 | 1989-09-05 | Advanced Micro Devices, Inc. | ECL programmable logic array with direct testing means for verification of programmed state |
US4868419A (en) * | 1985-10-23 | 1989-09-19 | Pilkington Micro-Electronics Limited | Gated transmission circuit (on-chip) |
US4870302A (en) * | 1984-03-12 | 1989-09-26 | Xilinx, Inc. | Configurable electrical circuit having configurable logic elements and configurable interconnects |
US4876466A (en) * | 1987-11-20 | 1989-10-24 | Mitsubishi Denki Kabushiki Kaisha | Programmable logic array having a changeable logic structure |
US4879646A (en) * | 1986-04-18 | 1989-11-07 | Nec Corporation | Data processing system with a pipelined structure for editing trace memory contents and tracing operations during system debugging |
US4882690A (en) * | 1985-09-26 | 1989-11-21 | Hitachi, Ltd. | Incremental logic synthesis method |
GB2180382B (en) | 1985-09-11 | 1989-11-22 | Pilkington Micro Electronics | Semi-conductor integrated circuits/systems |
US4899273A (en) * | 1985-12-11 | 1990-02-06 | Hitachi, Ltd. | Circuit simulation method with clock event suppression for debugging LSI circuits |
US4901260A (en) * | 1987-10-28 | 1990-02-13 | American Telephone And Telegraph Company At&T Bell Laboratories | Bounded lag distributed discrete event simulation method and apparatus |
US4901259A (en) * | 1988-08-15 | 1990-02-13 | Lsi Logic Corporation | Asic emulator |
US4908772A (en) * | 1987-03-30 | 1990-03-13 | Bell Telephone Laboratories | Integrated circuits with component placement by rectilinear partitioning |
US4914612A (en) * | 1988-03-31 | 1990-04-03 | International Business Machines Corporation | Massively distributed simulation engine |
US4918440A (en) * | 1986-11-07 | 1990-04-17 | Furtek Frederick C | Programmable logic cell and array |
US4918594A (en) * | 1986-02-07 | 1990-04-17 | Hitachi, Ltd. | Method and system for logical simulation of information processing system including logic circuit model and logic function model |
US4922432A (en) * | 1988-01-13 | 1990-05-01 | International Chip Corporation | Knowledge based method and apparatus for designing integrated circuits using functional specifications |
US4924429A (en) * | 1987-02-25 | 1990-05-08 | Nec Corporation | Hardware logic simulator |
US4931946A (en) * | 1988-03-10 | 1990-06-05 | Cirrus Logic, Inc. | Programmable tiles |
US4937827A (en) * | 1985-03-01 | 1990-06-26 | Mentor Graphics Corporation | Circuit verification accessory |
US4942536A (en) | 1985-04-19 | 1990-07-17 | Hitachi, Ltd. | Method of automatic circuit translation |
US4942615A (en) | 1987-02-20 | 1990-07-17 | Fujitsu Limited | Gate processor arrangement for simulation processor system |
US4945503A (en) | 1986-10-21 | 1990-07-31 | Nec Corporation | Hardware simulator capable of reducing an amount of information |
US4949275A (en) | 1984-07-13 | 1990-08-14 | Yamaha Corporation | Semiconductor integrated circuit device made by a standard-cell system and method for manufacture of same |
US4951220A (en) | 1987-09-22 | 1990-08-21 | Siemens Aktiengesellschaft | Method and apparatus for manufacturing a test-compatible, largely defect-tolerant configuration of redundantly implemented, systolic VLSI systems |
US4958324A (en) | 1987-11-24 | 1990-09-18 | Sgs-Thomson Microelectronics Sa | Method for the testing of electrically programmable memory cells, and corresponding integrated circuit |
US4965739A (en) | 1987-03-26 | 1990-10-23 | Vlsi Technology, Inc. | Machine process for routing interconnections from one module to another module and for positioning said two modules after said modules are interconnected |
US4972334A (en) | 1987-03-13 | 1990-11-20 | Hitachi, Ltd. | Automatic generation method of a simulation program for numerically solving a partial differential equation according to a boundary-fitted method |
US4972372A (en) | 1987-07-21 | 1990-11-20 | Fujitsu Limited | Programmable device and method of testing programmable device |
US5003487A (en) | 1988-06-28 | 1991-03-26 | International Business Machines Corporation | Method and apparatus for performing timing correction transformations on a technology-independent logic model during logic synthesis |
US5023775A (en) | 1985-02-14 | 1991-06-11 | Intel Corporation | Software programmable logic array utilizing "and" and "or" gates |
US5031129A (en) | 1989-05-12 | 1991-07-09 | Alcatel Na Network Systems Corp. | Parallel pseudo-random generator for emulating a serial pseudo-random generator and method for carrying out same |
US5036473A (en) | 1988-10-05 | 1991-07-30 | Mentor Graphics Corporation | Method of using electronically reconfigurable logic circuits |
US5041986A (en) | 1988-09-30 | 1991-08-20 | Nec Corporation | Logic synthesis system comprising a memory for a reduced number of translation rules |
US5046017A (en) | 1987-12-23 | 1991-09-03 | Hitachi, Ltd. | Wiring design for semiconductor integrated circuit |
US5051938A (en) | 1989-06-23 | 1991-09-24 | Hyduke Stanley M | Simulation of selected logic circuit designs |
US5053980A (en) | 1988-03-10 | 1991-10-01 | Matsushita Electric Industrial Co., Ltd. | Method and apparatus for logic simulation |
US5068812A (en) | 1989-07-18 | 1991-11-26 | Vlsi Technology, Inc. | Event-controlled LCC stimulation |
US5081602A (en) | 1989-11-07 | 1992-01-14 | Amp Incorporated | Computer simulator for electrical connectors |
US5083083A (en) | 1986-09-19 | 1992-01-21 | Actel Corporation | Testability architecture and techniques for programmable interconnect architecture |
US5084824A (en) | 1990-03-29 | 1992-01-28 | National Semiconductor Corporation | Simulation model generation from a physical data base of a combinatorial circuit |
US5093920A (en) | 1987-06-25 | 1992-03-03 | At&T Bell Laboratories | Programmable processing elements interconnected by a communication network including field operation unit for performing field operations |
US5109353A (en) | 1988-12-02 | 1992-04-28 | Quickturn Systems, Incorporated | Apparatus for emulation of electronic hardware system |
US5114353A (en) | 1991-03-01 | 1992-05-19 | Quickturn Systems, Incorporated | Multiple connector arrangement for printed circuit board interconnection |
US5126966A (en) | 1986-06-25 | 1992-06-30 | Ikos Systems, Inc. | High speed logic simulation system with stimulus engine using independent event channels selectively driven by independent stimulus programs |
US5128871A (en) | 1990-03-07 | 1992-07-07 | Advanced Micro Devices, Inc. | Apparatus and method for allocation of resoures in programmable logic devices |
US5140526A (en) | 1989-01-06 | 1992-08-18 | Minc Incorporated | Partitioning of Boolean logic equations into physical logic devices |
US5172011A (en) | 1989-06-30 | 1992-12-15 | Digital Equipment Corporation | Latch circuit and method with complementary clocking and level sensitive scan capability |
US5224055A (en) | 1989-02-10 | 1993-06-29 | Plessey Semiconductors Limited | Machine for circuit design |
US5224056A (en) | 1991-10-30 | 1993-06-29 | Xilinx, Inc. | Logic placement using positionally asymmetrical partitioning algorithm |
US5231588A (en) | 1989-08-15 | 1993-07-27 | Advanced Micro Devices, Inc. | Programmable gate array with logic cells having symmetrical input/output structures |
US5231589A (en) | 1989-12-11 | 1993-07-27 | Hitachi, Ltd. | Input/output pin assignment method |
US5233539A (en) | 1989-08-15 | 1993-08-03 | Advanced Micro Devices, Inc. | Programmable gate array with improved interconnect structure, input/output structure and configurable logic block |
US5253363A (en) | 1988-03-15 | 1993-10-12 | Edward Hyman | Method and apparatus for compiling and implementing state-machine states and outputs for a universal cellular sequential local array |
US5259006A (en) | 1990-04-18 | 1993-11-02 | Quickturn Systems, Incorporated | Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like |
US5276854A (en) | 1990-08-17 | 1994-01-04 | Cray Research, Inc. | Method of multiple CPU logic simulation |
US5321828A (en) | 1991-06-07 | 1994-06-14 | Step Engineering | High speed microcomputer in-circuit emulator |
US5329471A (en) | 1987-06-02 | 1994-07-12 | Texas Instruments Incorporated | Emulation devices, systems and methods utilizing state machines |
US5329470A (en) | 1988-12-02 | 1994-07-12 | Quickturn Systems, Inc. | Reconfigurable hardware emulation system |
US5331571A (en) | 1992-07-22 | 1994-07-19 | Nec Electronics, Inc. | Testing and emulation of integrated circuits |
US5339262A (en) | 1992-07-10 | 1994-08-16 | Lsi Logic Corporation | Method and apparatus for interim, in-situ testing of an electronic system with an inchoate ASIC |
US5341483A (en) | 1987-12-22 | 1994-08-23 | Kendall Square Research Corporation | Dynamic hierarchial associative memory |
US5345580A (en) | 1990-11-29 | 1994-09-06 | Kabushiki Kaisha Toshiba | Microprocessor device and emulator device thereof |
US5352123A (en) | 1992-06-08 | 1994-10-04 | Quickturn Systems, Incorporated | Switching midplane and interconnection system for interconnecting large numbers of signals |
US5377123A (en) | 1992-06-08 | 1994-12-27 | Hyman; Edward | Programmable logic device |
US5386550A (en) | 1992-01-24 | 1995-01-31 | Fujitsu Limited | Pseudo-LSI device and debugging system incorporating same |
US5396498A (en) | 1990-12-07 | 1995-03-07 | Thomson Csf | Integrated circuit with peripheral test controller |
US5425036A (en) | 1992-09-18 | 1995-06-13 | Quickturn Design Systems, Inc. | Method and apparatus for debugging reconfigurable emulation systems |
US5437037A (en) | 1992-06-05 | 1995-07-25 | Mega Chips Corporation | Simulation using compiled function description language |
US5448496A (en) | 1988-10-05 | 1995-09-05 | Quickturn Design Systems, Inc. | Partial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logic emulation system |
US5448522A (en) | 1994-03-24 | 1995-09-05 | Quickturn Design Systems, Inc. | Multi-port memory emulation using tag registers |
US5452239A (en) | 1993-01-29 | 1995-09-19 | Quickturn Design Systems, Inc. | Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system |
US5475830A (en) | 1992-01-31 | 1995-12-12 | Quickturn Design Systems, Inc. | Structure and method for providing a reconfigurable emulation circuit without hold time violations |
US5475624A (en) | 1992-04-30 | 1995-12-12 | Schlumberger Technologies, Inc. | Test generation by environment emulation |
US5479355A (en) | 1993-09-14 | 1995-12-26 | Hyduke; Stanley M. | System and method for a closed loop operation of schematic designs with electrical hardware |
US5530958A (en) | 1992-08-07 | 1996-06-25 | Massachusetts Institute Of Technology | Cache memory system and method with multiple hashing functions and hash control storage |
US5544069A (en) | 1989-09-20 | 1996-08-06 | Aptix Corporation | Structure having different levels of programmable integrated circuits interconnected through bus lines for interconnecting electronic components |
US5546562A (en) | 1995-02-28 | 1996-08-13 | Patel; Chandresh | Method and apparatus to emulate VLSI circuits within a logic simulator |
US5551013A (en) | 1994-06-03 | 1996-08-27 | International Business Machines Corporation | Multiprocessor for hardware emulation |
US5572710A (en) | 1992-09-11 | 1996-11-05 | Kabushiki Kaisha Toshiba | High speed logic simulation system using time division emulation suitable for large scale logic circuits |
US5574388A (en) | 1995-10-13 | 1996-11-12 | Mentor Graphics Corporation | Emulation system having a scalable multi-level multi-stage programmable interconnect network |
US5596742A (en) | 1993-04-02 | 1997-01-21 | Massachusetts Institute Of Technology | Virtual interconnections for reconfigurable logic systems |
US5623664A (en) | 1994-07-25 | 1997-04-22 | Motorola, Inc. | Interactive memory organization system and method therefor |
US5649176A (en) | 1995-08-10 | 1997-07-15 | Virtual Machine Works, Inc. | Transition analysis and circuit resynthesis method and device for digital circuit modeling |
US5659716A (en) | 1994-11-23 | 1997-08-19 | Virtual Machine Works, Inc. | Pipe-lined static router and scheduler for configurable logic system performing simultaneous communications and computation |
-
1997
- 1997-06-25 US US08/883,025 patent/US5970240A/en not_active Expired - Lifetime
Patent Citations (175)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB218220A (en) | 1923-10-31 | 1924-07-03 | Minimax G.M.B.H. | |
US3106698A (en) * | 1958-04-25 | 1963-10-08 | Bell Telephone Labor Inc | Parallel data processing apparatus |
US3287702A (en) * | 1962-12-04 | 1966-11-22 | Westinghouse Electric Corp | Computer control |
US3287703A (en) * | 1962-12-04 | 1966-11-22 | Westinghouse Electric Corp | Computer |
US3473160A (en) * | 1966-10-10 | 1969-10-14 | Stanford Research Inst | Electronically controlled microelectronic cellular logic array |
US4315315A (en) * | 1971-03-09 | 1982-02-09 | The Johns Hopkins University | Graphical automatic programming |
US3810577A (en) * | 1971-11-25 | 1974-05-14 | Ibm | Error testing and error localization in a modular data processing system |
GB1444084A (en) | 1972-06-21 | 1976-07-28 | Honeywell Inf Systems | Generalized logic device |
US3955180A (en) * | 1974-01-02 | 1976-05-04 | Honeywell Information Systems Inc. | Table driven emulation system |
US3928730A (en) * | 1974-07-01 | 1975-12-23 | Philips Corp | Matrix module and switching network |
US4020469A (en) * | 1975-04-09 | 1977-04-26 | Frank Manning | Programmable arrays |
US4032899A (en) * | 1975-05-05 | 1977-06-28 | International Business Machines Corporation | Apparatus and method for switching of data |
US4306286A (en) * | 1979-06-29 | 1981-12-15 | International Business Machines Corporation | Logic simulation machine |
US4357678A (en) * | 1979-12-26 | 1982-11-02 | International Business Machines Corporation | Programmable sequential logic array mechanism |
US4386403A (en) * | 1979-12-31 | 1983-05-31 | International Business Machines Corp. | System and method for LSI circuit analysis |
US4459694A (en) * | 1980-12-23 | 1984-07-10 | Fujitsu Limited | Field programmable device with circuitry for detecting poor insulation between adjacent word lines |
US4404635A (en) * | 1981-03-27 | 1983-09-13 | International Business Machines Corporation | Programmable integrated circuit and method of testing the circuit before it is programmed |
US4510602A (en) * | 1981-06-24 | 1985-04-09 | Fordahl S.A.R.L. | Programmable logic apparatus for entering, processing and transmitting data |
US4488354A (en) * | 1981-11-16 | 1984-12-18 | Ncr Corporation | Method for simulating and testing an integrated circuit chip |
US4503386A (en) * | 1982-04-20 | 1985-03-05 | International Business Machines Corporation | Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks |
US4656580A (en) * | 1982-06-11 | 1987-04-07 | International Business Machines Corporation | Logic simulation machine |
US4525789A (en) * | 1982-07-16 | 1985-06-25 | At&T Bell Laboratories | Programmable network tester with data formatter |
US4541071A (en) * | 1982-07-16 | 1985-09-10 | Nec Corporation | Dynamic gate array whereby an assembly of gates is simulated by logic operations on variables selected according to the gates |
US4539564A (en) * | 1982-08-04 | 1985-09-03 | Smithson G Ronald | Electronically controlled interconnection system |
US4527249A (en) * | 1982-10-22 | 1985-07-02 | Control Data Corporation | Simulator system for logic design validation |
US4613940A (en) * | 1982-11-09 | 1986-09-23 | International Microelectronic Products | Method and structure for use in designing and building electronic systems in integrated circuits |
US4527115A (en) * | 1982-12-22 | 1985-07-02 | Raytheon Company | Configurable logic gate array |
US4578761A (en) * | 1983-03-25 | 1986-03-25 | At&T Bell Laboratories | Separating an equivalent circuit into components to detect terminating networks |
US4791602A (en) * | 1983-04-14 | 1988-12-13 | Control Data Corporation | Soft programmable logic array |
US4583169A (en) * | 1983-04-29 | 1986-04-15 | The Boeing Company | Method for emulating a Boolean network system |
US4612618A (en) * | 1983-06-10 | 1986-09-16 | Rca Corporation | Hierarchical, computerized design of integrated circuits |
US4621339A (en) * | 1983-06-13 | 1986-11-04 | Duke University | SIMD machine using cube connected cycles network architecture for vector processing |
US4587625A (en) * | 1983-07-05 | 1986-05-06 | Motorola Inc. | Processor for simulating digital structures |
US4593363A (en) * | 1983-08-12 | 1986-06-03 | International Business Machines Corporation | Simultaneous placement and wiring for VLSI chips |
US4524240A (en) * | 1983-08-17 | 1985-06-18 | Lucasfilm Ltd. | Universal circuit prototyping board |
US4577276A (en) * | 1983-09-12 | 1986-03-18 | At&T Bell Laboratories | Placement of components on circuit substrates |
US4600846A (en) * | 1983-10-06 | 1986-07-15 | Sanders Associates, Inc. | Universal logic circuit modules |
US4675832A (en) * | 1983-10-13 | 1987-06-23 | Cirrus Computers Ltd. | Visual display logic simulation system |
US4656592A (en) * | 1983-10-14 | 1987-04-07 | U.S. Philips Corporation | Very large scale integrated circuit subdivided into isochronous regions, method for the machine-aided design of such a circuit, and method for the machine-aided testing of such a circuit |
US4725971A (en) * | 1983-11-03 | 1988-02-16 | Prime Computer, Inc. | Digital system simulation method and apparatus |
US4695968A (en) * | 1983-11-03 | 1987-09-22 | Prime Computer, Inc. | Digital system simulation method and apparatus having improved sampling |
US4870302A (en) * | 1984-03-12 | 1989-09-26 | Xilinx, Inc. | Configurable electrical circuit having configurable logic elements and configurable interconnects |
US4782461A (en) * | 1984-06-21 | 1988-11-01 | Step Engineering | Logical grouping of facilities within a computer development system |
US4695999A (en) * | 1984-06-27 | 1987-09-22 | International Business Machines Corporation | Cross-point switch of multiple autonomous planes |
US4949275A (en) | 1984-07-13 | 1990-08-14 | Yamaha Corporation | Semiconductor integrated circuit device made by a standard-cell system and method for manufacture of same |
US4782440A (en) * | 1984-08-03 | 1988-11-01 | Nec Corporation | Logic simulator using small capacity memories for storing logic states, connection patterns, and logic functions |
US4695950A (en) * | 1984-09-17 | 1987-09-22 | International Business Machines Corporation | Fast two-level dynamic address translation method and means |
US4695740A (en) * | 1984-09-26 | 1987-09-22 | Xilinx, Inc. | Bidirectional buffer amplifier |
US4713557A (en) * | 1984-09-26 | 1987-12-15 | Xilinx, Inc. | Bidirectional buffer amplifier |
US4642487A (en) * | 1984-09-26 | 1987-02-10 | Xilinx, Inc. | Special interconnect for configurable logic array |
US5023775A (en) | 1985-02-14 | 1991-06-11 | Intel Corporation | Software programmable logic array utilizing "and" and "or" gates |
US4706216A (en) * | 1985-02-27 | 1987-11-10 | Xilinx, Inc. | Configurable logic element |
US4758985A (en) * | 1985-02-27 | 1988-07-19 | Xilinx, Inc. | Microprocessor oriented configurable logic element |
US4697241A (en) * | 1985-03-01 | 1987-09-29 | Simulog, Inc. | Hardware logic simulator |
US4937827A (en) * | 1985-03-01 | 1990-06-26 | Mentor Graphics Corporation | Circuit verification accessory |
US4752887A (en) * | 1985-03-01 | 1988-06-21 | Nec Corporation | Routing method for use in wiring design |
US4766569A (en) * | 1985-03-04 | 1988-08-23 | Lattice Semiconductor Corporation | Programmable logic array |
US4761768A (en) * | 1985-03-04 | 1988-08-02 | Lattice Semiconductor Corporation | Programmable logic device |
US4864165A (en) * | 1985-03-22 | 1989-09-05 | Advanced Micro Devices, Inc. | ECL programmable logic array with direct testing means for verification of programmed state |
US4747102A (en) * | 1985-03-30 | 1988-05-24 | Nec Corporation | Method of controlling a logical simulation at a high speed |
US4819150A (en) * | 1985-04-05 | 1989-04-04 | Unisys Corporation | Array for simulating computer functions for large computer systems |
US4674089A (en) * | 1985-04-16 | 1987-06-16 | Intel Corporation | In-circuit emulator |
US4942536A (en) | 1985-04-19 | 1990-07-17 | Hitachi, Ltd. | Method of automatic circuit translation |
US4740919A (en) * | 1985-06-04 | 1988-04-26 | Texas Instruments Incorporated | Electrically programmable logic array |
GB2180382B (en) | 1985-09-11 | 1989-11-22 | Pilkington Micro Electronics | Semi-conductor integrated circuits/systems |
US4935734A (en) * | 1985-09-11 | 1990-06-19 | Pilkington Micro-Electronics Limited | Semi-conductor integrated circuits/systems |
US4725835A (en) * | 1985-09-13 | 1988-02-16 | T-Bar Incorporated | Time multiplexed bus matrix switching system |
US4882690A (en) * | 1985-09-26 | 1989-11-21 | Hitachi, Ltd. | Incremental logic synthesis method |
EP0217291A2 (en) | 1985-09-27 | 1987-04-08 | Hitachi, Ltd. | Circuit translator |
US4803636A (en) * | 1985-09-27 | 1989-02-07 | Hitachi Ltd. | Circuit translator |
US4722084A (en) * | 1985-10-02 | 1988-01-26 | Itt Corporation | Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits |
US4868419A (en) * | 1985-10-23 | 1989-09-19 | Pilkington Micro-Electronics Limited | Gated transmission circuit (on-chip) |
US4845633A (en) * | 1985-12-02 | 1989-07-04 | Apple Computer Inc. | System for programming graphically a programmable, asynchronous logic cell and array |
US4700187A (en) * | 1985-12-02 | 1987-10-13 | Concurrent Logic, Inc. | Programmable, asynchronous logic cell and array |
US4899273A (en) * | 1985-12-11 | 1990-02-06 | Hitachi, Ltd. | Circuit simulation method with clock event suppression for debugging LSI circuits |
US4769817A (en) * | 1986-01-31 | 1988-09-06 | Zycad Corporation | Concurrent fault simulation for logic designs |
US4918594A (en) * | 1986-02-07 | 1990-04-17 | Hitachi, Ltd. | Method and system for logical simulation of information processing system including logic circuit model and logic function model |
US4835705A (en) * | 1986-02-17 | 1989-05-30 | Mitsubishi Denki Kabushiki Kaisha | Interconnection area decision processor |
US4744084A (en) * | 1986-02-27 | 1988-05-10 | Mentor Graphics Corporation | Hardware modeling system and method for simulating portions of electrical circuits |
US4823276A (en) * | 1986-03-20 | 1989-04-18 | Kabushiki Kaisha Toshiba | Computer-aided automatic wiring method for semiconductor integrated circuit device |
US4879646A (en) * | 1986-04-18 | 1989-11-07 | Nec Corporation | Data processing system with a pipelined structure for editing trace memory contents and tracing operations during system debugging |
US4862347A (en) * | 1986-04-22 | 1989-08-29 | International Business Machine Corporation | System for simulating memory arrays in a logic simulation machine |
US4777606A (en) * | 1986-06-05 | 1988-10-11 | Northern Telecom Limited | Method for deriving an interconnection route between elements in an interconnection medium |
US5126966A (en) | 1986-06-25 | 1992-06-30 | Ikos Systems, Inc. | High speed logic simulation system with stimulus engine using independent event channels selectively driven by independent stimulus programs |
US4787061A (en) * | 1986-06-25 | 1988-11-22 | Ikos Systems, Inc. | Dual delay mode pipelined logic simulator |
US4787062A (en) * | 1986-06-26 | 1988-11-22 | Ikos Systems, Inc. | Glitch detection by forcing the output of a simulated logic device to an undefined state |
US4829202A (en) * | 1986-09-04 | 1989-05-09 | Pilkington Micro-Electronics Limited | Semiconductor integrated bipolar switching circuit for controlling passage of signals |
US4758745A (en) * | 1986-09-19 | 1988-07-19 | Actel Corporation | User programmable integrated circuit interconnect architecture and test method |
US4873459A (en) * | 1986-09-19 | 1989-10-10 | Actel Corporation | Programmable interconnect architecture |
US4758745B1 (en) * | 1986-09-19 | 1994-11-15 | Actel Corp | User programmable integrated circuit interconnect architecture and test method |
US4873459B1 (en) * | 1986-09-19 | 1995-01-10 | Actel Corp | Programmable interconnect architecture |
US5083083A (en) | 1986-09-19 | 1992-01-21 | Actel Corporation | Testability architecture and techniques for programmable interconnect architecture |
US4736338A (en) * | 1986-10-07 | 1988-04-05 | Silicon Solutions Corporation | Programmable look up system |
US4945503A (en) | 1986-10-21 | 1990-07-31 | Nec Corporation | Hardware simulator capable of reducing an amount of information |
US4768196A (en) * | 1986-10-28 | 1988-08-30 | Silc Technologies, Inc. | Programmable logic array |
US4918440A (en) * | 1986-11-07 | 1990-04-17 | Furtek Frederick C | Programmable logic cell and array |
US4811214A (en) * | 1986-11-14 | 1989-03-07 | Princeton University | Multinode reconfigurable pipeline computer |
US4786904A (en) * | 1986-12-15 | 1988-11-22 | Zoran Corporation | Electronically programmable gate array having programmable interconnect lines |
US4849928A (en) * | 1987-01-28 | 1989-07-18 | Hauck Lane T | Logic array programmer |
US4942615A (en) | 1987-02-20 | 1990-07-17 | Fujitsu Limited | Gate processor arrangement for simulation processor system |
US4924429A (en) * | 1987-02-25 | 1990-05-08 | Nec Corporation | Hardware logic simulator |
US4827427A (en) * | 1987-03-05 | 1989-05-02 | Hyduke Stanley M | Instantaneous incremental compiler for producing logic circuit designs |
US4972334A (en) | 1987-03-13 | 1990-11-20 | Hitachi, Ltd. | Automatic generation method of a simulation program for numerically solving a partial differential equation according to a boundary-fitted method |
US4965739A (en) | 1987-03-26 | 1990-10-23 | Vlsi Technology, Inc. | Machine process for routing interconnections from one module to another module and for positioning said two modules after said modules are interconnected |
US4908772A (en) * | 1987-03-30 | 1990-03-13 | Bell Telephone Laboratories | Integrated circuits with component placement by rectilinear partitioning |
US5329471A (en) | 1987-06-02 | 1994-07-12 | Texas Instruments Incorporated | Emulation devices, systems and methods utilizing state machines |
US4815003A (en) * | 1987-06-19 | 1989-03-21 | General Electric Company | Structured design method for high density standard cell and macrocell layout of VLSI chips |
US4849904A (en) * | 1987-06-19 | 1989-07-18 | International Business Machines Corporation | Macro structural arrangement and method for generating macros for VLSI semiconductor circuit devices |
US5093920A (en) | 1987-06-25 | 1992-03-03 | At&T Bell Laboratories | Programmable processing elements interconnected by a communication network including field operation unit for performing field operations |
US4972372A (en) | 1987-07-21 | 1990-11-20 | Fujitsu Limited | Programmable device and method of testing programmable device |
US4951220A (en) | 1987-09-22 | 1990-08-21 | Siemens Aktiengesellschaft | Method and apparatus for manufacturing a test-compatible, largely defect-tolerant configuration of redundantly implemented, systolic VLSI systems |
US4855669A (en) * | 1987-10-07 | 1989-08-08 | Xilinx, Inc. | System for scan testing of logic circuit networks |
US4901260A (en) * | 1987-10-28 | 1990-02-13 | American Telephone And Telegraph Company At&T Bell Laboratories | Bounded lag distributed discrete event simulation method and apparatus |
US4876466A (en) * | 1987-11-20 | 1989-10-24 | Mitsubishi Denki Kabushiki Kaisha | Programmable logic array having a changeable logic structure |
US4958324A (en) | 1987-11-24 | 1990-09-18 | Sgs-Thomson Microelectronics Sa | Method for the testing of electrically programmable memory cells, and corresponding integrated circuit |
US5341483A (en) | 1987-12-22 | 1994-08-23 | Kendall Square Research Corporation | Dynamic hierarchial associative memory |
US5046017A (en) | 1987-12-23 | 1991-09-03 | Hitachi, Ltd. | Wiring design for semiconductor integrated circuit |
US4922432A (en) * | 1988-01-13 | 1990-05-01 | International Chip Corporation | Knowledge based method and apparatus for designing integrated circuits using functional specifications |
US5053980A (en) | 1988-03-10 | 1991-10-01 | Matsushita Electric Industrial Co., Ltd. | Method and apparatus for logic simulation |
US4931946A (en) * | 1988-03-10 | 1990-06-05 | Cirrus Logic, Inc. | Programmable tiles |
US5253363A (en) | 1988-03-15 | 1993-10-12 | Edward Hyman | Method and apparatus for compiling and implementing state-machine states and outputs for a universal cellular sequential local array |
US4914612A (en) * | 1988-03-31 | 1990-04-03 | International Business Machines Corporation | Massively distributed simulation engine |
US4854039A (en) * | 1988-05-04 | 1989-08-08 | The Technology Congress, Ltd. | Prototype circuit board and method of testing |
US5003487A (en) | 1988-06-28 | 1991-03-26 | International Business Machines Corporation | Method and apparatus for performing timing correction transformations on a technology-independent logic model during logic synthesis |
US4901259A (en) * | 1988-08-15 | 1990-02-13 | Lsi Logic Corporation | Asic emulator |
US5041986A (en) | 1988-09-30 | 1991-08-20 | Nec Corporation | Logic synthesis system comprising a memory for a reduced number of translation rules |
US5612891A (en) | 1988-10-05 | 1997-03-18 | Quickturn Design Systems, Inc. | Hardware logic emulation system with memory capability |
US5036473A (en) | 1988-10-05 | 1991-07-30 | Mentor Graphics Corporation | Method of using electronically reconfigurable logic circuits |
US5452231A (en) | 1988-10-05 | 1995-09-19 | Quickturn Design Systems, Inc. | Hierarchically connected reconfigurable logic assembly |
US5448496A (en) | 1988-10-05 | 1995-09-05 | Quickturn Design Systems, Inc. | Partial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logic emulation system |
US5477475A (en) | 1988-12-02 | 1995-12-19 | Quickturn Design Systems, Inc. | Method for emulating a circuit design using an electrically reconfigurable hardware emulation apparatus |
US5109353A (en) | 1988-12-02 | 1992-04-28 | Quickturn Systems, Incorporated | Apparatus for emulation of electronic hardware system |
US5329470A (en) | 1988-12-02 | 1994-07-12 | Quickturn Systems, Inc. | Reconfigurable hardware emulation system |
US5140526A (en) | 1989-01-06 | 1992-08-18 | Minc Incorporated | Partitioning of Boolean logic equations into physical logic devices |
US5224055A (en) | 1989-02-10 | 1993-06-29 | Plessey Semiconductors Limited | Machine for circuit design |
US5031129A (en) | 1989-05-12 | 1991-07-09 | Alcatel Na Network Systems Corp. | Parallel pseudo-random generator for emulating a serial pseudo-random generator and method for carrying out same |
US5051938A (en) | 1989-06-23 | 1991-09-24 | Hyduke Stanley M | Simulation of selected logic circuit designs |
US5172011A (en) | 1989-06-30 | 1992-12-15 | Digital Equipment Corporation | Latch circuit and method with complementary clocking and level sensitive scan capability |
US5068812A (en) | 1989-07-18 | 1991-11-26 | Vlsi Technology, Inc. | Event-controlled LCC stimulation |
US5231588A (en) | 1989-08-15 | 1993-07-27 | Advanced Micro Devices, Inc. | Programmable gate array with logic cells having symmetrical input/output structures |
US5233539A (en) | 1989-08-15 | 1993-08-03 | Advanced Micro Devices, Inc. | Programmable gate array with improved interconnect structure, input/output structure and configurable logic block |
US5544069A (en) | 1989-09-20 | 1996-08-06 | Aptix Corporation | Structure having different levels of programmable integrated circuits interconnected through bus lines for interconnecting electronic components |
US5081602A (en) | 1989-11-07 | 1992-01-14 | Amp Incorporated | Computer simulator for electrical connectors |
US5231589A (en) | 1989-12-11 | 1993-07-27 | Hitachi, Ltd. | Input/output pin assignment method |
US5128871A (en) | 1990-03-07 | 1992-07-07 | Advanced Micro Devices, Inc. | Apparatus and method for allocation of resoures in programmable logic devices |
US5084824A (en) | 1990-03-29 | 1992-01-28 | National Semiconductor Corporation | Simulation model generation from a physical data base of a combinatorial circuit |
US5259006A (en) | 1990-04-18 | 1993-11-02 | Quickturn Systems, Incorporated | Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like |
US5276854A (en) | 1990-08-17 | 1994-01-04 | Cray Research, Inc. | Method of multiple CPU logic simulation |
US5345580A (en) | 1990-11-29 | 1994-09-06 | Kabushiki Kaisha Toshiba | Microprocessor device and emulator device thereof |
US5396498A (en) | 1990-12-07 | 1995-03-07 | Thomson Csf | Integrated circuit with peripheral test controller |
US5114353A (en) | 1991-03-01 | 1992-05-19 | Quickturn Systems, Incorporated | Multiple connector arrangement for printed circuit board interconnection |
US5321828A (en) | 1991-06-07 | 1994-06-14 | Step Engineering | High speed microcomputer in-circuit emulator |
US5224056A (en) | 1991-10-30 | 1993-06-29 | Xilinx, Inc. | Logic placement using positionally asymmetrical partitioning algorithm |
US5386550A (en) | 1992-01-24 | 1995-01-31 | Fujitsu Limited | Pseudo-LSI device and debugging system incorporating same |
US5475830A (en) | 1992-01-31 | 1995-12-12 | Quickturn Design Systems, Inc. | Structure and method for providing a reconfigurable emulation circuit without hold time violations |
US5475624A (en) | 1992-04-30 | 1995-12-12 | Schlumberger Technologies, Inc. | Test generation by environment emulation |
US5437037A (en) | 1992-06-05 | 1995-07-25 | Mega Chips Corporation | Simulation using compiled function description language |
US5352123A (en) | 1992-06-08 | 1994-10-04 | Quickturn Systems, Incorporated | Switching midplane and interconnection system for interconnecting large numbers of signals |
US5377123A (en) | 1992-06-08 | 1994-12-27 | Hyman; Edward | Programmable logic device |
US5339262A (en) | 1992-07-10 | 1994-08-16 | Lsi Logic Corporation | Method and apparatus for interim, in-situ testing of an electronic system with an inchoate ASIC |
US5331571A (en) | 1992-07-22 | 1994-07-19 | Nec Electronics, Inc. | Testing and emulation of integrated circuits |
US5530958A (en) | 1992-08-07 | 1996-06-25 | Massachusetts Institute Of Technology | Cache memory system and method with multiple hashing functions and hash control storage |
US5572710A (en) | 1992-09-11 | 1996-11-05 | Kabushiki Kaisha Toshiba | High speed logic simulation system using time division emulation suitable for large scale logic circuits |
US5425036A (en) | 1992-09-18 | 1995-06-13 | Quickturn Design Systems, Inc. | Method and apparatus for debugging reconfigurable emulation systems |
US5452239A (en) | 1993-01-29 | 1995-09-19 | Quickturn Design Systems, Inc. | Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system |
US5596742A (en) | 1993-04-02 | 1997-01-21 | Massachusetts Institute Of Technology | Virtual interconnections for reconfigurable logic systems |
US5479355A (en) | 1993-09-14 | 1995-12-26 | Hyduke; Stanley M. | System and method for a closed loop operation of schematic designs with electrical hardware |
US5563829A (en) | 1994-03-24 | 1996-10-08 | Quickturn Design Systems, Inc. | Multi-port memory emulation using tag registers |
US5448522A (en) | 1994-03-24 | 1995-09-05 | Quickturn Design Systems, Inc. | Multi-port memory emulation using tag registers |
US5551013A (en) | 1994-06-03 | 1996-08-27 | International Business Machines Corporation | Multiprocessor for hardware emulation |
US5623664A (en) | 1994-07-25 | 1997-04-22 | Motorola, Inc. | Interactive memory organization system and method therefor |
US5659716A (en) | 1994-11-23 | 1997-08-19 | Virtual Machine Works, Inc. | Pipe-lined static router and scheduler for configurable logic system performing simultaneous communications and computation |
US5546562A (en) | 1995-02-28 | 1996-08-13 | Patel; Chandresh | Method and apparatus to emulate VLSI circuits within a logic simulator |
US5649176A (en) | 1995-08-10 | 1997-07-15 | Virtual Machine Works, Inc. | Transition analysis and circuit resynthesis method and device for digital circuit modeling |
US5574388A (en) | 1995-10-13 | 1996-11-12 | Mentor Graphics Corporation | Emulation system having a scalable multi-level multi-stage programmable interconnect network |
Non-Patent Citations (199)
Title |
---|
"ERA60100 Electrically Reconfigurable Array-ERA," Brochure by Plessey Semiconductors, Apr. 1989. |
"Partitioning of PLA Logic," IBM TDM, vol. 28, No. 6, Nov. 1985, pp. 2332-2333. |
"Plus Logic FPGA2020 Field Programmable Gate Array" Brochure by Plus Logic, San Jose, CA, pp. 1-13. |
"The Homogenous Computational Medium; New Technology For Computation", Concurrent Logic Inc., Jan. 26, 1987. |
"The Programmable Gate Array Data Book", Xilinx Inc. 1988. |
A.Agarwal; Virtual Wires: A Technology for Massive Multi FPGA Systems; Virtual Machine Works. * |
A.Agarwal; Virtual Wires: A Technology for Massive Multi-FPGA Systems; Virtual Machine Works. |
Abramovici, et al., "A Logic Simulation Machine," 19th Design Automation Conference, Paper 7.4, 1982, pp. 65-73. |
Abramovici, et al., A Logic Simulation Machine, 19 th Design Automation Conference, Paper 7.4, 1982, pp. 65 73. * |
Agrawal, et al. "MARS: A Multiprocessor-Based Programmable Accelerator", IEEE Design & Test Computers, Oct. 1987, pp. 28-36. |
Agrawal, et al. MARS: A Multiprocessor Based Programmable Accelerator , IEEE Design & Test Computers, Oct. 1987, pp. 28 36. * |
Alfred E. Dunlop, et al., "A Procedure for Placement of Standard-Cell VLSI Circuits," 1985 IEEE, pp. 92-98. |
Alfred E. Dunlop, et al., A Procedure for Placement of Standard Cell VLSI Circuits, 1985 IEEE, pp. 92 98. * |
Anderson, "Restructurable VLSI Program" Report No. ESD-TR-80-192 (DARPA Contract No. F19628-80-C-0002), Mar. 31, 1980. |
Anderson, Restructurable VLSI Program Report No. ESD TR 80 192 (DARPA Contract No. F19628 80 C 0002), Mar. 31, 1980. * |
Andrew B. Kahng, "Fast Hypergraph Partition," pp. 662-666, 26th ACM/IEEE Design Automation Conference. |
Andrew B. Kahng, Fast Hypergraph Partition, pp. 662 666, 26 th ACM/IEEE Design Automation Conference. * |
Balakrishman Krishnamurthy, "An Improved Min-Cut Algorithm for Partitioning LVSI Networks," May 1984, pp. 438-446, IEEE Transactions on Computers, vol. C-33, No. 5. |
Balakrishman Krishnamurthy, An Improved Min Cut Algorithm for Partitioning LVSI Networks, May 1984, pp. 438 446, IEEE Transactions on Computers, vol. C 33, No. 5. * |
Beece et al. "The IBM Engineering Verification Engine," 25th ACM/IEEE Design Automation Conference, Paper 17.1, 1988 pp. 218-224. |
Beece et al. The IBM Engineering Verification Engine, 25 th ACM/IEEE Design Automation Conference, Paper 17.1, 1988 pp. 218 224. * |
Beresford, An Emulator for CMOS ASICS, VLSI Systems Design, May 4, 1987, p. 8. * |
Beresford, Hard Facts, Soft ASICS, VLSI Systems Design, Dec. 1986, p. 8. * |
Borriello; "High-Level Synthesis: Current Status and Future Directions" IEEE 1988, pp. 477-482. |
Bradsma, et al., "The Hardware Simulator: A Tool for Evaluting Computer Systems," IEEE Transactions on Computers, Jan., 1977, pp. 68-72. |
Chapter 36, "Switching Networks and Traffic Concepts,"Reference Data for Radio Engineers, Howard W. Sams & Co., 1981, pp. 36-1 to 36-16. |
Chapter 36, Switching Networks and Traffic Concepts, Reference Data for Radio Engineers, Howard W. Sams & Co., 1981, pp. 36 1 to 36 16. * |
Chen, "Fault-Tolerant Wafer Scale Architectures Using Large Crossbar Switch Arrays," excerpt from Jesshope, et al., Wafer Scale Integration, A.Hilger, 1986, pp. 113-124. |
Chen, Fault Tolerant Wafer Scale Architectures Using Large Crossbar Switch Arrays, excerpt from Jesshope, et al., Wafer Scale Integration, A.Hilger, 1986, pp. 113 124. * |
Chin, et al. A Dynamically Reconfigurable Interconnect Chip: IEEE International Solid State Circuits conference, 1987; pp. 276 277 & 425. * |
Chin, et al. A Dynamically Reconfigurable Interconnect Chip: IEEE International Solid State Circuits conference, 1987; pp. 276-277 & 425. |
Ching Wei Yeh, et al., A General Purpose Multiple Way Partitioning Algorithm, pp. Q15400 Q15405. * |
Ching-Wei Yeh, et al., "A General Purpose Multiple Way Partitioning Algorithm," pp. Q15400-Q15405. |
Choi, et al., "Fault Diagnosis of Switches in Wafer-Scale Arrays," IEEE, 1986, pp. 292-295. |
Choi, et al., Fault Diagnosis of Switches in Wafer Scale Arrays, IEEE, 1986, pp. 292 295. * |
Clos, "A Study of Non-Blocking Switching Networks," The Bell System Technical Journal, Mar. 1953, pp. 126-144. |
Clos, A Study of Non Blocking Switching Networks, The Bell System Technical Journal, Mar. 1953, pp. 126 144. * |
D.Jones; A Time-Multiplexed FPGA Architecture For Logic Emulation; 1995. |
DeMicheli, et al., "Hercules-a System for High Level Synthesis," 25th ACM/IEEE Design Automation Conference, 1988, pp. 483-488. |
DeMicheli, et al., "Topological Partitioning of Programmable Logic Arrays," undated, pp. 182-183. |
DeMicheli, et al., Hercules a System for High Level Synthesis, 25 th ACM/IEEE Design Automation Conference, 1988, pp. 483 488. * |
DeMicheli, et al., Topological Partitioning of Programmable Logic Arrays, undated, pp. 182 183. * |
Denneau, "The Yorktown Simulation Engine," 19th Design Automation Conference, Paper 7.2, 1982, pp. 55-59. |
Denneau, The Yorktown Simulation Engine, 19 th Design Automation Conference, Paper 7.2, 1982, pp. 55 59. * |
Donnell, "Corsspoint Switch: A PLD Approach," Digital Design, July 1986 pp. 40-44. |
Donnell, Corsspoint Switch: A PLD Approach, Digital Design, July 1986 pp. 40 44. * |
Dussault, et al., "A High Level Synthesis Tool for MOS Chip Design," 21st Design Automation conference, 1984, IEEE, pp. 308-314. |
Dussault, et al., A High Level Synthesis Tool for MOS Chip Design, 21 st Design Automation conference, 1984, IEEE, pp. 308 314. * |
ERA60100 Electrically Reconfigurable Array ERA, Brochure by Plessey Semiconductors, Apr. 1989. * |
Feng, "A Survey of Interconnection Networks," Computer, Dec. 1981, pp. 12-27. |
Feng, A Survey of Interconnection Networks, Computer, Dec. 1981, pp. 12 27. * |
Fiduccia, et al. "A Linear-Time Heuristic For Improving Network Partitions," IEEE Design Automation Conference, 1982, pp. 175-181. |
Fiduccia, et al. A Linear Time Heuristic For Improving Network Partitions, IEEE Design Automation Conference, 1982, pp. 175 181. * |
Gate Station Reference Manual, Mentor Graphics Corp., 1987 (excerpts). * |
Gentile, et al. "Design of Switches for Self-Reconfiguring VLSO Array Structures," Microprocessing and Microprogramming, North-Holland, 1984, pp. 99-108. |
Gentile, et al. Design of Switches for Self Reconfiguring VLSO Array Structures, Microprocessing and Microprogramming, North Holland, 1984, pp. 99 108. * |
Geoffrey Mott, et al. "The Utility of Hardware Accelerators in the Design Environmment," Oct. 1985, pp. 62-71, VLSI Systems Design. |
Geoffrey Mott, et al. The Utility of Hardware Accelerators in the Design Environmment, Oct. 1985, pp. 62 71, VLSI Systems Design. * |
Goossens, et al., "A Computer-Aided Design Methodology for Mapping DSP-Algorithms onto Custom Multi-Processing Architectures," IEEE 1986, pp. 924-925. |
Goossens, et al., A Computer Aided Design Methodology for Mapping DSP Algorithms onto Custom Multi Processing Architectures, IEEE 1986, pp. 924 925. * |
Hedlund, "Wafer Scale Integration of Parallel Processors," Doctoral Thesis (Purdue University; Office of Naval Research Contracts N00014-80-K-0816 & N00014-81-K-0360) 1982. |
Hedlund, et al., "Systolic Architectures-A Wafer Scale Approach," IEEE, 1984, pp. 604-610. |
Hedlund, et al., Systolic Architectures A Wafer Scale Approach, IEEE, 1984, pp. 604 610. * |
Hedlund, Wafer Scale Integration of Parallel Processors, Doctoral Thesis (Purdue University; Office of Naval Research Contracts N00014 80 K 0816 & N00014 81 K 0360) 1982. * |
Hennessy, "Partitioning Programmable Logic Arrays,"undated, pp. 180-181. |
Hennessy, Partitioning Programmable Logic Arrays, undated, pp. 180 181. * |
Horstmann, "Macro Test Circuit Generation," IBM TDM vol. 18, No. 12, May 1976 pp. 4023-4029. |
Hou, et al., "A High Level Synthesis Tool For Systolic Designs," IEEE, 1988, pp. 665-673. |
Hou, et al., A High Level Synthesis Tool For Systolic Designs, IEEE, 1988, pp. 665 673. * |
I.Maliniak, Pin Multiplexing Yields Low Cost Logic Emulation, Electronic Design, Jan. 1996. * |
I.Maliniak, Pin Multiplexing Yields Low-Cost Logic Emulation, Electronic Design, Jan. 1996. |
IKOS Systems to Acquire Virtual Machineworks; IKOS Systems Mar. 26, 1997. * |
IMB TDM "Testing Multiple Discrete Software Components by Connecting Real and Simulated Hardware Components," vol. 30, No. 4, Sep. 1987, pp. 1844-1845. |
J. Babb, "Virtual Wires; Overcoming Pin Limitations in FPGA-based Logic Emulators", Massachusetts Institute of Technology, Student Workshop on Scalable Computing, Aug. 4, 1993. |
J. Babb, R. Tessier, A.Agarwal, Virtual Wires; Overcoming Pin Limitation, IEEE, 1993, pp. 142 151. * |
J. Babb, R. Tessier, A.Agarwal, Virtual Wires; Overcoming Pin Limitation, IEEE, 1993, pp. 142-151. |
J.Babb, A.Agrawal "More Virtual Wires", article from Webmaster@cag.lcs.mit.edu Feb. 3, 1995. |
J.Babb, A.Agrawal More Virtual Wires , article from Webmaster cag.lcs.mit.edu Feb. 3, 1995. * |
J.W. Babb, "Virtual Wires: Overcomming Pin Limitations in FPGA-based Logic Emulation", Masters Thesis, Massachusette Institute of Technology, Departmment of Electrical Engineering and Computer Science, Nov. 1993; Also available as MIT/LCS Technical Report TR-586. |
J.W. Babb, Virtual Wires: Overcomming Pin Limitations in FPGA based Logic Emulation , Masters Thesis, Massachusette Institute of Technology, Departmment of Electrical Engineering and Computer Science, Nov. 1993; Also available as MIT/LCS Technical Report TR 586. * |
Jorn Garbers, et al., "Findings Clusters in VLSI Circuits," 1990 IEEE, pp. 520-523. |
Jorn Garbers, et al., Findings Clusters in VLSI Circuits, 1990 IEEE, pp. 520 523. * |
Jump, et al. "Microprogrammed Arrays," IEEE Transactions on Computers, vol. C-21, No. 9, Sep. 1972, pp. 974-984. |
Jump, et al. Microprogrammed Arrays, IEEE Transactions on Computers, vol. C 21, No. 9, Sep. 1972, pp. 974 984. * |
Kautz, et al. "Cellular Logic-in-Memory Arrays," IEEE Transaction on Computers, vol. C-18, No. 8, Aug. 1969, pp. 719-727. |
Kautz, et al. Cellular Logic in Memory Arrays, IEEE Transaction on Computers, vol. C 18, No. 8, Aug. 1969, pp. 719 727. * |
Kautz, et al., "Cellular Interconnection Arrays," IEEE Transactions on Computers, vol. C-17, No. 5, May 1968, pp. 443-451. |
Kautz, et al., Cellular Interconnection Arrays, IEEE Transactions on Computers, vol. C 17, No. 5, May 1968, pp. 443 451. * |
Koike, et al., "HAL: A High-Speed Logic Simulation Machine," IEEE Design & Test, Oct. 1985, pp. 61-73. |
Koike, et al., HAL: A High Speed Logic Simulation Machine, IEEE Design & Test, Oct. 1985, pp. 61 73. * |
Kronstadt, et al., "Software Support For the Yorktown Simulation Engine," 19th Design Automation Conference, Paper 7.3, 1982, pp. 60-64. |
Kronstadt, et al., Software Support For the Yorktown Simulation Engine, 19 th Design Automation Conference, Paper 7.3, 1982, pp. 60 64. * |
Kung, "Why Systolic Architectures?," Computer, Jan. 1982, pp. 37-46. |
Kung, Why Systolic Architectures , Computer, Jan. 1982, pp. 37 46. * |
Logic Emulation For The Masses Arrives; IKOS Systems Mar. 26, 1997. * |
M.Dahl, "An Implementation of the Virtual Wires Interconnect Scheme", Masters Thesis, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, Feb. 1994; Also available as MIT/LCS Technical Report. |
M.Dahl, An Implementation of the Virtual Wires Interconnect Scheme , Masters Thesis, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, Feb. 1994; Also available as MIT/LCS Technical Report. * |
M.Dahl,J.Babb,R.Tessler,S.Hanono,D.Hoki and A.Agarwal, "Emulation of a Sparcle Microprocessor With the MIT, Virtual Wires Emulation System", IEEE Workshop on FPGAs for Custom Computing Machines '94 (FCCM '94), Apr. 1994. |
M.Dahl,J.Babb,R.Tessler,S.Hanono,D.Hoki and A.Agarwal, Emulation of a Sparcle Microprocessor With the MIT, Virtual Wires Emulation System , IEEE Workshop on FPGAs for Custom Computing Machines 94 (FCCM 94), Apr. 1994. * |
M.McFarland, A.Parker, R.Camposano "The High-Level Synthesis of Digital Systems", IEEE, 1990, pp. 301-316. |
M.McFarland, A.Parker, R.Camposano The High Level Synthesis of Digital Systems , IEEE, 1990, pp. 301 316. * |
Malik, Sharad, et al., "Combining Multi-Level Decomposition and Topological Partitioning for PLAS," IEEE 1987, pp. 112-115. |
Manning "An Approach to Highly Integrated, Computer-Maintained Cellular Arrays", IEEE Transactions on Computers, Vol. C-26, Jun. 1977, pp. 536-552. |
Manning An Approach to Highly Integrated, Computer Maintained Cellular Arrays , IEEE Transactions on Computers, Vol. C 26, Jun. 1977, pp. 536 552. * |
Manning, "Automatic Test, Configuration, and Repair of Cellular Arrays", Doctoral Thesis MAC TR-151 (MIT), Jun. 1975. |
Manning, Automatic Test, Configuration, and Repair of Cellular Arrays , Doctoral Thesis MAC TR 151 (MIT), Jun. 1975. * |
Mark R. Hartoog, "Analysis of Placement Procedures for VLSI Standard Cell Layout," pp. 314-319, 23rd Design Automation Conference. |
Mark R. Hartoog, Analysis of Placement Procedures for VLSI Standard Cell Layout, pp. 314 319, 23 rd Design Automation Conference. * |
Masson, "A Sampler of Circuit Switching Networks" Computer, Jun. 1979, pp. 32-48. |
Masson, A Sampler of Circuit Switching Networks Computer, Jun. 1979, pp. 32 48. * |
McCarthy, "Partitioning Adapts Large State Machines to PLDs," EDN, Sep. 17, 1987, pp. 163-166. |
McCarthy, Partitioning Adapts Large State Machines to PLDs, EDN, Sep. 17, 1987, pp. 163 166. * |
McClure, "PLD Breadboarding of Gate Array Designs," VLSI Systems Design, Feb. 1987, pp. 36-41. |
McClure, PLD Breadboarding of Gate Array Designs, VLSI Systems Design, Feb. 1987, pp. 36 41. * |
McFarland; "Tutorial on High-Level Synthesis" 25th ACM/IEEE Design Automation Conference, 1988, pp. 330-336. |
Mentor Graphics Corp., "Gate Station User's Manual," 1987, (excerpts). |
Mentor Graphics Corp., Gate Station User s Manual, 1987, (excerpts). * |
Mentor Graphics Corp., Technology Definition Format Reference Manual, 1987, (excerpts). * |
Minnick, "A Programmable Cellular Array," undated, pp. 25-26. |
Minnick, "Cutpoint Cellular Logic," IEEE Transactions on Electronic Comuters, Dec. 1964, pp. 685-698. |
Minnick, "Survey of Microcellular Research," Stanford Research Institute Project 5876 (Contract AF 19(628)-5828), Jul. 1966. |
Minnick, A Programmable Cellular Array, undated, pp. 25 26. * |
Minnick, Cutpoint Cellular Logic, IEEE Transactions on Electronic Comuters, Dec. 1964, pp. 685 698. * |
Minnick, Survey of Microcellular Research, Stanford Research Institute Project 5876 (Contract AF 19(628) 5828), Jul. 1966. * |
Munoz, et al., "Automatic Partitioning of Programmable Logic Devices," VLSI Systems Design, Oct. 1987, pp. 74-86. |
Munoz, et al., Automatic Partitioning of Programmable Logic Devices, VLSI Systems Design, Oct. 1987, pp. 74 86. * |
Nick Schmits, "Emulation of VLSI Devices Using LACs," May 20, 1987, pp. 54-63, VLSI Systems Design. |
Nick Schmits, Emulation of VLSI Devices Using LACs, May 20, 1987, pp. 54 63, VLSI Systems Design. * |
Odaware, "Partitioning and Placement Technique for CMOS Gate Arrays," IEEE Transactions on Computer Aided Design, May 1987, pp. 355-363. |
Odaware, Partitioning and Placement Technique for CMOS Gate Arrays, IEEE Transactions on Computer Aided Design, May 1987, pp. 355 363. * |
Paleski, et al., "Logic Partitioning for Minimizing Gate Arrays," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-2, No. 2, Apr. 1983. |
Paleski, et al., Logic Partitioning for Minimizing Gate Arrays, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. CAD 2, No. 2, Apr. 1983. * |
Pardner Wynn, "In-Circuit Emulation for ASIC-Based Designs," Oct. 1986, pp. 38-46, VLSI Systems Design. |
Pardner Wynn, In Circuit Emulation for ASIC Based Designs, Oct. 1986, pp. 38 46, VLSI Systems Design. * |
Partitioning of PLA Logic, IBM TDM, vol. 28, No. 6, Nov. 1985, pp. 2332 2333. * |
Pfister, "The Yorktown Simulation Engine: Introduction," 19th Design Automation Conference, Paper 7.1 1982, pp. 51-54. |
Pfister, The Yorktown Simulation Engine: Introduction, 19 th Design Automation Conference, Paper 7.1 1982, pp. 51 54. * |
Plus Logic FPGA2020 Field Programmable Gate Array Brochure by Plus Logic, San Jose, CA, pp. 1 13. * |
Prathima Agrawal, "A Hardware Logic Simulation System," Jan. 1980, pp. 19-29, IEEE Transactions on Computer Aided Design, vol. 9, No. 1. |
Prathima Agrawal, A Hardware Logic Simulation System, Jan. 1980, pp. 19 29, IEEE Transactions on Computer Aided Design, vol. 9, No. 1. * |
Preparata, "The Cube-Connected Cycles: A Versatile Network for Parallel Computation," Communications of the ACM, May, 1981, pp. 300-309. |
Preparata, The Cube Connected Cycles: A Versatile Network for Parallel Computation, Communications of the ACM, May, 1981, pp. 300 309. * |
R. Ayres, "Silicon Compilation a Hierarchical Use of PLAs", Xerox Corporation, pp. 314-326. |
R. Tessier "More Virtual Pictures", article from Webmaster@cag.Ics.mit.edu Feb. 3, 1995. |
R. Tessier More Virtual Pictures , article from Webmaster cag.Ics.mit.edu Feb. 3, 1995. * |
R. Tessier, J.Babb, M.Dahl, S.Hanono and D.Hoki, "The Virtual Wires Emulation System: A Gate-Efficient ASIC Prototyping Environment", MIT, Student Workshop on Scalable Computing Jul. 21-22 1994. |
R.Goering; Emulation for the Masses Electronic Engineering Times; Jan. 96. * |
R.Tessier, J.Babb,M.Dahl, S.Hanono and A.Agarwal, "The Virtual wires Emulation System; A Gate Efficient ASIC Prototyping Environment", ACM Workshop on FPGA's (FPGA '94) Feb. 94. |
R.Tessier, J.Babb,M.Dahl, S.Hanono and A.Agarwal, The Virtual wires Emulation System; A Gate Efficient ASIC Prototyping Environment , ACM Workshop on FPGA s (FPGA 94) Feb. 94. * |
Ravenscroft, Function Language Extractor and Boolean Generator IEEE 1986, pp. 120 123. * |
Ravenscroft, Function Language Extractor and Boolean Generator IEEE 1986, pp. 120-123. |
Runner, "Synthesizing Ada's Ideal machine Mate," VLSI Systems Design, Oct., 1988, pp. 30-39. |
Runner, Synthesizing Ada s Ideal machine Mate, VLSI Systems Design, Oct., 1988, pp. 30 39. * |
S.Hanono, "Inner View Hardware Debugger; A Logic Analysis Tool for the Virtual Wires Emulation Systems", Masters Thesis, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, Jan. 1995; Also available as MIT/LCS Technical Report. |
S.Hanono, Inner View Hardware Debugger; A Logic Analysis Tool for the Virtual Wires Emulation Systems , Masters Thesis, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, Jan. 1995; Also available as MIT/LCS Technical Report. * |
Sami, et al. "Reconfigurable Architectures for VLSI Processing Arrays," AFIPS Conference Proceedings, 1983 National Computer Conference, May 16-19, 1983, pp. 565-577. |
Sami, et al. Reconfigurable Architectures for VLSI Processing Arrays, AFIPS Conference Proceedings, 1983 National Computer Conference, May 16 19, 1983, pp. 565 577. * |
Schmitz, "Emulation of VLSI Devices Using LCAs," VLSI systems Design, May 20, 1987, pp. 54-62. |
Schmitz, Emulation of VLSI Devices Using LCAs, VLSI systems Design, May 20, 1987, pp. 54 62. * |
Schweikert, "A Proper Model for the Partitioning of Electrical Circuits," Bell Telephone Laboratories, Inc. Murray Hill, N.J., pp. 57-62. |
Schweikert, A Proper Model for the Partitioning of Electrical Circuits, Bell Telephone Laboratories, Inc. Murray Hill, N.J., pp. 57 62. * |
Shear, Tools help you retain the advantages of using breadboards in gate array design, EDN, Mar. 18, 1987, pp. 81 88. * |
Shear,"Tools help you retain the advantages of using breadboards in gate-array design," EDN, Mar. 18, 1987, pp. 81-88. |
Shoup, "Programmable Cellular Logic Arrays," Doctoral Thesis (Carnegie-Mellon University; DARPA contract No. F44620-67-C0058), Mar. 1970. |
Shoup, "Programmable Cellular Logic," undated, pp. 27-281. |
Shoup, Programmable Cellular Logic Arrays, Doctoral Thesis (Carnegie Mellon University; DARPA contract No. F44620 67 C0058), Mar. 1970. * |
Shoup, Programmable Cellular Logic, undated, pp. 27 281. * |
Siegel "The Design of a Logic Simulation Accelerator", Oct. 1985 pp. 76-86 VLSI Systems Design. |
Siegel The Design of a Logic Simulation Accelerator , Oct. 1985 pp. 76 86 VLSI Systems Design. * |
Snyder, "Introduction to the Configurable, Highly Parallel Computer," Report CSD-TR-351, Office of Naval Research Contracts N00014-80-K-0816 and N00014-8-1-K-0360, Nov. 1980. |
Snyder, Introduction to the Configurable, Highly Parallel Computer, Report CSD TR 351, Office of Naval Research Contracts N00014 80 K 0816 and N00014 8 1 K 0360, Nov. 1980. * |
Spandorfer, "Synthesis of Logic Functions on an Array of Integrated Circuits", Contract Report AFCRI-6-6-298, Oct. 31, 1965. |
Spandorfer, Synthesis of Logic Functions on an Array of Integrated Circuits , Contract Report AFCRI 6 6 298, Oct. 31, 1965. * |
T.J. Bauer, Thje Design of an Efficient Hardware Subroutine Protocol for FPGAs Masters Thesis, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, May. 1994; Also available as MIT/LCS Technical Report. * |
T.Payne; Automated Partitioning of Hierarchically Specified Digital Systems; May 1981, pp. 1 132. * |
T.Payne; Automated Partitioning of Hierarchically Specified Digital Systems; May 1981, pp. 1-132. |
Tham, "Parallel Processing CAD Applications", IEEE Design & Test of Computer, Oct. 1987, pp. 13-17. |
Tham, Parallel Processing CAD Applications , IEEE Design & Test of Computer, Oct. 1987, pp. 13 17. * |
The Homogenous Computational Medium; New Technology For Computation , Concurrent Logic Inc., Jan. 26, 1987. * |
The Programmable Gate Array Data Book , Xilinx Inc. 1988. * |
Trickey, "Flamel: A High-Level Hardware Compiler," IEEE Transaction on Computer-Aided Design, Mar., 1987, pp. 259-269. |
Trickey, Flamel: A High Level Hardware Compiler, IEEE Transaction on Computer Aided Design, Mar., 1987, pp. 259 269. * |
VHDL Mixed Level Fault Simulator; IKOS Systems Mar. 26, 1997. * |
VHDL Mixed-Level Fault Simulator; IKOS Systems Mar. 26, 1997. |
VirtuaLogic SLI Emulation System; IKOS Systems Mar. 26, 1997. * |
Wagner, "The Boolean Vector Machine," ACM SIGARCH, 1983, pp. 59-66. |
Wagner, The Boolean Vector Machine, ACM SIGARCH, 1983, pp. 59 66. * |
William S. Carter, et al., "A User Programmable Reconfigurable Logic Array," 1986 IEEE, pp. 233-235, Custom Integrated Circuits Conference. |
Wirbel, Plus Logic Rethinks PLD Approach, newspaper article, not dated, one page. * |
Wolfgang Rosenstiel, "Optimizations in High Level Synthesis," 1986, pp. 347-352, Microprocessing and Microprogramming. |
Wolfgang Rosenstiel, Optimizations in High Level Synthesis, 1986, pp. 347 352, Microprocessing and Microprogramming. * |
Wynn, "In-Circuit Emulation for ASIC-Based Designs" VLSI Systems Design, Oct. 1986, pp. 38-45. |
Wynn, In Circuit Emulation for ASIC Based Designs VLSI Systems Design, Oct. 1986, pp. 38 45. * |
Xilinx, First Edition, "The Programmable Gate Array Design Handbook," 1986, pp. 1-1 to 4-33. |
Xilinx, First Edition, The Programmable Gate Array Design Handbook, 1986, pp. 1 1 to 4 33. * |
Yen Chuen Wei, et al. Towards Efficient Hierarchial Designs by Ratio Cut Partitioning, 1989 IEEE. * |
Yen Chuen Wei, et al., Ratio Cut Partitioning for Hierarchial Designs, pp. 1 24. * |
Yen-Chuen Wei, et al. "Towards Efficient Hierarchial Designs by Ratio Cut Partitioning,"1989 IEEE. |
Yen-Chuen Wei, et al., "Ratio Cut Partitioning for Hierarchial Designs," pp. 1-24. |
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