|Publication number||US5905387 A|
|Application number||US 08/742,978|
|Publication date||18 May 1999|
|Filing date||1 Nov 1996|
|Priority date||3 Nov 1995|
|Also published as||EP0774726A1|
|Publication number||08742978, 742978, US 5905387 A, US 5905387A, US-A-5905387, US5905387 A, US5905387A|
|Inventors||Mauro Chinosi, Roberto Canegallo, Alan Kramer, Roberto Guerrieri|
|Original Assignee||Stmicroelectronics, S.R.L.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Non-Patent Citations (2), Referenced by (23), Classifications (9), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates generally to analog voltage-signal selector devices, and more specifically to a device for selecting within a group of analog voltage signals of predetermined value the one with the highest value.
The field of application of the present invention specifically concerns pattern classifiers and the following description is given with reference to a device for selecting within a group of analog voltage-signals of predetermined value the one with the highest value.
As known, the majority of these devices, which are known in the literature as "Winner Take All" (WTA), are provided by means of architectures which exhibit a voltage-follower configuration and make use of inhibitor mechanisms operating among the calculation elements included in them.
A first known technical solution, shown in FIG. 1 and described in the article "Winner Take All Networks of O(N) Complexity," J. Lazzaro et al., Neural Inform Proc. Syst. 1:703-711, Denver, Colo., 1989, calls for the use of a selector device 1 comprising a plurality of circuit branches 2 operating in parallel and each including a first voltage follower transistor T1i and a second local positive feedback transistor T2i, where i=1,. . . j, . . . n.
The device I also comprises a total feedback line LN common to all the circuit branches 2.
Operation of the selector device 1 is as follows.
Each circuit branch 2 receives the input of a one-way current Ii and supplies output of a voltage Vi which represents the result of the selection process.
When the current Ii=max (Il,. . . In), the voltage Vi coincides with a logarithmic function of Ii, and if the current Ij<<Ii, the voltage Vj˜0.
Although advantageous in some ways, this first solution exhibits diverse shortcomings.
Indeed, the device 1 does not provide any offset compensation and has a calculation time which depends on the number of elements making it up.
A second known technical solution is described in the article "A Scalable High-Speed Current-Mode Winner Take All Network for VLSI Neural Applications," Sean Smedley et al., IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications 42(5), 1995 which proposes a tree-structured circuit comprising a plurality of cells provided by using bipolar transistors integrated with a BICMOS technology.
Each cell receives at input two current signals I1 and I2 which are compared with each other to select the highest one.
The latter represents the input for a cell included in a subsequent layer of the tree structure and so on until there is obtained at output the higher input current signal.
In accordance with one aspect of the present invention, an analog voltage-signal selector device includes a plurality of comparator circuits that operate in parallel and that each have at least a first and a second input terminal that are designed to receive respectively an analog voltage-comparison signal and analog voltage signals of predetermined value, and that each include at least one output terminal that provides a digital voltage signal. The selector device also includes at least one logic circuit that has a plurality of input terminals that are each coupled to the output terminal of a corresponding one of the comparator circuits, and that each have at least one output terminal. A plurality of latches each have at least one input terminal that is coupled to the output terminal of a corresponding one of the comparator circuits and that each have at least one drive terminal coupled to the output terminal of the logic circuit, and each having at least one output terminal that corresponds to an output of the selector device.
An advantage of the present invention is that it provides an analog voltage-signal selector device having low calculation time in addition to exhibiting high accuracy and flexibility.
The characteristics and advantages of the method in accordance with the present invention are set forth in the description of an embodiment thereof given below by way of nonlimiting example with reference to the annexed drawings.
FIG. 1 shows a circuit diagram of a selector device provided in accordance with the prior art.
FIG. 2 shows a block diagram of a selector device provided in accordance with the present invention.
FIG. 3 shows charts, with the same time base, of electrical signals present in the device of FIG. 2.
FIG. 4 shows a portion of the device of FIG. 2.
FIG. 5 shows a time chart of electrical signals present in the circuit portion shown in FIG. 4.
FIG. 6 shows a possible circuit embodiment of a portion of the block diagram of FIG. 2.
FIG. 7 shows a time chart of additional electrical signals present in the circuit portion shown in FIG. 4.
FIG. 8 shows a possible circuit application of the selector device in accordance with the present invention.
With reference to FIGS. 2-8, reference number 1 indicates as a whole and diagrammatically an analog voltage-signal selector device provided in accordance with the present invention.
With reference to FIG. 2, the selector device 1 comprises a plurality of comparator circuits Ci with, e.g., i=1, 2, 3, and operating in parallel.
Each comparator circuit Ci comprises first and second input terminals designed to respectively receive an analog voltage comparison signal RAMP and analog voltage signals Vi of predetermined value, and an output terminal for digital voltage signals Voi.
The analog voltage comparison signal RAMP and the analog voltage signals Vi are obtained through first conventional signal generator means that are outside the device 1 and thus not shown in FIG. 2 for clarity.
In addition, the analog voltage comparison signal RAMP is the decreasing monotone type as shown in FIG. 3.
Each comparator circuit Ci also incorporates between its input terminals and its output terminal first, second, and third inverters INV1, INV2, and INV3, which are mutually cascaded, i.e., serially coupled, with one another.
The first inverter INV1 comprises an input terminal and an output terminal that is fedback to the input terminal through a first switch circuit element Si.
This first switch circuit element Si is driven by means of a third digital signal C1, shown in FIG. 3, and obtained through second conventional signal generator circuit means that are external to the device 1 and thus not shown in FIG. 2 for clarity.
The first and second input terminals of each comparator circuit Ci are alternately coupled to the input of the first inverter INV1 through a second and a third switch circuit elements SWi' and SWi", respectively, which are both coupled to a capacitive element Cci.
The second SWi' and third SWi' switch circuit elements are driven respectively by a first digital clock Ck and a second complementary digital clock Ck that are generated by third conventional signal generator circuit means that are external to the device 1 and thus not shown in FIG. 2 for clarity. In one aspect of the invention, Ck is the same as C1 of FIG. 3, and Ck is the inverse of C1.
The device 1 also incorporates a logic circuit L--a NOR gate L in the illustrated embodiment--having a plurality of input terminals that are each coupled to a corresponding output terminal of the comparator circuits Ci, and having an output terminal.
The device 1 comprises lastly a plurality of latches Mi each having an input terminal connected to the output terminal of a corresponding comparator circuit Ci and a drive, i.e., enable, terminal coupled to the output terminal of the logic circuit L.
These latches Mi also include output terminals (i.e., VOUT1, VOUT2, VOUT3, respectively) that provide the outputs of the device 1.
Referring to FIGS. 4 and 5, the comparator circuit Ci also comprises a feedback network Ri that is inserted between the output terminal VINT and the input terminal of the second inverter INV2, and is designed to reduce the response time of the inverter INV1.
This feedback network Ri comprises a first p-channel MOS enhancement transistor T1 having a first terminal connected to the input terminal of the second inverter INV2, having a control terminal coupled to drive circuit means designed to generate a digital signal Ck1--which is shown in FIG. 5--and having a second terminal.
The feedback network Ri also comprises a second p-channel MOS transistor T2 having a first terminal connected to the second terminal of the first transistor T1, a second terminal connected to the supply voltage reference Vdd, and a control terminal connected to the output terminal of the second inverter INV2.
FIG. 6 shows one possible circuit embodiment of the comparator circuit Ci of the selector device 1.
With reference to FIG. 6, the first Si, second SWi' and third SWi" switch circuit elements are the complementary CMOS type.
The first inverter INV1 is implemented by means of the cascade between a first and a second p-channel MOS transistors and a third and a fourth n-channel MOS transistors while the second inverter INV2 includes the cascade between fifth and sixth transistors that are respectively p-channel and an n-channel MOS transistors having control terminals connected together. The third inverter INV3 includes a p-channel transistor that is cascaded with an n-channel transistor.
The logic circuit L is provided as a wired NOR gate with n inputs where n is the number of comparator circuits Ci included in the device 1. For example, in this case n=3. The output of the inverter INV3, i.e., the output Voi, is coupled to the gate of a transistor 10. The drain of the transistor 10 is wired to the drains of the transistors 10 of the remaining comparators Ci. Thus, the drains of the transistors 10 of all the comparators Ci are wired together to form the output of the NOR gate L. A pull-up impedance (not shown) couples the wired NOR output of the gate L to Vdd. Alternatively, the inverters INV3 may be omitted, and the NOR gate replaced with an AND gate.
The latches Mi are conventional, and for clarity, are omitted from FIG. 6.
Still referring to FIG. 6, there is now described operation of the device 1 in accordance with the present invention with specific reference to an initial state in which the first Si and second SWi' switch circuit elements are closed, while the third switch circuit element SWi" is open.
In this first phase, termed "memorization," the second input terminals of the comparator circuits Ci simultaneously receive the analog voltage signals Vi while the input of the first inverter INV1 is short-circuited with its output.
The capacitive element Cci is charged to a voltage Vcci corresponding to the difference between the input voltage signal Vi and a threshold voltage Vthi for each comparator Ci, i.e.:
where Vthn is the nominal threshold voltage of INV1, while Voffi represents the offset voltage for the threshold voltage Vthi and can differ from one comparator to another.
During the memorization phase, in each comparator Ci flows a supply current, which charges the capacitive element Cci and which drives toward equilibrium the voltages present at the input and output of the first inverter INV1.
After this first phase, the first Si and the second SWi' switch circuit elements open while the third switch circuit elements SWi" close.
During this second phase, termed "comparison," the first input terminal of each comparator Ci receives the analog voltage comparison signal RAMP.
The initial voltage value of RAMP is greater than the maximum value reached by any of the input voltage signals Vi.
In the comparison phase, the input of the first inverter INV1 presents a high impedance so that the capacitive element Cci behaves like a DC level shifter and takes this input to a level such that the first inverter INV1 generates a low logic level at its output.
In this manner all the outlet terminals Voi of the comparators Ci are at a low logic level, the output of the NOR gate L is at a high logic level, and all the latches Mi are enabled or disabled, depending on whether the latches are active low or active high as discussed below.
When the voltage comparison signal RAMP begins to decrease linearly in time with constant slope, there is created on the input of the first inverter INV1 a voltage Vfi which follows the linear decrease of RAMP, but which is offset from RAMP by the voltage stored on the capacitor Cci.
When the voltage Vfi reaches the value:
the output of the first inverter INV1 begins to transition from a logic low to a logic high, as does Voi.
Formula (1) can also be rewritten as follows.
By simplifying the common terms, the voltages Voi at the output terminals of the comparators Ci begin to move to a high logic level when:
Consequently, since initially the voltage comparison signal RAMP has a value higher than the maximum value reached by any of the input voltage signals Vi, and in addition is monotonically decreasing, the voltage Voi at the output terminal of the comparator Ci that receives at its input the input voltage signal Vi of highest value begins transitioning to logic high first, while each of the voltages Voi at the output terminals of the other comparators Ci begin their transitions at a subsequent time that is proportional to the value of the corresponding input voltage signal Vi previously memorized.
For example purposes, the digital voltage signals Voi are shown in FIG. 3 where Vo1>Vo2>Vo3.
The logic gate L detects which output Voi of the comparators Ci first moves to a high logic level, and in response to this detection, generates a logic low at its output terminal. In one embodiment of the invention, the latches Mi are active low, such that the logic low at the output of the logic gate L enables them. In this embodiment, in response to the logic gate L detecting the first logic-high output voltage Voi of the comparator Ci that corresponds to the highest voltage Vi, the logic gate L enables all of the latches Mi such that the latch Mi that corresponds to the highest voltage Vi stores and outputs a logic high.
The remaining latches Mi then store high logic levels successively in such a manner as to output from the device 1 a digital vector comprising n components, where n corresponds to the number of input voltage signals Vi.
The components of the output vector at each instant represent the outputs OUTi activated, i.e., at a high logic level, up to that moment.
If the output vector is read when it contains only a single logic "1," the selector device 1 implements the so-called WTA function. That is, the selector device 1 is being used to determine which of the signals Vi has the highest value.
In another embodiment of the invention, all of the latches Mi are active high. Thus, before the logic gate L detects the highest voltage Vi, i.e., before RAMP descends to the highest voltage Vi, all of the latches Mi are enabled. When the output voltage Voi corresponding to the highest voltage Vi transitions to a logic 1, this logic high is stored in the corresponding latch Mi. After a time that is equal to the delay of the NOR gate L, the output of the NOR gate L transitions to a logic low and thus disables all of the latches Mi. Thus, only the latch Mi that corresponds to the highest voltage Vi stores a logic high, and the remaining latches store a logic low. Thus, one can examine the outputs of the latches Mi to determine which of the signals Vi has the highest value, and can perform this examination at virtually any time after the highest value Vi is detected without having to worry that the state of the remaining latches will change as the ramp further decreases.
In addition, by inverting the slope of the voltage comparison signal RAMP and changing the MOS feedback transistors T1 and T2 from p-channel to n-channel, the same architecture provided in accordance with the present invention permits sorting the values of the input voltage signals Vi in increasing order and detecting among them the one with the least value, (Loser Take All LTA!).
Specifically, the main condition for implementation of a WTA function with high precision is linked to the separation in time of the individual components of the output vector.
To separate two consecutive components of the output vector the delay between them must be greater than the delay introduced by the logic gate L.
Defining the delay introduced by the logic gate L as "Tdgn," Tdgn is the minimum time Tm required to separate two consecutive components of the output vector, that is:
With reference to FIG. 3, it is found that the separability condition for a differential input voltage signal ΔVi corresponding to a distance in time ΔTi is given by:
where V is the amplitude of the voltage reference signal RAMP, Tr is the time employed by this signal to cover the amplitude V and S is its slope.
Once the value of the parameter V is set in accordance with the interval of values in which are included the input voltage signals Vi, condition (2) is satisfied when:
By decreasing the value of Tr below this value, more than one output voltage Voi can be activated, i.e., logic high, before the logic gate L enables or disables the latches Mi. Thus, several winners can be drawn at the same time.
The parameter Tr can also be used for selecting the highest or the lowest allowed intervals ΔVi between the input voltage signals Vi.
From the above discussion it follows that by decreasing or increasing the parameter Tr, i.e., by modifying the slope of the voltage comparison signal RAMP, the precision of the device 1 increases or decreases.
It also follows that the feedback network R contributes to reducing the uncertainties present in the device 1 and to increasing its speed.
The network R is enabled after the comparison phase is terminated, but begins to act only when the first inverter INV1 begins changing its output state from a logic low to a logic high.
Once the output of this first inverter INV1 is at a high enough level to permit the second inverter INV2 to modify its output state to a logic low, the feedback network Ri causes the output level of the first inverter INV1 to rise faster.
The feedback network Ri can be disabled after the voltage signals Voi have been memorized by the latches Mi.
FIG. 7 shows the behavior of the voltage signal output from the first inverter INV1 with and without the feedback network R.
FIG. 8 shows a conventional electronic classification system CLASS including a selector device having outputs OUT provided in accordance with the present invention.
The electronic classification system CLASS comprises a plurality of input terminals designed to receive strings of digital signals SDi with, e.g., i=1, 2, and a plurality of output terminals.
This system also includes an associative memory MA comprising groups 2 of memory blocks SRAM/XNOR connected together through respective input terminals leading to an input terminal of the system and each having an output connected to a same output of the membership group 2.
The memory MA makes a comparison between strings of digital reference signals stored therein and the digital input signal SDi strings. For example, each of the memory blocks in the first group 2 compares a component of the input vector SD1 with a stored value and then outputs a current on the node 2 that is representative of the comparison. In one aspect of the invention, if the compared component of the vector SD1 and the value stored in the associated memory block SRAM/XNOR are equal, the memory block sinks a current from node 2, and if the vector component and stored value are not equal, the memory block neither sinks nor sources a current to the node 2.
The classification system CLASS also incorporates a plurality of adding circuits SUMi each having an output terminal and at least one first input terminal connected to an output of a corresponding group 2 of the associative memory MA and a second input terminal connected to a fixed voltage reference GND. Thus, each adding circuit SUMi converts the sum of the currents generated by the memory blocks in a corresponding group 2 into a voltage at the output of the circuit SUMi. In one aspect of the invention, the circuits SUMi each include an operational amplifier that has its noninverting input terminal coupled to ground and its inverting input terminal coupled to the common output of the associated group 2 of memory blocks. A feedback impedance Ii is coupled between the inverting input terminal and the output of the operational amplifier.
Finally, the system CLASS comprises a selector device 1 of FIG. 2 that has its input terminals respectively coupled to the output terminals of the circuits SUMi. The outputs OUT of the selector device I provide the output terminals of the CLASS system.
In the application described here, the device 1 selects the memorized digital signal string corresponding to the input digital signal string on the basis of a relationship implemented in the memory MA. Specifically, in a Winner Take All embodiment, the device 1 identifies which of the circuits SUMi generates the highest output voltage, and thus which group 2 of memory blocks SRAM/XNOR sinks the largest total current from the common output node that is connected to the input of the SUMi circuit. The group 2 that generates the highest current is the one that finds the most matches between the values stored in the memory blocks SRAM/XNOR and the corresponding components of the input digital vector SDi. For example, suppose there are ten blocks SRAM/XNOR in each group 2, and that each vector SDi includes ten corresponding components. Furthermore, assume that out of the ten possible matches between the ten values stored in the memory blocks SRAM/XNOR and the ten components of the vectors SDi, there are eight matches between the components of SD1 and the corresponding group 2, and four matches between the components of SD2 and its corresponding group 2. Therefore, the group 2 corresponding to SD1 would sink a greater current than the group 2 corresponding to SD2, and thus SUM1 would generate a greater output voltage than SUM2. The selector device 1 would then identify that SUM1 had the higher input voltage. One could then read this data and determine that there were more matches with SD1 than there were with SD2.
The CLASS system of FIG. 8 can be used in analog associative memories for pattern recognition as well as in associative memories in general. For example, the CLASS system can be used in an optical character recognition (OCR) system, or for simple motion control functions in robotics. The CLASS system can also be used in personal digital assistants (PDA). For example, where the CLASS system is part of an OCR system, the CLASS circuit receives at all of its inputs a vector SD that represents a character. The CLASS circuit also stores in the memory MA a database of characters. The vector SD is then compared with each of the characters that are stored in the groups 2 of memory blocks SRAM/XNOR. Each of the groups 2 generates at its common output node a current that is proportional to the number of matches between the stored values and the components of the vector SD. The WTA circuit 1 then determines which of the currents is the greatest, i.e., which of the stored characters has the most component matches with the vector SD, and thus which character the vector SD represents. The vector SD is then coded into the recognized character by circuitry that is not shown here for clarity.
From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5408194 *||25 Jun 1993||18 Apr 1995||Synaptics, Incorporated||Adaptive analog minimum/maximum selector and subtractor circuit|
|US5539340 *||31 Oct 1994||23 Jul 1996||U.S. Philips Corporation||Circuit for detecting pulses, and video recorder comprising the circuit|
|US5546028 *||7 Sep 1995||13 Aug 1996||Nec Corporation||Chopper type comparator for an analog-to-digital converter|
|EP0653793A1 *||29 Jul 1993||17 May 1995||SHIBATA, Tadashi||Semiconductor device|
|JP36226691A *||Title not available|
|JP40401431A *||Title not available|
|1||Yamashita, Takeo et al., "Neuron MOS Winner-Take-All Circuit and Its Application to Associative Memory," in IEEE International Solid-State Circuits Conference, New York, Feb. 1993, pp. 236-237, and 294.|
|2||*||Yamashita, Takeo et al., Neuron MOS Winner Take All Circuit and Its Application to Associative Memory, in IEEE International Solid State Circuits Conference , New York, Feb. 1993, pp. 236 237, and 294.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6127852 *||2 Jul 1998||3 Oct 2000||Canon Kabushiki Kaisha||Semiconductor integrated circuit for parallel signal processing|
|US6188251 *||1 Apr 1998||13 Feb 2001||Roland Priemer||Analog voltage maximum selection and sorting circuits|
|US6362662 *||4 May 2001||26 Mar 2002||Winbond Electronics Corp.||Analog W.T.A. circuit reject signal|
|US6583651||7 Dec 2001||24 Jun 2003||Stmicroelectronics, Inc.||Neural network output sensing and decision circuit and method|
|US6686786||31 Aug 2001||3 Feb 2004||Micron Technology, Inc.||Voltage generator stability indicator circuit|
|US6696867 *||18 Jul 2001||24 Feb 2004||Micron Technology, Inc.||Voltage generator with stability indicator circuit|
|US6710630||10 Jul 2001||23 Mar 2004||Micron Technology, Inc.||256 Meg dynamic random access memory|
|US7673195 *||3 Oct 2007||2 Mar 2010||International Business Machines Corporation||Circuits and methods for characterizing device variation in electronic memory circuits|
|US7969810||6 Mar 2009||28 Jun 2011||Round Rock Research, Llc||256 Meg dynamic random access memory|
|US8086917||17 Aug 2009||27 Dec 2011||International Business Machines Corporation||Methods for characterizing device variation in electronic memory circuits|
|US8189423||24 Jun 2011||29 May 2012||Round Rock Research, Llc||256 Meg dynamic random access memory|
|US8368621 *||5 Feb 2013||Lg Display Co., Ltd.||Image display device|
|US8773168 *||10 Jun 2013||8 Jul 2014||Fairchild Semiconductor Corporation||Maximum voltage selection circuit and method and sub-selection circuit|
|US9144126 *||22 Aug 2012||22 Sep 2015||Allegro Microsystems, Llc||LED driver having priority queue to track dominant LED channel|
|US9265104||6 Jul 2011||16 Feb 2016||Allegro Microsystems, Llc||Electronic circuits and techniques for maintaining a consistent power delivered to a load|
|US9337727||6 Jan 2014||10 May 2016||Allegro Microsystems, Llc||Circuitry to control a switching regulator|
|US20060097695 *||10 Nov 2004||11 May 2006||Sicheng Chen||Analog OR circuit with wide input voltage detection range|
|US20090091346 *||3 Oct 2007||9 Apr 2009||International Business Machines Corporation||Circuits and methods for characterizing device variation in electronic memory circuits|
|US20090213148 *||7 May 2009||27 Aug 2009||Shinji Takasugi||Image display device|
|US20090303260 *||27 Oct 2006||10 Dec 2009||Shinji Takasugi||Image Display Device|
|US20090310430 *||17 Aug 2009||17 Dec 2009||International Business Machines Corporation||Methods for characterizing device variation in electronic memory circuits|
|US20140002139 *||10 Jun 2013||2 Jan 2014||Fairchild Semiconductor Corporation||Maximum voltage selection circuit and method and sub-selection circuit|
|US20140055051 *||22 Aug 2012||27 Feb 2014||Allegro Microsystems, Inc.||LED Driver Having Priority Queue to Track Dominant LED Channel|
|U.S. Classification||327/62, 327/64, 327/50, 326/35, 327/63, 327/58|
|25 Feb 1997||AS||Assignment|
Owner name: SGS-THOMSON MICROELECTRONICS S.R.L., ITALY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHINOSI, MAURO;CANEGALLO, ROBERTO;KRAMER, ALAN;AND OTHERS;REEL/FRAME:008440/0800;SIGNING DATES FROM 19961220 TO 19970117
|14 Dec 1998||AS||Assignment|
Owner name: SGS-THOMSON MICROELECTRONICS S.R.L., ITALY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHINOSI, MAURO;CANEGALLO, ROBERTO;KRAMER, ALAN;AND OTHERS;REEL/FRAME:009644/0932
Effective date: 19970305
|4 Nov 2002||FPAY||Fee payment|
Year of fee payment: 4
|27 Oct 2006||FPAY||Fee payment|
Year of fee payment: 8
|26 Oct 2010||FPAY||Fee payment|
Year of fee payment: 12
|3 Jul 2013||AS||Assignment|
Effective date: 20120523
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:STMICROELECTRONICS, S.R.L. (FORMERLY KNOWN AS SGS-THMSON MICROELECTRONICS S.R.L.);REEL/FRAME:031796/0348