US5776836A - Self aligned method to define features smaller than the resolution limit of a photolithography system - Google Patents
Self aligned method to define features smaller than the resolution limit of a photolithography system Download PDFInfo
- Publication number
- US5776836A US5776836A US08/608,691 US60869196A US5776836A US 5776836 A US5776836 A US 5776836A US 60869196 A US60869196 A US 60869196A US 5776836 A US5776836 A US 5776836A
- Authority
- US
- United States
- Prior art keywords
- layer
- etched
- mask layer
- pattern
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
Claims (50)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/608,691 US5776836A (en) | 1996-02-29 | 1996-02-29 | Self aligned method to define features smaller than the resolution limit of a photolithography system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/608,691 US5776836A (en) | 1996-02-29 | 1996-02-29 | Self aligned method to define features smaller than the resolution limit of a photolithography system |
Publications (1)
Publication Number | Publication Date |
---|---|
US5776836A true US5776836A (en) | 1998-07-07 |
Family
ID=24437602
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/608,691 Expired - Lifetime US5776836A (en) | 1996-02-29 | 1996-02-29 | Self aligned method to define features smaller than the resolution limit of a photolithography system |
Country Status (1)
Country | Link |
---|---|
US (1) | US5776836A (en) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6110837A (en) * | 1999-04-28 | 2000-08-29 | Worldwide Semiconductor Manufacturing Corp. | Method for forming a hard mask of half critical dimension |
US20020042007A1 (en) * | 2000-10-06 | 2002-04-11 | Ko Miyazaki | Fabrication method of semiconductor integrated circuit device |
US6383853B2 (en) * | 2000-07-05 | 2002-05-07 | Oki Electric Industry Co., Ltd. | Method of fabricating semiconductor device |
US6455438B1 (en) * | 2000-03-13 | 2002-09-24 | Oki Electric Industry Co., Ltd. | Fabrication method for a semiconductor device |
US6514868B1 (en) * | 2001-03-26 | 2003-02-04 | Advanced Micro Devices, Inc. | Method of creating a smaller contact using hard mask |
US6514867B1 (en) | 2001-03-26 | 2003-02-04 | Advanced Micro Devices, Inc. | Method of creating narrow trench lines using hard mask |
US6519018B1 (en) | 1998-11-03 | 2003-02-11 | International Business Machines Corporation | Vertically aligned liquid crystal displays and methods for their production |
WO2003028104A2 (en) * | 2001-09-05 | 2003-04-03 | Infineon Technologies Ag | Semiconductor memory with memory cells comprising a vertical selection transistor and method for production thereof |
US6610607B1 (en) | 2000-05-25 | 2003-08-26 | International Business Machines Corporation | Method to define and tailor process limited lithographic features using a modified hard mask process |
NL1025475C2 (en) * | 2004-02-12 | 2005-08-15 | C2V | Microstructure producing method for forming e.g. ionizer electrodes, comprises placing substrate with stepped surface in stream of particles |
US20060003182A1 (en) * | 2004-07-01 | 2006-01-05 | Lane Richard H | Method for forming controlled geometry hardmasks including subresolution elements and resulting structures |
CN100334687C (en) * | 2000-07-07 | 2007-08-29 | 株式会社日立制作所 | Method of manufacturing integrated circuit |
US20080028360A1 (en) * | 2006-07-31 | 2008-01-31 | Picciotto Carl E | Methods and systems for performing lithography, methods for aligning objects relative to one another, and nanoimprinting molds having non-marking alignment features |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4759822A (en) * | 1984-10-12 | 1988-07-26 | Triquint Semiconductor Inc. | Methods for producing an aperture in a surface |
US4774206A (en) * | 1986-03-19 | 1988-09-27 | Siemens Aktiengesellschaft | Method for the manufacture of a self-aligned metal contact |
US5294296A (en) * | 1992-02-12 | 1994-03-15 | Hyundai Electronics Industries, Co., Ltd. | Method for manufacturing a contact hole of a semiconductor device |
US5384281A (en) * | 1992-12-29 | 1995-01-24 | International Business Machines Corporation | Non-conformal and oxidizable etch stops for submicron features |
US5403779A (en) * | 1992-02-26 | 1995-04-04 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD |
US5403435A (en) * | 1992-01-23 | 1995-04-04 | Micron Technology, Inc. | Process for selectively etching integrated circuit devices having deep trenches or troughs or elevated features with re-entrant profiles |
US5500080A (en) * | 1993-06-22 | 1996-03-19 | Hyundai Electronics Industries Co., Ltd. | Process of forming contact holes |
-
1996
- 1996-02-29 US US08/608,691 patent/US5776836A/en not_active Expired - Lifetime
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4759822A (en) * | 1984-10-12 | 1988-07-26 | Triquint Semiconductor Inc. | Methods for producing an aperture in a surface |
US4774206A (en) * | 1986-03-19 | 1988-09-27 | Siemens Aktiengesellschaft | Method for the manufacture of a self-aligned metal contact |
US5403435A (en) * | 1992-01-23 | 1995-04-04 | Micron Technology, Inc. | Process for selectively etching integrated circuit devices having deep trenches or troughs or elevated features with re-entrant profiles |
US5294296A (en) * | 1992-02-12 | 1994-03-15 | Hyundai Electronics Industries, Co., Ltd. | Method for manufacturing a contact hole of a semiconductor device |
US5403779A (en) * | 1992-02-26 | 1995-04-04 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD |
US5384281A (en) * | 1992-12-29 | 1995-01-24 | International Business Machines Corporation | Non-conformal and oxidizable etch stops for submicron features |
US5500080A (en) * | 1993-06-22 | 1996-03-19 | Hyundai Electronics Industries Co., Ltd. | Process of forming contact holes |
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6519018B1 (en) | 1998-11-03 | 2003-02-11 | International Business Machines Corporation | Vertically aligned liquid crystal displays and methods for their production |
US6110837A (en) * | 1999-04-28 | 2000-08-29 | Worldwide Semiconductor Manufacturing Corp. | Method for forming a hard mask of half critical dimension |
US6455438B1 (en) * | 2000-03-13 | 2002-09-24 | Oki Electric Industry Co., Ltd. | Fabrication method for a semiconductor device |
US6610607B1 (en) | 2000-05-25 | 2003-08-26 | International Business Machines Corporation | Method to define and tailor process limited lithographic features using a modified hard mask process |
US6383853B2 (en) * | 2000-07-05 | 2002-05-07 | Oki Electric Industry Co., Ltd. | Method of fabricating semiconductor device |
CN100334687C (en) * | 2000-07-07 | 2007-08-29 | 株式会社日立制作所 | Method of manufacturing integrated circuit |
US20020042007A1 (en) * | 2000-10-06 | 2002-04-11 | Ko Miyazaki | Fabrication method of semiconductor integrated circuit device |
US6514868B1 (en) * | 2001-03-26 | 2003-02-04 | Advanced Micro Devices, Inc. | Method of creating a smaller contact using hard mask |
US6514867B1 (en) | 2001-03-26 | 2003-02-04 | Advanced Micro Devices, Inc. | Method of creating narrow trench lines using hard mask |
WO2003028104A3 (en) * | 2001-09-05 | 2003-08-14 | Infineon Technologies Ag | Semiconductor memory with memory cells comprising a vertical selection transistor and method for production thereof |
US20040201055A1 (en) * | 2001-09-05 | 2004-10-14 | Jorn Lutzen | Semiconductor memory with memory cells comprising a vertical selection transistor and method for fabricating it |
US6977405B2 (en) | 2001-09-05 | 2005-12-20 | Infineon Technologies, Ag | Semiconductor memory with memory cells comprising a vertical selection transistor and method for fabricating it |
WO2003028104A2 (en) * | 2001-09-05 | 2003-04-03 | Infineon Technologies Ag | Semiconductor memory with memory cells comprising a vertical selection transistor and method for production thereof |
NL1025475C2 (en) * | 2004-02-12 | 2005-08-15 | C2V | Microstructure producing method for forming e.g. ionizer electrodes, comprises placing substrate with stepped surface in stream of particles |
US20060003182A1 (en) * | 2004-07-01 | 2006-01-05 | Lane Richard H | Method for forming controlled geometry hardmasks including subresolution elements and resulting structures |
US20070020939A1 (en) * | 2004-07-01 | 2007-01-25 | Lane Richard H | Controlled geometry hardmask including subresolution elements |
US7473644B2 (en) | 2004-07-01 | 2009-01-06 | Micron Technology, Inc. | Method for forming controlled geometry hardmasks including subresolution elements |
US20080028360A1 (en) * | 2006-07-31 | 2008-01-31 | Picciotto Carl E | Methods and systems for performing lithography, methods for aligning objects relative to one another, and nanoimprinting molds having non-marking alignment features |
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Legal Events
Date | Code | Title | Description |
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AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANDHU, GURTEJ SINGH;REEL/FRAME:007915/0026 Effective date: 19960227 |
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AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: TO CHANGE STATE OF INCORPORATION OF ASSIGNEE FROM IDAHO TO DELAWARE;ASSIGNOR:SANDHU, GURTEJ SINGH;REEL/FRAME:008169/0846 Effective date: 19960227 |
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Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
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Free format text: PATENTED CASE |
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Owner name: ROUND ROCK RESEARCH, LLC,NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416 Effective date: 20091223 Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416 Effective date: 20091223 |