US5614842A - Semiconductor integrated circuit with buffer circuit and manufacturing method thereof - Google Patents

Semiconductor integrated circuit with buffer circuit and manufacturing method thereof Download PDF

Info

Publication number
US5614842A
US5614842A US08/522,962 US52296295A US5614842A US 5614842 A US5614842 A US 5614842A US 52296295 A US52296295 A US 52296295A US 5614842 A US5614842 A US 5614842A
Authority
US
United States
Prior art keywords
gate
drain
source
output terminal
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/522,962
Inventor
Katsuro Doke
Toshikazu Sei
Yasunobu Umemoto
Eiji Ban
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BAN, EIJI, DOKE, KATSURO, SEI, TOSHIKAZU, UMEMOTO, YASUNOBU
Application granted granted Critical
Publication of US5614842A publication Critical patent/US5614842A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Definitions

  • the present invention relates to a semiconductor integrated circuit and a method of manufacturing the same. More specifically, the present invention relates to a semiconductor integrated circuit provided with a buffer circuit and a method of manufacturing the same semiconductor integrated circuit.
  • FIG. 1 is a circuit diagram showing an example of such a conventional semiconductor integrated circuit.
  • a control circuit 701 when an enable signal B is at a low level, a control circuit 701 outputs low-level output signals EI and EIN in response to a high-level input signal A, whereas high-level output signals EI and EIN in response to a low-level input signal A.
  • the control circuit 701 when the enable signal E is at a high level, the control circuit 701 outputs a high-level output signal EI and a low-level output signal EIN, irrespective of the input signal level.
  • a PMOS transistor 703 and an NMOS transistor 704 constitute an output buffer circuit 702 that is connected to the control circuit 701.
  • the PMOS transistor 703 When the low-level output signal EI of the control circuit 701 is applied to the gate of the PMOS transistor 703, the PMOS transistor 703 is turned on, so that a supply potential supplied to the source of the transistor 703 is applied to an output terminal 707.
  • the output signal EI of the control circuit 701 is at the high level, the PMOS transistor 703 is turned off.
  • the NMOS transistor 704 is turned on, so that a ground potential is applied to the output terminal 707.
  • the output signal EIN of the control circuit 701 is at the low level, the PMOS transistor 704 is turned off.
  • a PMOS transistor 705 acts as a pull-up circuit 705.
  • this PMOS transistor 705 is always kept turned on, so that a supply potential supplied to its source is always applied to the output terminal 707.
  • an input buffer circuit 706 outputs a signal inputted through the output terminal 707 to internal circuitry (not shown) of the semiconductor integrated circuit.
  • the present invention provides a semiconductor integrated circuit, comprising: a first MOS transistor of a first-conductive type having a gate, a source connected to a first voltage supply and a drain connected to an output terminal; a second MOS transistor of a second-conductive type different from the first-conductive type having a gate, a source connected to a second voltage supply different from the first voltage supply in potential and a drain connected to the output terminal; a third MOS transistor of the first-conductive type having a gate connected to the gate of the second MOS transistor, a source connected to the first voltage supply and a drain connected to the output terminal; a fourth MOS transistor of the second-conductive type having a source, a drain and a gate connected to the gate of the first MOS transistor, at least one of the source and drain being floated; and means, responsive to an enable signal and an input signal, for applying control signals to the gates of the first and second MOS transistors to turn on any one of the first and second MOS transistors based on the
  • the present invention provides a semiconductor integrated circuit, comprising: a first MOS transistor of a first-conductive type having a drain, a source connected to a first voltage supply and a drain connected to an output terminal; a second MOS transistor of a second-conductive type different from the first-conductive type having a gate, a source connected to a second voltage supply different from the first voltage supply in potential and a drain connected to an output terminal; a third MOS transistor of the first-conductive type having a source, a drain and a gate connected to the gate of the second MOS transistor, at least one of the source and drain being floated; a fourth MOS transistor of the second-conductive type having a source, a drain and a gate connected to a gate of the first MOS transistor, at least one of the source and drain being floated; and means, responsive to an enable signal and an input signal, for applying control signals to the gates of the first and second MOS transistors to turn on any one of the first and second MOS transistors based on the input signal level when the enable signal
  • the semiconductor integrated circuits may further include means for applying a signal appearing at the output terminal to their internal circuitry.
  • the first and third transistors may be PMOS transistors and the second and fourth transistors may be NMOS transistors.
  • the present invention provides a method of manufacturing a semiconductor integrated circuit including a first MOS transistor of a first-conductive type having a gate, a source connected to a first voltage supply and a drain connected to an output terminal, a second MOS transistor of a second-conductive type different from the first-conductive type having a gate, a source connected to a second voltage supply different from the first voltage supply in potential and a drain connected to the output terminal, a third MOS transistor of the first-conductive type having a gate connected to the gate of the second MOS transistor, a source connected to the first voltage supply and a drain connected to the output terminal and a fourth MOS transistor of the second-conductive type having a source connected to the second voltage supply, a drain connected to the output terminal and a gate connected to the gate of the first MOS transistor, the method comprising the step of: cutting off at least one of wiring connected between the source of the third MOS transistor and the first voltage supply, wiring connected between the drain of the third MOS transistor and the output terminal, wiring connected between the source of the fourth
  • the present invention provides a semiconductor integrated circuit, comprising: a first PMOS transistor having a gate, a source connected to a voltage supply and a drain connected to an output terminal; a first NMOS transistor having a gate, a source connected to a ground and a drain connected to the output terminal; a second PMOS transistor having a gate connected to the gate of the first NMOS transistor, a source connected to the voltage supply and a drain connected to the output terminal via a resistor; a second NMOS transistor having a source, a drain and a gate connected to the gate of the first PMOS transistor, at least one of the source and drain being floated; a NAND gate having one input accepting an input signal and an output connected to the gate of the first PMOS transistor; a NOR gate having one input connected to the one input of the NAND gate, an another input accepting an enable signal and an output connected to the gate of the first NMOS transistor; and an inverter having an input connected to the other input of the NOR gate and an output connected to an another input
  • the semiconductor integrated circuit with the floating second NMOS transistor may further include an input buffer connected to the drain of the second PMOS transistor, for applying a signal appearing at the output terminal to the internal circuitry.
  • the present invention provides a semiconductor integrated circuit, comprising: a first PMOS transistor having a gate, a source connected to a voltage supply and a drain connected to an output terminal; a first NMOS transistor having a gate, a source connected to a ground and a drain connected to the output terminal; a second PMOS transistor having a source, a drain and a gate connected to the gate of the first NMOS transistor, at least one of the source and drain being floated; a second NMOS transistor having a gate connected to the gate of the first PMOS transistor, a source connected to the ground and a drain connected to the output terminal via a resistor; a NAND gate having one input accepting an input signal and an output connected to the gate of the first PMOS transistor; a NOR gate having one input connected to the one input of the NAND gate, an another input accepting an enable signal and an output connected to the gate of the first NMOS transistor; and an inverter having an input connected to the other input of the NOR gate and an output connected to the an another input
  • the semiconductor integrated circuit with the floating second PMOS transistor may further include an input buffer connected to the drain of the second NMOS transistor, for applying a signal appearing at the output terminal to the internal circuitry.
  • the present invention provides a semiconductor integrated circuit, comprising: a first PMOS transistor having a gate, a source connected to a voltage supply and a drain connected to an output terminal; a first NMOS transistor having a gate, a source connected to a ground and a drain connected to the output terminal; a second PMOS transistor having a source, a drain and a gate connected to the gate of the first NMOS transistor, at least one of the source and drain being floated; a second NMOS transistor having a source, a drain and a gate connected to the gate of the first PMOS transistor, at least one of the source and drain being floated; a NAND gate having one input accepting an input signal and an output connected to the gate of the first PMOS transistor; a NOR gate having one input connected to the one input of the NAND gate, an another input accepting an enable signal and an output connected to the gate of the first NMOS transistor; and an inverter having an input connected to the other input of the NOR gate and an output connected to an another input of the N
  • the semiconductor integrated circuit with the floating second PMOS and NMOS transistors may further include an input buffer connected to the output terminal via a resistor, for applying a signal appearing at the output terminal to internal circuitry of the semiconductor integrated circuit.
  • the present invention provides a semiconductor integrated circuit, comprising: a first PMOS transistor having a gate, a source connected to a voltage supply and a drain connected to an output terminal; a first NMOS transistor having a gate, a source connected to a ground and a drain connected to the output terminal; a NAND gate having one input accepting an input signal and an output connected to the gate of the first PMOS transistor; a NOR gate having one input connected to the one input of the NAND gate, an another input accepting an enable signal and an output connected to the gate of the first NMOS transistor; an inverter having an input connected to the other input of the NOR gate and an output connected to an another input of the NAND gate; and a second NMOS transistor having a gate connected to the input of the inverter, a drain connected to the output terminal via a resistor and a source connected to the ground, wherein any one of the first PMOS and NMOS transistors is turned on based on the input signal level when the enable signal is substantially at the ground level, whereas
  • the semiconductor integrated circuit with no floating transistor may further include an input buffer connected to the drain of the second NMOS transistor, for applying a signal appearing at the output terminal to internal circuitry of the semiconductor integrated circuit.
  • FIG. 1 is a circuit diagram showing an example of conventional semiconductor integrated circuit provided with a bidirectional buffer circuit having a pull-up circuit;
  • FIG. 2 is a circuit diagram showing the first preferred embodiment of the semiconductor integrated circuit according to the present invention, in which the bidirectional buffer circuit has a pull-up circuit;
  • FIG. 3 is a circuit diagram for assistance in explaining the manufacturing method of the first embodiment of the semiconductor integrated circuit shown in FIG. 2, in which the state where the wiring is not yet cut off is shown;
  • FIG. 4 is a circuit diagram showing the second preferred embodiment of the semiconductor integrated circuit according to the present invention, in which the bidirectional buffer circuit has a pull-down circuit;
  • FIG. 5 is a circuit diagram showing the third preferred embodiment of the semiconductor integrated circuit according to the present invention, in which the bidirectional buffer circuit has no pull-up and pull-down circuit;
  • FIG. 6 is a circuit diagram showing a modified example embodiment of the semiconductor integrated circuit shown in FIG. 2;
  • FIG. 7 is a circuit diagram showing a modified example of the semiconductor integrated circuit shown in FIG. 4.
  • FIG. 2 in which a bidirectional buffer circuit having a pull-up circuit is shown.
  • the circuit includes a control circuit 110, an output buffer circuit 120, a pull-up circuit 130, and an input buffer circuit 140.
  • the control circuit 110 includes a NOT (inverter) circuit 111, a NAND circuit 112 and a NOR circuit 113.
  • the NAND circuit 112 accepts a signal/E obtained by inverting an enable signal E through the NOT circuit 111 and a signal A, and outputs an inverted control signal EI of a logical product of both the signals/E and A.
  • the NOR circuit 113 accepts the enable signal E and the signal A, and outputs an inverted control signal EIN of a logical sum of both the signals E and A.
  • the control circuit 110 when the enable signal E is at the low level, the control circuit 110 outputs low-level output signals EI and EIN in response to the high-level input signal A, whereas high-level output signals EI and EIN in response to the low-level input signal A.
  • the control circuit 110 when the enable signal E is at the high level, the control circuit 110 outputs a high-level output signal EI and a low-level output signal EIN, irrespective of the level of the input signal A.
  • the output buffer circuit 120 includes a PMOS transistor 121 (the first MOS transistor) and an NMOS transistor 122 (the second MOS transistor).
  • the source of the PMOS transistor 121 is connected to a voltage supply (the first voltage supply) and its drain is connected to an output terminal 160.
  • the signal EI is inputted from the control circuit 110 to the gate of the PMOS transistor 121.
  • the source of the NMOS transistor 122 is connected to a ground voltage (the second voltage supply) and its drain is connected to the output terminal 160.
  • the signal EIN is inputted from the control circuit 110 to the gate of the NMOS transistor 122.
  • the PMOS transistor 121 is turned on when the low-level signal EI is applied from the control circuit 110 to the gate of the PMOS transistor 121.
  • the supply potential supplied to the source of the PMOS transistor 121 is thus applied to the output terminal 160.
  • the PMOS transistor 121 is turned off.
  • the NMOS transistor 122 is turned on when the high-level signal EIN is applied from the control circuit 110 to the gate of the NMOS transistor 122.
  • the ground potential is thus applied to the output terminal 160.
  • the signal EIN is at the low level, the NMOS transistor 122 is turned off.
  • the pull-up circuit 130 includes a PMOS transistor 131 (the third MOS transistor) and an NMOS transistor 132 (the fourth transistor).
  • the source of the PMOS transistor 131 is connected to the voltage supply, its drain is connected to the output terminal 160 through a resistor 150 and its gate is connected to the gate of the NMOS transistor 122.
  • the gate of the NMOS transistor 132 is connected to the gate of the PMOS transistor 121 and its source and drain (at least one of them) are floated.
  • the PMOS transistor 131 is turned on when the low-level signal EIN is applied from the control circuit 110 to the gate of the PMOS transistor 131.
  • the supply potential supplied to the source of the PMOS transistor 131 is thus applied, through the resistor 150, to the output terminal 160.
  • the signal EIN is at the high level, the PMOS transistor 131 is turned off.
  • the NMOS transistor 132 is inoperative because its source and drain are both floated.
  • the input buffer circuit 140 is connected to the output circuit 160 through the resistor 150, so that a signal inputted through the output terminal 160 is transmitted to internal circuitry (not shown) of the semiconductor integrated circuit.
  • both the enable signal E and the input signal A are at the low level
  • both the output signals EI and EIN of the control circuit 110 are at the high level
  • the PMOS transistor 121 is turned off and the NMOS transistor 122 is turned on.
  • the signal EIN is at the high level
  • the PMOS transistor 131 is also turned off. As a result, the ground potential can be applied to the output terminal 160 through the NMOS transistor 122.
  • the enable signal E is at the high level
  • the PMOS transistor 121 and the NMOS transistor 122 are both turned off.
  • the PMOS transistor 131 is turned on since the output signal EIN is at the low level. The supply potential thus can be applied to the output terminal 160 through the PMOS transistor 131 to pull up the potential at the output terminal 160.
  • the PMOS transistor 131 is turned off when the NMOS transistor 122 is turned on. There is thus no through current that flows, via the PMOS transistor 131 and NMOS transistor 122 to the ground, so that the power consumption of the circuit can be saved.
  • the gate of the PMOS transistor 131 is connected to the gate of the NMOS transistor 122, a load applied to the gate of the NMOS transistor 122 increases. This results in the operating speed of the NMOS transistor 122 being lowered. Therefore, in FIG. 2, the gate of the inoperative NMOS transistor 132 is connected to the gate of the PMOS transistor 121 to equalize the load applied to the gate of the PMOS transistor 121 to that of the NMOS transistor 122.
  • the operating speed of the NMOS transistor 122 can be equalized to that of the PMOS transistor 121 by the connection of the inoperative NMOS transistor 132, it is possible to obtain a constant operating speed of the bidirectional buffer circuit, irrespective of whether the high- or low-level signal is outputted from the output terminal 160.
  • the NMOS transistor 132 is of course unnecessary.
  • the transistors 121 and 131 are of PMOS type and the transistors 122 and 132 are of NMOS type.
  • the former may be of NMOS type and the latter may be of PMOS type.
  • the output signals EI and EIN of the control circuit 110 will be applied to a PMOS transistor 122 and an NMOS transistor 121, respectively. This exchange of conductive types of MOS transistors can be applied to every circuit described later.
  • a circuit as shown in FIG. 3 is first formed on a semiconductor substrate by a well known manufacturing method.
  • FIG. 3 the same reference numerals have been retained for the similar composing elements shown in FIG. 2.
  • the source of a PMOS transistor 201 (the third transistor) in FIG. 3 is connected to the voltage supply (the first voltage supply), its drain is connected to the output terminal 160 and its gate is connected to the gate of the NMOS transistor 122.
  • the source of an NMOS transistor 202 (the fourth transistor) is connected to the ground (the second voltage supply), its drain is connected to the output terminal 160 and its gate is connected to the gate of the PMOS transistor 121.
  • the positions as shown by the lines A-A' and B-B' are both cut off, that is, the source of the NMOS transistor 202 is cut away from the ground and its drain is cut away from the output terminal 160, to obtain the circuit construction as shown in FIG. 2. In this case, it is also sufficient when any one of both is cut off.
  • the NMOS transistor 202 (in which the source and/or drain is floated) can be formed by simply cutting off the above-mentioned wires. Therefore, when the disconnected wire is required to be reconnected, the cut-off wiring can be connected again by use of FIB (Focused Ion Beam).
  • FIB Flucused Ion Beam
  • FIG. 4 in which a bidirectional buffer circuit having a pull-down circuit is shown.
  • a pull-down circuit 310 shown in FIG. 4 includes an NMOS transistor 311 (the third MOS transistor) and a PMOS transistor 312 (the fourth transistor).
  • the source of the NMOS transistor 311 is connected to the ground (the first voltage supply), its drain is connected to the output terminal 160 through the resistor 150 and its gate is connected to the gate of the PMOS transistor 121 (the second MOS transistor).
  • the gate of the PMOS transistor 312 is connected to the gate of the NMOS transistor 122 (the first MOS transistor) and its source and drain (at least one of them) are floated. Therefore, the NMOS transistor 311 is turned on when the high-level signal EI is applied from the control circuit 110 to the gate of the NMOS transistor 311. The ground potential is thus applied to the output terminal 160.
  • the signal EI is at the low level
  • the NMOS transistor 311 is turned off.
  • the PMOS transistor 312 is inoperative because its source and drain are both floated.
  • the enable signal E is at the low level and when the input signal A is at the high level, the output signals EI and EIN of the control circuit 110 are both at the low level.
  • the PMOS transistor 121 is turned on and the NMOS transistor 122 is turned off. Further, the NMOS transistor 311 is also turned off. As a result, the supply potential can be applied to the output terminal 160 through the PMOS transistors 121.
  • the output signals EI and EIN of the control circuit 110 are both at the high level.
  • the PMOS transistor 121 is turned off and the NMOS transistor 122 is turned on.
  • NMOS transistor 311 is turned on.
  • the ground potential can be applied to the output terminal 160 through the two turn-on NMOS transistors 122 and 311.
  • the enable signal E is at the high level
  • the output signal EI of the control circuit 110 is at the high level and its output signal EIN is at the low level.
  • the PMOS transistor 121 and the NMOS transistor 122 are both turned off.
  • the NMOS transistor 311 is turned on. This results in the ground potential being applied to the output terminal 160 through the NMOS transistor 311 to pull down the potential at the output terminal 160.
  • the gate of the NMOS transistor 311 is connected to the gate of the PMOS transistor 121, a load applied to the gate of the PMOS transistor 121 increases. This results in the operating speed of the PMOS transistor 121 being lowered.
  • the gate of the inoperative PMOS transistor 312 is connected to the gate of the NMOS transistor 122 to equalize the load applied to the gate of the PMOS transistor 121 to that of the NMOS transistor 122.
  • the operating speed of the NMOS transistor 122 can be equalized to that of the PMOS transistor 121 by the connection of the inoperative NMOS transistor 312, it is possible to obtain a constant operating speed of the bidirectional buffer circuit, irrespective of whether the high- or low-level signal is outputted from the output terminal 160.
  • the NMOS transistor 312 is of course unnecessary.
  • a circuit as shown in FIG. 3 is first formed on a semiconductor substrate. After that, in the circuit wiring shown in FIG. 3, the positions as shown by the lines C-C' and D-D' are both cut off, that is, the source of the PMOS transistor 201 (312) is cut away from the voltage supply, and its drain is cut away from the output terminal 160, to obtain the circuit construction as shown in FIG. 4. In this case, it is also sufficient when any one of both is cut off.
  • the PMOS transistor 201 in which the source and/or drain is floated
  • the PMOS transistor 201 can be formed by simply cutting off the above-mentioned wires. Therefore, when the disconnected wire is required to be reconnected, the cut-off wiring can be connected again by use of FIB (Focused Ion Beam).
  • FIB Fluorused Ion Beam
  • the gate of a PMOS transistor 401 (the third MOS transistor) is connected to the gate of the NMOS transistor 122 (the second MOS transistor) and its source and drain (at least one of them) are floated.
  • the gate of an NMOS transistor 402 (the fourth MOS transistor) is connected to the gate of the PMOS transistor 121 (the first MOS transistor) and its source and drain (at least one of them) are floated.
  • the gates of the inoperative MOS transistors 401 and 402 are connected to the gates of the MOS transistors 122 and 121, respectively, to apply only a load to the gates of the MOS transistors 122 and 121.
  • a circuit as shown in FIG. 3 is first formed on a semiconductor substrate. After that, in the circuit wiring shown in FIG. 3, the positions as shown by the lines A-A', B-B', C-C' and D-D' are all cut off, that is, the source of the PMOS transistor 202 (402) is cut away from the ground and its drain is cut away from the output terminal 160. Further, the source of the PMOS transistor 201 (401) is cut away from the voltage supply and its drain is cut away from the output terminal 160, to obtain the circuit construction as shown in FIG. 5. In this case, it is also sufficient when any one of the lines A-A' and B-B' and any one of the lines C-C' and D-D' are cut off.
  • the two MOS transistors 201 and 202 (in which the source and/or drain is floated) can be formed by simply cutting off the above-mentioned wires. Therefore, when the disconnected wires are required to be reconnected, the cut-off wiring can be connected again by use of FIB (Focused Ion Beam), in the same way as with the cases shown in FIGS. 2 and 4. In other words, it is possible to easily change the circuit shown in FIG. 5 having the MOS transistors 401 and 402 to any of the pull-up circuit as shown in FIG. 2 or the pull-down circuit as shown in FIG. 4.
  • FIB Flucused Ion Beam
  • FIG. 6 The semiconductor integrated circuit as a modified example of the first preferred embodiment of the present invention will be described hereinbelow with reference to FIG. 6, in which a bidirectional buffer circuit having a pull-up circuit is shown.
  • FIG. 6 the same reference numerals have been retained for the similar composing elements which have the same functions as with the case shown in FIG. 2.
  • control circuit 501 the construction of a control circuit 501 is the same as with the case of the first embodiment shown in FIG. 2. However, this example is different from the first embodiment in that an output signal of the NOT circuit 111 is used as a control signal C 1 .
  • the pull-up circuit is constructed by a PMOS transistor 502 (the third MOS transistor).
  • the source of the PMOS transistor 502 is connected to the voltage supply, its drain is connected to the output terminal 160 via the resistor 150 and its gate is connected to the output of the NOT circuit 111 to accept the control signal C 1 . Therefore, when the signal C 1 is at the low level, the PMOS transistor 502 is turned on, so that the supply potential supplied to its source is applied to the output terminal 160. On the other hand, when the signal C 1 is at the high level, the PMOS transistor 502 is turned off.
  • the enable signal E is at the low level and when the input signal A is at the high level, the output signals EI and EIN of the control circuit 501 are both at the low level as already described, and the signal C 1 is at the high level. Therefore, the PMOS transistor 121 is turned on and the NMOS transistor 122 is turned off. Further, the PMOS transistor 502 is also turned off. As a result, the supply potential can be applied to the output terminal 160 through the PMOS transistors 121.
  • the output signals EI, EIN and C 1 of the control circuit 501 are all at the high level.
  • the PMOS transistor 121 is turned off, the NMOS transistor 122 is turned on and the PMOS transistor 502 is turned off.
  • the ground potential can be applied to the output terminal 160 through the NMOS transistor 122.
  • the enable signal E is at the high level
  • the output signal EI of the control circuit 501 is at the high level and its output signal EIN is at the low level.
  • the PMOS transistor 121 and the NMOS transistor 122 are both turned off.
  • the NMOS transistor 502 is turned on.
  • the supply potential can be applied to the output terminal 160 through the NMOS transistor 502 to pull up the potential at the output terminal 160.
  • the PMOS transistor 502 can be kept turned off. It is thus possible to eliminate the through current, as a result it is possible to reduce the power consumption of the circuit.
  • the PMOS transistor 502 (the pull-up circuit) can be controllably turned on or off based on the control signal C 1 of the control circuit 501, no load is applied to the MOS transistor 122 of the output buffer circuit 120. This is different from the case of the first embodiment shown in FIG. 2, so that it is unnecessary to provide an additional NMOS transistor for equalization of the loads of the two MOS transistors 121 and 122 each other.
  • the integrated semiconductor circuit as a modified example of the second preferred embodiment of the present invention will be described hereinbelow with reference to FIG. 7, in which a bidirectional buffer circuit having a pull-down circuit is shown.
  • control circuit 601 the construction of a control circuit 601 is the same as with the case of the second embodiment shown in FIG. 4. However, this example is different from the second embodiment in that the enable signal E is used as an enable signal C 2 as it is.
  • the pull-down circuit is constructed by an NMOS transistor 602 (the third MOS transistor).
  • the source of the NMOS transistor 602 is connected to the ground (the first voltage supply) and its drain is connected to the output terminal 160 via the resistor 150.
  • the enable signal E is applied as the control signal C 2 to the gate of the NMOS transistor 602. Therefore, when the signal C 2 is at the high level, the NMOS transistor 602 is turned on, so that the ground potential supplied to its source is applied to the output terminal 160. On the other hand, when the signal C 2 is at the low level, the NMOS transistor 602 is turned off.
  • the enable signal E is at the low level and when the input signal A is at the high level, the output signals EI, EIN, and C 2 of the control circuit 602 are all at the low level. Therefore, the PMOS transistor 121 is turned on and the NMOS transistor 122 is turned off. Further, the NMOS transistor 602 is also turned off. As a result, the supply potential can be applied to the output terminal 160 through the PMOS transistors 121.
  • the enable signal E and the input signal A are both at the low level, the output signals EI and EIN of the control circuit 601 are at the high level, and the output signal C 2 is at the low level.
  • the PMOS transistor 121 is turned off, the NMOS transistor 122 is turned on and the NMOS transistor 602 is turned off.
  • the ground potential can be supplied to the output terminal 160 through the NMOS transistor 122.
  • the enable signal E is at the high level
  • the output signal EI of the control circuit 601 is at the high level and its output signal EIN is at the low level.
  • the PMOS transistor 121 and the NMOS transistor 122 are thus turned off.
  • the output signal C 2 is at the high level
  • the NMOS transistor 602 is turned on.
  • the ground potential can be supplied to the output terminal 160 through the NMOS transistor 602 to pull down the potential at the output terminal 160.
  • the NMOS transistor 602 can be kept turned off. It is thus possible to eliminate the through current, as a result it is possible to reduce the power consumption of the circuit.
  • the NMOS transistor 602 (the pull-down circuit) can be controllably turned on or off based on the control signal C 2 of the control circuit 601. This is different from the case of the second embodiment shown in FIG. 4. No load is thus applied to the MOS transistor 122 of the output buffer circuit 120 and hence it is unnecessary to provide an additional PMOS transistor for equalization of the loads of the two MOS transistors 121 and 122 each other.
  • the semiconductor integrated circuit has been described by taking the case of the bidirectional buffer circuit. Without being limited only thereto, however, the present invention can be of course applied to the semiconductor integrated circuit having only the output buffer circuit (having no input buffer circuit 140).

Abstract

A semiconductor integrated circuit with a buffer circuit is disclosed. The source of the first P(N)MOS transistor is connected to a voltage supply (ground), its drain being connected to an output terminal. The source of the first N(P)MOS transistor is connected to the ground (voltage supply), its drain being connected to the output terminal. The gate of the second P(N)MOS transistor is connected to the gate of the first NMOS transistor, its source being connected to the voltage supply (ground) and its drain being connected to the output terminal. The gate of the second N(P)MOS transistor is connected to the gate of the first PMOS transistor, at least one of its source and drain being floated. A controller responses to an enable signal and an input signal to apply control signals to the gates of the first PMOS and NMOS transistors. By these control signals, any one of the first PMOS and NMOS transistors is turned on based on the input signal level when the enable signal is on. Whereas both the first PMOS and NMOS transistors are turned off irrespective of the input signal level when the enable signal is off. The semiconductor integrated circuit further includes an input buffer connected the output terminal via a resistor. The input buffer applies a signal appearing at the output terminal to internal circuitry of the semiconductor integrated circuit.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a method of manufacturing the same. More specifically, the present invention relates to a semiconductor integrated circuit provided with a buffer circuit and a method of manufacturing the same semiconductor integrated circuit.
2. Description of the Prior Art
There is a conventional semiconductor integrated circuit provided with a bidirectional buffer circuit having a pull-up circuit.
FIG. 1 is a circuit diagram showing an example of such a conventional semiconductor integrated circuit. In this circuit, when an enable signal B is at a low level, a control circuit 701 outputs low-level output signals EI and EIN in response to a high-level input signal A, whereas high-level output signals EI and EIN in response to a low-level input signal A. On the other hand, when the enable signal E is at a high level, the control circuit 701 outputs a high-level output signal EI and a low-level output signal EIN, irrespective of the input signal level.
A PMOS transistor 703 and an NMOS transistor 704 constitute an output buffer circuit 702 that is connected to the control circuit 701. When the low-level output signal EI of the control circuit 701 is applied to the gate of the PMOS transistor 703, the PMOS transistor 703 is turned on, so that a supply potential supplied to the source of the transistor 703 is applied to an output terminal 707. On the other hand, when the output signal EI of the control circuit 701 is at the high level, the PMOS transistor 703 is turned off. In contrast with this, when the high-level output signal EIN of the control circuit 701 is applied to the gate of the NMOS transistor 704, the NMOS transistor 704 is turned on, so that a ground potential is applied to the output terminal 707. On the other hand, when the output signal EIN of the control circuit 701 is at the low level, the PMOS transistor 704 is turned off.
Further, in FIG. 1, a PMOS transistor 705 acts as a pull-up circuit 705. Here, since the gate of the PMOS transistor 705 is grounded, this PMOS transistor 705 is always kept turned on, so that a supply potential supplied to its source is always applied to the output terminal 707.
Further, an input buffer circuit 706 outputs a signal inputted through the output terminal 707 to internal circuitry (not shown) of the semiconductor integrated circuit.
In the above-mentioned conventional integrated circuit, when the enable signal E is at the low level and when the input signal A is at the high level, since the output signal of the output buffer 702 changes to the high level, the output terminal 707 changes also to the high potential level. Further, when the enable signal E is at the low level and when the input signal A is also at the low level, since the output signal of the output buffer 702 changes to the low level, the output terminal 707 changes also to the low potential level. On the other hand, when the enable signal E is at the high level, although the output of the output buffer 702 is not decided, since being pulled up by the PMOS transistor 705, the potential at the output terminal 707 is kept at the high level.
In the above-mentioned conventional semiconductor integrated circuit provided with the buffer circuit shown in FIG. 1, however, even when the output signal of the output buffer circuit 702 is at the low level, the PMOS transistor 705 is always kept turned on. There exists a problem in that current flows from the supply potential connected to the source of the PMOS transistor 705 to the ground through the two turn-on MOS transistors 705 and 704. This through current increases power consumption of the semiconductor integrated circuit.
SUMMARY OF THE INVENTION
With the problem in mind therefore, it is the object of the present invention to provide a semiconductor integrated circuit including a buffer circuit of low power consumption.
To achieve the above-mentioned object, the present invention provides a semiconductor integrated circuit, comprising: a first MOS transistor of a first-conductive type having a gate, a source connected to a first voltage supply and a drain connected to an output terminal; a second MOS transistor of a second-conductive type different from the first-conductive type having a gate, a source connected to a second voltage supply different from the first voltage supply in potential and a drain connected to the output terminal; a third MOS transistor of the first-conductive type having a gate connected to the gate of the second MOS transistor, a source connected to the first voltage supply and a drain connected to the output terminal; a fourth MOS transistor of the second-conductive type having a source, a drain and a gate connected to the gate of the first MOS transistor, at least one of the source and drain being floated; and means, responsive to an enable signal and an input signal, for applying control signals to the gates of the first and second MOS transistors to turn on any one of the first and second MOS transistors based on the input signal level when the enable signal is on, whereas to turn off both the first and second MOS transistors irrespective of the input signal level when the enable signal is off.
Further, the present invention provides a semiconductor integrated circuit, comprising: a first MOS transistor of a first-conductive type having a drain, a source connected to a first voltage supply and a drain connected to an output terminal; a second MOS transistor of a second-conductive type different from the first-conductive type having a gate, a source connected to a second voltage supply different from the first voltage supply in potential and a drain connected to an output terminal; a third MOS transistor of the first-conductive type having a source, a drain and a gate connected to the gate of the second MOS transistor, at least one of the source and drain being floated; a fourth MOS transistor of the second-conductive type having a source, a drain and a gate connected to a gate of the first MOS transistor, at least one of the source and drain being floated; and means, responsive to an enable signal and an input signal, for applying control signals to the gates of the first and second MOS transistors to turn on any one of the first and second MOS transistors based on the input signal level when the enable signal is on, whereas to turn off both the first and second MOS transistors irrespective of the input signal level when the enable signal is off.
The semiconductor integrated circuits may further include means for applying a signal appearing at the output terminal to their internal circuitry. In the semiconductor integrated circuits, the first and third transistors may be PMOS transistors and the second and fourth transistors may be NMOS transistors.
Further, the present invention provides a method of manufacturing a semiconductor integrated circuit including a first MOS transistor of a first-conductive type having a gate, a source connected to a first voltage supply and a drain connected to an output terminal, a second MOS transistor of a second-conductive type different from the first-conductive type having a gate, a source connected to a second voltage supply different from the first voltage supply in potential and a drain connected to the output terminal, a third MOS transistor of the first-conductive type having a gate connected to the gate of the second MOS transistor, a source connected to the first voltage supply and a drain connected to the output terminal and a fourth MOS transistor of the second-conductive type having a source connected to the second voltage supply, a drain connected to the output terminal and a gate connected to the gate of the first MOS transistor, the method comprising the step of: cutting off at least one of wiring connected between the source of the third MOS transistor and the first voltage supply, wiring connected between the drain of the third MOS transistor and the output terminal, wiring connected between the source of the fourth MOS transistor and the second voltage supply, and wiring connected between the drain of the fourth MOS transistor and the output terminal.
Further, the present invention provides a semiconductor integrated circuit, comprising: a first PMOS transistor having a gate, a source connected to a voltage supply and a drain connected to an output terminal; a first NMOS transistor having a gate, a source connected to a ground and a drain connected to the output terminal; a second PMOS transistor having a gate connected to the gate of the first NMOS transistor, a source connected to the voltage supply and a drain connected to the output terminal via a resistor; a second NMOS transistor having a source, a drain and a gate connected to the gate of the first PMOS transistor, at least one of the source and drain being floated; a NAND gate having one input accepting an input signal and an output connected to the gate of the first PMOS transistor; a NOR gate having one input connected to the one input of the NAND gate, an another input accepting an enable signal and an output connected to the gate of the first NMOS transistor; and an inverter having an input connected to the other input of the NOR gate and an output connected to an another input of the NAND gate, wherein any one of the first PMOS and NMOS transistors is turned on based on the input signal level when the enable signal is substantially at the ground level, whereas the first PMOS and NMOS transistors are both turned off irrespective of the input signal level when the enable signal is substantially at the supply voltage level.
The semiconductor integrated circuit with the floating second NMOS transistor may further include an input buffer connected to the drain of the second PMOS transistor, for applying a signal appearing at the output terminal to the internal circuitry.
Further, the present invention provides a semiconductor integrated circuit, comprising: a first PMOS transistor having a gate, a source connected to a voltage supply and a drain connected to an output terminal; a first NMOS transistor having a gate, a source connected to a ground and a drain connected to the output terminal; a second PMOS transistor having a source, a drain and a gate connected to the gate of the first NMOS transistor, at least one of the source and drain being floated; a second NMOS transistor having a gate connected to the gate of the first PMOS transistor, a source connected to the ground and a drain connected to the output terminal via a resistor; a NAND gate having one input accepting an input signal and an output connected to the gate of the first PMOS transistor; a NOR gate having one input connected to the one input of the NAND gate, an another input accepting an enable signal and an output connected to the gate of the first NMOS transistor; and an inverter having an input connected to the other input of the NOR gate and an output connected to the an another input of the NAND gate, wherein any one of the first PMOS and NMOS transistors is turned on based on the input signal level when the enable signal is substantially at the ground level, whereas the first PMOS and NMOS transistors are both turned off irrespective of the input signal level when the enable signal is substantially at the supply voltage level.
The semiconductor integrated circuit with the floating second PMOS transistor may further include an input buffer connected to the drain of the second NMOS transistor, for applying a signal appearing at the output terminal to the internal circuitry.
Further, the present invention provides a semiconductor integrated circuit, comprising: a first PMOS transistor having a gate, a source connected to a voltage supply and a drain connected to an output terminal; a first NMOS transistor having a gate, a source connected to a ground and a drain connected to the output terminal; a second PMOS transistor having a source, a drain and a gate connected to the gate of the first NMOS transistor, at least one of the source and drain being floated; a second NMOS transistor having a source, a drain and a gate connected to the gate of the first PMOS transistor, at least one of the source and drain being floated; a NAND gate having one input accepting an input signal and an output connected to the gate of the first PMOS transistor; a NOR gate having one input connected to the one input of the NAND gate, an another input accepting an enable signal and an output connected to the gate of the first NMOS transistor; and an inverter having an input connected to the other input of the NOR gate and an output connected to an another input of the NAND gate, wherein any one of the first PMOS and NMOS transistors is turned on based on the input signal level when the enable signal is substantially at the ground level, whereas the first PMOS and NMOS transistors are both turned off irrespective of the input signal level when the enable signal is substantially at the supply voltage level.
The semiconductor integrated circuit with the floating second PMOS and NMOS transistors may further include an input buffer connected to the output terminal via a resistor, for applying a signal appearing at the output terminal to internal circuitry of the semiconductor integrated circuit.
Further, the present invention provides a semiconductor integrated circuit, comprising: a first PMOS transistor having a gate, a source connected to a voltage supply and a drain connected to an output terminal; a first NMOS transistor having a gate, a source connected to a ground and a drain connected to the output terminal; a NAND gate having one input accepting an input signal and an output connected to the gate of the first PMOS transistor; a NOR gate having one input connected to the one input of the NAND gate, an another input accepting an enable signal and an output connected to the gate of the first NMOS transistor; an inverter having an input connected to the other input of the NOR gate and an output connected to an another input of the NAND gate; and a second NMOS transistor having a gate connected to the input of the inverter, a drain connected to the output terminal via a resistor and a source connected to the ground, wherein any one of the first PMOS and NMOS transistors is turned on based on the input signal level when the enable signal is substantially at the ground level, whereas the first PMOS and NMOS transistors are both turned off irrespective of the input signal level when the enable signal is substantially at the supply voltage level.
The semiconductor integrated circuit with no floating transistor may further include an input buffer connected to the drain of the second NMOS transistor, for applying a signal appearing at the output terminal to internal circuitry of the semiconductor integrated circuit.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram showing an example of conventional semiconductor integrated circuit provided with a bidirectional buffer circuit having a pull-up circuit;
FIG. 2 is a circuit diagram showing the first preferred embodiment of the semiconductor integrated circuit according to the present invention, in which the bidirectional buffer circuit has a pull-up circuit;
FIG. 3 is a circuit diagram for assistance in explaining the manufacturing method of the first embodiment of the semiconductor integrated circuit shown in FIG. 2, in which the state where the wiring is not yet cut off is shown;
FIG. 4 is a circuit diagram showing the second preferred embodiment of the semiconductor integrated circuit according to the present invention, in which the bidirectional buffer circuit has a pull-down circuit;
FIG. 5 is a circuit diagram showing the third preferred embodiment of the semiconductor integrated circuit according to the present invention, in which the bidirectional buffer circuit has no pull-up and pull-down circuit;
FIG. 6 is a circuit diagram showing a modified example embodiment of the semiconductor integrated circuit shown in FIG. 2; and
FIG. 7 is a circuit diagram showing a modified example of the semiconductor integrated circuit shown in FIG. 4.
DETAILED DESCRIPTION OF THE EMBODIMENTS
The preferred embodiments of the semiconductor integrated circuit according to the present invention will be described hereinbelow with reference to the attached drawings.
The first preferred embodiment of the present invention will be described hereinbelow with reference to FIG. 2, in which a bidirectional buffer circuit having a pull-up circuit is shown.
In FIG. 2, the circuit includes a control circuit 110, an output buffer circuit 120, a pull-up circuit 130, and an input buffer circuit 140. The control circuit 110 includes a NOT (inverter) circuit 111, a NAND circuit 112 and a NOR circuit 113. The NAND circuit 112 accepts a signal/E obtained by inverting an enable signal E through the NOT circuit 111 and a signal A, and outputs an inverted control signal EI of a logical product of both the signals/E and A. Further, the NOR circuit 113 accepts the enable signal E and the signal A, and outputs an inverted control signal EIN of a logical sum of both the signals E and A. Therefore, when the enable signal E is at the low level, the control circuit 110 outputs low-level output signals EI and EIN in response to the high-level input signal A, whereas high-level output signals EI and EIN in response to the low-level input signal A. On the other hand, when the enable signal E is at the high level, the control circuit 110 outputs a high-level output signal EI and a low-level output signal EIN, irrespective of the level of the input signal A.
The output buffer circuit 120 includes a PMOS transistor 121 (the first MOS transistor) and an NMOS transistor 122 (the second MOS transistor). The source of the PMOS transistor 121 is connected to a voltage supply (the first voltage supply) and its drain is connected to an output terminal 160. The signal EI is inputted from the control circuit 110 to the gate of the PMOS transistor 121. Further, the source of the NMOS transistor 122 is connected to a ground voltage (the second voltage supply) and its drain is connected to the output terminal 160. The signal EIN is inputted from the control circuit 110 to the gate of the NMOS transistor 122. The PMOS transistor 121 is turned on when the low-level signal EI is applied from the control circuit 110 to the gate of the PMOS transistor 121. The supply potential supplied to the source of the PMOS transistor 121 is thus applied to the output terminal 160. On the other hand, when the signal EI is at the high level, the PMOS transistor 121 is turned off. The NMOS transistor 122 is turned on when the high-level signal EIN is applied from the control circuit 110 to the gate of the NMOS transistor 122. The ground potential is thus applied to the output terminal 160. On the other hand, when the signal EIN is at the low level, the NMOS transistor 122 is turned off.
The pull-up circuit 130 includes a PMOS transistor 131 (the third MOS transistor) and an NMOS transistor 132 (the fourth transistor). The source of the PMOS transistor 131 is connected to the voltage supply, its drain is connected to the output terminal 160 through a resistor 150 and its gate is connected to the gate of the NMOS transistor 122. Further, the gate of the NMOS transistor 132 is connected to the gate of the PMOS transistor 121 and its source and drain (at least one of them) are floated. The PMOS transistor 131 is turned on when the low-level signal EIN is applied from the control circuit 110 to the gate of the PMOS transistor 131. The supply potential supplied to the source of the PMOS transistor 131 is thus applied, through the resistor 150, to the output terminal 160. On the other hand, when the signal EIN is at the high level, the PMOS transistor 131 is turned off. The NMOS transistor 132 is inoperative because its source and drain are both floated.
The input buffer circuit 140 is connected to the output circuit 160 through the resistor 150, so that a signal inputted through the output terminal 160 is transmitted to internal circuitry (not shown) of the semiconductor integrated circuit.
The operation of the bidirectional buffer circuit having a pull-up circuit shown in FIG. 2 will be described hereinbelow.
When the enable signal E is at the low level and when the input signal A is at the high level, since both the output signals EI and EIN of the control circuit 110 are at the low level as already described, the PMOS transistor 121 is turned on and the NMOS transistor 122 is turned off. Further, since the signal EIN is at the low level, the PMOS transistor 131 is also turned on. As a result, the supply potential can be applied to the output terminal 160 through the two PMOS transistors 121 and 131.
Further, when both the enable signal E and the input signal A are at the low level, since both the output signals EI and EIN of the control circuit 110 are at the high level, the PMOS transistor 121 is turned off and the NMOS transistor 122 is turned on. Further, since the signal EIN is at the high level, the PMOS transistor 131 is also turned off. As a result, the ground potential can be applied to the output terminal 160 through the NMOS transistor 122.
Further, when the enable signal E is at the high level, since the output signal EIN of the control circuit 110 is at the low level, the PMOS transistor 121 and the NMOS transistor 122 are both turned off. On the other hand, the PMOS transistor 131 is turned on since the output signal EIN is at the low level. The supply potential thus can be applied to the output terminal 160 through the PMOS transistor 131 to pull up the potential at the output terminal 160.
As described above, in the bidirectional buffer circuit having the pull-up circuit shown in FIG. 2, the PMOS transistor 131 is turned off when the NMOS transistor 122 is turned on. There is thus no through current that flows, via the PMOS transistor 131 and NMOS transistor 122 to the ground, so that the power consumption of the circuit can be saved.
In the bidirectional buffer circuit having the pull-up circuit as shown in FIG. 2, since the gate of the PMOS transistor 131 is connected to the gate of the NMOS transistor 122, a load applied to the gate of the NMOS transistor 122 increases. This results in the operating speed of the NMOS transistor 122 being lowered. Therefore, in FIG. 2, the gate of the inoperative NMOS transistor 132 is connected to the gate of the PMOS transistor 121 to equalize the load applied to the gate of the PMOS transistor 121 to that of the NMOS transistor 122. In other words, since the operating speed of the NMOS transistor 122 can be equalized to that of the PMOS transistor 121 by the connection of the inoperative NMOS transistor 132, it is possible to obtain a constant operating speed of the bidirectional buffer circuit, irrespective of whether the high- or low-level signal is outputted from the output terminal 160. However, when it is unnecessary to equalize the operating speed of the bidirectional buffer circuit for both the high- and low-level signals, the NMOS transistor 132 is of course unnecessary.
In FIG. 2, the transistors 121 and 131 are of PMOS type and the transistors 122 and 132 are of NMOS type. However, the former may be of NMOS type and the latter may be of PMOS type. In this case, the output signals EI and EIN of the control circuit 110 will be applied to a PMOS transistor 122 and an NMOS transistor 121, respectively. This exchange of conductive types of MOS transistors can be applied to every circuit described later.
The method of manufacturing the bidirectional buffer circuit having the pull-up circuit shown in FIG. 2 will be described hereinbelow. To manufacture the bidirectional buffer circuit having the pull-up circuit, a circuit as shown in FIG. 3 is first formed on a semiconductor substrate by a well known manufacturing method.
In FIG. 3, the same reference numerals have been retained for the similar composing elements shown in FIG. 2. The source of a PMOS transistor 201 (the third transistor) in FIG. 3 is connected to the voltage supply (the first voltage supply), its drain is connected to the output terminal 160 and its gate is connected to the gate of the NMOS transistor 122. Further, the source of an NMOS transistor 202 (the fourth transistor) is connected to the ground (the second voltage supply), its drain is connected to the output terminal 160 and its gate is connected to the gate of the PMOS transistor 121.
In the circuit wiring shown in FIG. 3, the positions as shown by the lines A-A' and B-B' are both cut off, that is, the source of the NMOS transistor 202 is cut away from the ground and its drain is cut away from the output terminal 160, to obtain the circuit construction as shown in FIG. 2. In this case, it is also sufficient when any one of both is cut off.
As described above, after the wiring of the source and drain of the NMOS transistor 202 has been completed, the NMOS transistor 202 (in which the source and/or drain is floated) can be formed by simply cutting off the above-mentioned wires. Therefore, when the disconnected wire is required to be reconnected, the cut-off wiring can be connected again by use of FIB (Focused Ion Beam). In other words, it is possible to easily change the pull-up circuit 130 shown in FIG. 2 to a pull-down circuit (described later in further detail with reference to FIG. 4). As a result, whenever the pull-up circuit 130 is required to be changed to the pull-down circuit, it is unnecessary to manufacture the semiconductor integrated circuit with the pull-down circuit from the beginning, so that the manufacturing cost of the semiconductor integrated circuit can be reduced.
The second preferred embodiment of the present invention will be described hereinbelow with reference to FIG. 4, in which a bidirectional buffer circuit having a pull-down circuit is shown.
In FIG. 4, the same reference numerals have been retained for the similar composing elements which have the same functions as with the case shown in FIG. 2.
A pull-down circuit 310 shown in FIG. 4 includes an NMOS transistor 311 (the third MOS transistor) and a PMOS transistor 312 (the fourth transistor). The source of the NMOS transistor 311 is connected to the ground (the first voltage supply), its drain is connected to the output terminal 160 through the resistor 150 and its gate is connected to the gate of the PMOS transistor 121 (the second MOS transistor). Further, the gate of the PMOS transistor 312 is connected to the gate of the NMOS transistor 122 (the first MOS transistor) and its source and drain (at least one of them) are floated. Therefore, the NMOS transistor 311 is turned on when the high-level signal EI is applied from the control circuit 110 to the gate of the NMOS transistor 311. The ground potential is thus applied to the output terminal 160. On the other hand, when the signal EI is at the low level, the NMOS transistor 311 is turned off. The PMOS transistor 312 is inoperative because its source and drain are both floated.
The operation of the bidirectional buffer circuit shown in FIG. 4 will be described hereinbelow.
When the enable signal E is at the low level and when the input signal A is at the high level, the output signals EI and EIN of the control circuit 110 are both at the low level. Thus, the PMOS transistor 121 is turned on and the NMOS transistor 122 is turned off. Further, the NMOS transistor 311 is also turned off. As a result, the supply potential can be applied to the output terminal 160 through the PMOS transistors 121.
Further, when both the enable signal E and the input signal A are at the low level, the output signals EI and EIN of the control circuit 110 are both at the high level. Thus, the PMOS transistor 121 is turned off and the NMOS transistor 122 is turned on. Further, NMOS transistor 311 is turned on. As a result, the ground potential can be applied to the output terminal 160 through the two turn-on NMOS transistors 122 and 311.
Further, when the enable signal E is at the high level, the output signal EI of the control circuit 110 is at the high level and its output signal EIN is at the low level. Thus, the PMOS transistor 121 and the NMOS transistor 122 are both turned off. On the other hand, since the output signal EI is at the low level, the NMOS transistor 311 is turned on. This results in the ground potential being applied to the output terminal 160 through the NMOS transistor 311 to pull down the potential at the output terminal 160.
As described above, in the bidirectional buffer circuit having the pull-down circuit shown in FIG. 4, when the PMOS transistor 121 is turned on, the NMOS transistor 131 can be turned off. Thus, there is no through current that flows via the NMOS transistor 311 and the NMOS transistor 122 to the ground. Consequently, the circuit power consumption can be reduced.
Further, in the same way as with the circuit shown in FIG. 2, since the gate of the NMOS transistor 311 is connected to the gate of the PMOS transistor 121, a load applied to the gate of the PMOS transistor 121 increases. This results in the operating speed of the PMOS transistor 121 being lowered. However, as shown in FIG. 4, the gate of the inoperative PMOS transistor 312 is connected to the gate of the NMOS transistor 122 to equalize the load applied to the gate of the PMOS transistor 121 to that of the NMOS transistor 122. In other words, since the operating speed of the NMOS transistor 122 can be equalized to that of the PMOS transistor 121 by the connection of the inoperative NMOS transistor 312, it is possible to obtain a constant operating speed of the bidirectional buffer circuit, irrespective of whether the high- or low-level signal is outputted from the output terminal 160. However, when it is unnecessary to equalize the operating speed of the bidirectional buffer circuit for both the high- and low-level signal, the NMOS transistor 312 is of course unnecessary.
When the bidirectional buffer circuit having the pull-down circuit as shown in FIG. 4 is manufactured, a circuit as shown in FIG. 3 is first formed on a semiconductor substrate. After that, in the circuit wiring shown in FIG. 3, the positions as shown by the lines C-C' and D-D' are both cut off, that is, the source of the PMOS transistor 201 (312) is cut away from the voltage supply, and its drain is cut away from the output terminal 160, to obtain the circuit construction as shown in FIG. 4. In this case, it is also sufficient when any one of both is cut off.
As described above, in the second preferred embodiment, after the wiring of the source and the drain of the PMOS transistor 201 (312) has been completed, the PMOS transistor 201 (in which the source and/or drain is floated) can be formed by simply cutting off the above-mentioned wires. Therefore, when the disconnected wire is required to be reconnected, the cut-off wiring can be connected again by use of FIB (Focused Ion Beam). In other words, it is possible to easily change the pull-down circuit 310 to the pull-up circuit. As a result, whenever the pull-down circuit 310 is required to be changed to the pull-up circuit, it is unnecessary to manufacture the semiconductor integrated circuit with the pull-down circuit from the beginning, so that the manufacturing cost of the semiconductor integrated circuit can be reduced.
The third preferred embodiment of the present invention will be described hereinbelow with reference to FIG. 5, in which a bidirectional buffer circuit having no pull-up and pull-down circuits is shown.
In FIG. 5, the same reference numerals have been retained for the similar composing elements which have the same functions as with the case shown in FIG. 2.
In FIG. 5, the gate of a PMOS transistor 401 (the third MOS transistor) is connected to the gate of the NMOS transistor 122 (the second MOS transistor) and its source and drain (at least one of them) are floated. Further, the gate of an NMOS transistor 402 (the fourth MOS transistor) is connected to the gate of the PMOS transistor 121 (the first MOS transistor) and its source and drain (at least one of them) are floated.
As described above, in the bidirectional circuit having no pull-up and pull-down circuits shown in FIG. 5, the gates of the inoperative MOS transistors 401 and 402 are connected to the gates of the MOS transistors 122 and 121, respectively, to apply only a load to the gates of the MOS transistors 122 and 121. As a result, it is possible to equalize the operating speed of the bidirectional buffer circuit shown in FIG. 5 to that of the bidirectional buffer circuit having the pull-up circuit (shown in FIG. 2) or the pull-down circuit (shown in FIG. 4).
When the bidirectional buffer circuit shown in FIG. 5 is manufactured, a circuit as shown in FIG. 3 is first formed on a semiconductor substrate. After that, in the circuit wiring shown in FIG. 3, the positions as shown by the lines A-A', B-B', C-C' and D-D' are all cut off, that is, the source of the PMOS transistor 202 (402) is cut away from the ground and its drain is cut away from the output terminal 160. Further, the source of the PMOS transistor 201 (401) is cut away from the voltage supply and its drain is cut away from the output terminal 160, to obtain the circuit construction as shown in FIG. 5. In this case, it is also sufficient when any one of the lines A-A' and B-B' and any one of the lines C-C' and D-D' are cut off.
As described above, after the wiring of the sources and the drains of the two MOS transistors 201 and 202 have been completed, the two MOS transistors 201 and 202 (in which the source and/or drain is floated) can be formed by simply cutting off the above-mentioned wires. Therefore, when the disconnected wires are required to be reconnected, the cut-off wiring can be connected again by use of FIB (Focused Ion Beam), in the same way as with the cases shown in FIGS. 2 and 4. In other words, it is possible to easily change the circuit shown in FIG. 5 having the MOS transistors 401 and 402 to any of the pull-up circuit as shown in FIG. 2 or the pull-down circuit as shown in FIG. 4. As a result, whenever the bidirectional circuit having no pull-up and pull-down circuits is required to be changed to the bidirectional buffer circuit having a pull-up or pull-down circuit, it is unnecessary to manufacture the semiconductor integrated circuit from the beginning, so that the manufacturing cost of the semiconductor integrated circuit can be reduced.
As described above, also in the third embodiment according to the present invention, it is possible to provide a semiconductor integrated circuit which is small in the power consumption, constant in the operating speed, and low in manufacturing cost.
The semiconductor integrated circuit as a modified example of the first preferred embodiment of the present invention will be described hereinbelow with reference to FIG. 6, in which a bidirectional buffer circuit having a pull-up circuit is shown.
In FIG. 6, the same reference numerals have been retained for the similar composing elements which have the same functions as with the case shown in FIG. 2.
In this example, the construction of a control circuit 501 is the same as with the case of the first embodiment shown in FIG. 2. However, this example is different from the first embodiment in that an output signal of the NOT circuit 111 is used as a control signal C1.
In FIG. 6, the pull-up circuit is constructed by a PMOS transistor 502 (the third MOS transistor). The source of the PMOS transistor 502 is connected to the voltage supply, its drain is connected to the output terminal 160 via the resistor 150 and its gate is connected to the output of the NOT circuit 111 to accept the control signal C1. Therefore, when the signal C1 is at the low level, the PMOS transistor 502 is turned on, so that the supply potential supplied to its source is applied to the output terminal 160. On the other hand, when the signal C1 is at the high level, the PMOS transistor 502 is turned off.
The operation of the bidirectional buffer circuit having the pull-up circuit shown in FIG. 6 will be described hereinbelow.
When the enable signal E is at the low level and when the input signal A is at the high level, the output signals EI and EIN of the control circuit 501 are both at the low level as already described, and the signal C1 is at the high level. Therefore, the PMOS transistor 121 is turned on and the NMOS transistor 122 is turned off. Further, the PMOS transistor 502 is also turned off. As a result, the supply potential can be applied to the output terminal 160 through the PMOS transistors 121.
Further, when both the enable signal E and the input signal A are at the low level, the output signals EI, EIN and C1 of the control circuit 501 are all at the high level. Thus, the PMOS transistor 121 is turned off, the NMOS transistor 122 is turned on and the PMOS transistor 502 is turned off. As a result, the ground potential can be applied to the output terminal 160 through the NMOS transistor 122.
Further, when the enable signal E is at the high level, the output signal EI of the control circuit 501 is at the high level and its output signal EIN is at the low level. Thus, the PMOS transistor 121 and the NMOS transistor 122 are both turned off. On the other hand, since the output signal C1 is at the low level, the NMOS transistor 502 is turned on. Thus, the supply potential can be applied to the output terminal 160 through the NMOS transistor 502 to pull up the potential at the output terminal 160.
As described above, in the bidirectional buffer circuit having the pull-up circuit shown in FIG. 6, when the NMOS transistor 122 is turned on, the PMOS transistor 502 can be kept turned off. It is thus possible to eliminate the through current, as a result it is possible to reduce the power consumption of the circuit.
Further, in the bidirection buffer circuit having the pull-up circuit shown in FIG. 6, since the PMOS transistor 502 (the pull-up circuit) can be controllably turned on or off based on the control signal C1 of the control circuit 501, no load is applied to the MOS transistor 122 of the output buffer circuit 120. This is different from the case of the first embodiment shown in FIG. 2, so that it is unnecessary to provide an additional NMOS transistor for equalization of the loads of the two MOS transistors 121 and 122 each other.
The integrated semiconductor circuit as a modified example of the second preferred embodiment of the present invention will be described hereinbelow with reference to FIG. 7, in which a bidirectional buffer circuit having a pull-down circuit is shown.
In FIG. 7, the same reference numerals have been retained for the similar composing elements which have the same functions as with the case shown in FIG. 4.
In this example, the construction of a control circuit 601 is the same as with the case of the second embodiment shown in FIG. 4. However, this example is different from the second embodiment in that the enable signal E is used as an enable signal C2 as it is.
Further, in FIG. 7, the pull-down circuit is constructed by an NMOS transistor 602 (the third MOS transistor). The source of the NMOS transistor 602 is connected to the ground (the first voltage supply) and its drain is connected to the output terminal 160 via the resistor 150. The enable signal E is applied as the control signal C2 to the gate of the NMOS transistor 602. Therefore, when the signal C2 is at the high level, the NMOS transistor 602 is turned on, so that the ground potential supplied to its source is applied to the output terminal 160. On the other hand, when the signal C2 is at the low level, the NMOS transistor 602 is turned off.
The operation of the bidirectional buffer circuit having the pull-down circuit shown in FIG. 7 will be described hereinbelow.
When the enable signal E is at the low level and when the input signal A is at the high level, the output signals EI, EIN, and C2 of the control circuit 602 are all at the low level. Therefore, the PMOS transistor 121 is turned on and the NMOS transistor 122 is turned off. Further, the NMOS transistor 602 is also turned off. As a result, the supply potential can be applied to the output terminal 160 through the PMOS transistors 121.
Further, when the enable signal E and the input signal A are both at the low level, the output signals EI and EIN of the control circuit 601 are at the high level, and the output signal C2 is at the low level. Thus, the PMOS transistor 121 is turned off, the NMOS transistor 122 is turned on and the NMOS transistor 602 is turned off. As a result, the ground potential can be supplied to the output terminal 160 through the NMOS transistor 122.
Further, when the enable signal E is at the high level, since the output signal EI of the control circuit 601 is at the high level and its output signal EIN is at the low level. The PMOS transistor 121 and the NMOS transistor 122 are thus turned off. On the other hand, since the output signal C2 is at the high level, the NMOS transistor 602 is turned on. Thus, the ground potential can be supplied to the output terminal 160 through the NMOS transistor 602 to pull down the potential at the output terminal 160.
As described above, in the bidirectional buffer circuit having the pull-down circuit shown in FIG. 7, when the PMOS transistor 121 is turned on, the NMOS transistor 602 can be kept turned off. It is thus possible to eliminate the through current, as a result it is possible to reduce the power consumption of the circuit.
Further, in this bidirectional buffer circuit having the pull-down circuit shown in FIG. 7, the NMOS transistor 602 (the pull-down circuit) can be controllably turned on or off based on the control signal C2 of the control circuit 601. This is different from the case of the second embodiment shown in FIG. 4. No load is thus applied to the MOS transistor 122 of the output buffer circuit 120 and hence it is unnecessary to provide an additional PMOS transistor for equalization of the loads of the two MOS transistors 121 and 122 each other.
As described above, also in this modified example, it is possible to provide a semiconductor integrated circuit, which is small in the power consumption, constant in the operating speed, and low in the manufacturing cost.
Further, in the above-mentioned embodiments, the semiconductor integrated circuit has been described by taking the case of the bidirectional buffer circuit. Without being limited only thereto, however, the present invention can be of course applied to the semiconductor integrated circuit having only the output buffer circuit (having no input buffer circuit 140).

Claims (13)

What is claimed is:
1. A semiconductor integrated circuit, comprising:
a first MOS transistor of a first-conductive type having a gate, a source connected to a first voltage supply and a drain connected to an output terminal;
a second MOS transistor of a second-conductive type different from the first-conductive type having a gate, a source connected to a second voltage supply different from the first voltage supply in potential and a drain connected to the output terminal;
a third MOS transistor of the first-conductive type having a gate connected to the gate of the second MOS transistor, a source connected to the first voltage supply and a drain connected to the output terminal;
a fourth MOS transistor of the second-conductive type having a source, a drain and a gate connected to the gate of the first MOS transistor, at least one of the source and drain being floated; and
means, responsive to an enable signal and an input signal, for applying control signals to the gates of the first and second MOS transistors to turn on any one of the first and second MOS transistors based on the input signal level when the enable signal is on, whereas to turn off both the first and second MOS transistors irrespective of the input signal level when the enable signal is off.
2. The semiconductor integrated circuit of claim 1 further comprising means for applying a signal appearing at the output terminal to internal circuitry of the semiconductor integrated circuit.
3. The semiconductor integrated circuit of claim 1, the first and third MOS transistors are PMOS transistors and the second and fourth MOS transistors are NMOS transistors.
4. A semiconductor integrated circuit, comprising:
a first MOS transistor of a first-conductive type having a drain, a source connected to a first voltage supply and a drain connected to an output terminal;
a second MOS transistor of a second-conductive type different from the first-conductive type having a gate, a source connected to a second voltage supply different from the first voltage supply in potential and a drain connected to an output terminal;
a third MOS transistor of the first-conductive type having a source, a drain and a gate connected to the gate of the second MOS transistor, at least one of the source and drain being floated;
a fourth MOS transistor of the second-conductive type having a source, a drain and a gate connected to a gate of the first MOS transistor, at least one of the source and drain being floated; and
means, responsive to an enable signal and an input signal, for applying control signals to the gates of the first and second MOS transistors to turn on any one of the first and second MOS transistors based on the input signal level when the enable signal is on, whereas to turn off both the first and second MOS transistors irrespective of the input signal level when the enable signal is off.
5. The semiconductor integrated circuit of claim 4 further comprising means for applying a signal appearing at the output terminal to internal circuitry of the semiconductor integrated circuit.
6. The semiconductor integrated circuit of claim 4, the first and third MOS transistors are PMOS transistors and the second and fourth MOS transistors are NMOS transistors.
7. A method of manufacturing a semiconductor integrated circuit including a first MOS transistor of a first-conductive type having a gate, a source connected to a first voltage supply and a drain connected to an output terminal, a second MOS transistor of a second-conductive type different from the first-conductive type having a gate, a source connected to a second voltage supply different from the first voltage supply in potential and a drain connected to the output terminal, a third MOS transistor of the first-conductive type having a gate connected to the gate of the second MOS transistor, a source connected to the first voltage supply and a drain connected to the output terminal and a fourth MOS transistor of the second-conductive type having a source connected to the second voltage supply, a drain connected to the output terminal and a gate connected to the gate of the first MOS transistor, the method comprising the step of:
cutting off at least one of wiring connected between the source of the third MOS transistor and the first voltage supply, wiring connected between the drain of the third MOS transistor and the output terminal, wiring connected between the source of the fourth MOS transistor and the second voltage supply, and wiring connected between the drain of the fourth MOS transistor and the output terminal.
8. A semiconductor integrated circuit, comprising:
a first PMOS transistor having a gate, a source connected to a voltage supply and a drain connected to an output terminal;
a first NMOS transistor having a gate, a source connected to a ground and a drain connected to the output terminal;
a second PMOS transistor having a gate connected to the gate of the first NMOS transistor, a source connected to the voltage supply and a drain connected to the output terminal via a resistor;
a second NMOS transistor having a source, a drain and a gate connected to the gate of the first PMOS transistor, at least one of the source and drain being floated;
a NAND gate having one input accepting an input signal and an output connected to the gate of the first PMOS transistor;
a NOR gate having one input connected to the one input of the NAND gate, an another input accepting an enable signal and an output connected to the gate of the first NMOS transistor; and
an inverter having an input connected to the other input of the NOR gate and an output connected to an another input of the NAND gate,
wherein any one of the first PMOS and NMOS transistors is turned on based on the input signal level when the enable signal is substantially at the ground level, whereas the first PMOS and NMOS transistors are both turned off irrespective of the input signal level when the enable signal is substantially at the supply voltage level.
9. The semiconductor integrated circuit of claim 4 further comprising an input buffer connected to the drain of the second PMOS transistor, for applying a signal appearing at the output terminal to internal circuitry of the semiconductor integrated circuit.
10. A semiconductor integrated circuit, comprising:
a first PMOS transistor having a gate, a source connected to a voltage supply and a drain connected to an output terminal;
a first NMOS transistor having a gate, a source connected to a ground and a drain connected to the output terminal;
a second PMOS transistor having a source, a drain and a gate connected to the gate of the first NMOS transistor, at least one of the source and drain being floated;
a second NMOS transistor having a gate connected to the gate of the first PMOS transistor, a source connected to the ground and a drain connected to the output terminal via a resistor;
a NAND gate having one input accepting an input signal and an output connected to the gate of the first PMOS transistor;
a NOR gate having one input connected to the one input of the NAND gate, an another input accepting an enable signal and an output connected to the gate of the first NMOS transistor; and
an inverter having an input connected to the other input of the NOR gate and an output connected to the an another input of the NAND gate,
wherein any one of the first PMOS and NMOS transistors is turned on based on the input signal level when the enable signal is substantially at the ground level, whereas the first PMOS and NMOS transistors are both turned off irrespective of the input signal level when the enable signal is substantially at the supply voltage level.
11. The semiconductor integrated circuit of claim 10 further comprising an input buffer connected to the drain of the second NMOS transistor, for applying a signal appearing at the output terminal to internal circuitry of the semiconductor integrated circuit.
12. A semiconductor integrated circuit, comprising:
a first PMOS transistor having a gate, a source connected to a voltage supply and a drain connected to an output terminal;
a first NMOS transistor having a gate, a source connected to a ground and a drain connected to the output terminal;
a second PMOS transistor having a source, a drain and a gate connected to the gate of the first NMOS transistor, at least one of the source and drain being floated;
a second NMOS transistor having a source, a drain and a gate connected to the gate of the first PMOS transistor, at least one of the source and drain being floated;
a NAND gate having one input accepting an input signal and an output connected to the gate of the first PMOS transistor;
a NOR gate having one input connected to the one input of the NAND gate, an another input accepting an enable signal and an output connected to the gate of the first NMOS transistor; and
an inverter having an input connected to the other input of the NOR gate and an output connected to an another input of the NAND gate,
wherein any one of the first PMOS and NMOS transistors is turned on based on the input signal level when the enable signal is substantially at the ground level, whereas the first PMOS and NMOS transistors are both turned off irrespective of the input signal level when the enable signal is substantially at the supply voltage level.
13. The semiconductor integrated circuit of claim 12 further comprising an input buffer connected to the output terminal via a resistor, for applying a signal appearing at the output terminal to internal circuitry of the semiconductor integrated circuit.
US08/522,962 1994-09-02 1995-09-01 Semiconductor integrated circuit with buffer circuit and manufacturing method thereof Expired - Lifetime US5614842A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP6210109A JPH0879047A (en) 1994-09-02 1994-09-02 Semiconductor integrated circuit and its manufacture
JP6-210109 1994-09-02

Publications (1)

Publication Number Publication Date
US5614842A true US5614842A (en) 1997-03-25

Family

ID=16583964

Family Applications (1)

Application Number Title Priority Date Filing Date
US08/522,962 Expired - Lifetime US5614842A (en) 1994-09-02 1995-09-01 Semiconductor integrated circuit with buffer circuit and manufacturing method thereof

Country Status (3)

Country Link
US (1) US5614842A (en)
JP (1) JPH0879047A (en)
KR (1) KR100197388B1 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5952850A (en) * 1996-09-25 1999-09-14 Kabushiki Kaisha Toshiba Input/output circuit and a method for controlling an input/output signal
US6127840A (en) * 1998-03-17 2000-10-03 International Business Machines Corporation Dynamic line termination clamping circuit
US6281706B1 (en) * 1998-03-30 2001-08-28 National Semiconductor Corp. Programmable high speed quiet I/O cell
US6351172B1 (en) * 2000-02-29 2002-02-26 Dmel Inc. High-speed output driver with an impedance adjustment scheme
US6448812B1 (en) * 1998-06-11 2002-09-10 Infineon Technologies North America Corp. Pull up/pull down logic for holding a defined value during power down mode
US20090073619A1 (en) * 2007-09-18 2009-03-19 Yu-Chen Chen Esd/eos protection circuit and related integrated circuit
US20090179684A1 (en) * 2006-06-22 2009-07-16 Mediatek Inc. Voltage converter with auto-isolation function
US20100081484A1 (en) * 2006-10-12 2010-04-01 Hisateru Kobatake Communication apparatus, semiconductor integrated circuit, and electronic device
US20120119816A1 (en) * 2010-11-17 2012-05-17 Rogers Aaron S Variable-width power gating module
US11264989B1 (en) 2020-08-07 2022-03-01 Kabushiki Kaisha Toshiba Semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006279273A (en) * 2005-03-28 2006-10-12 Oki Electric Ind Co Ltd Interface circuit

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4680487A (en) * 1985-08-19 1987-07-14 Ricoh Company, Ltd. Input/output port including auxiliary low-power transistors
US4697107A (en) * 1986-07-24 1987-09-29 National Semiconductor Corporation Four-state I/O control circuit
JPH025613A (en) * 1988-06-23 1990-01-10 Nec Corp Three-state output circuit
JPH0254617A (en) * 1988-08-18 1990-02-23 Nec Ic Microcomput Syst Ltd Input/output buffer circuit
JPH0382218A (en) * 1989-08-25 1991-04-08 Fujitsu Ltd Two-way buffer
JPH05259879A (en) * 1991-03-15 1993-10-08 Hitachi Ltd Input output buffer
US5450356A (en) * 1994-10-25 1995-09-12 At&T Corp. Programmable pull-up buffer

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4680487A (en) * 1985-08-19 1987-07-14 Ricoh Company, Ltd. Input/output port including auxiliary low-power transistors
US4697107A (en) * 1986-07-24 1987-09-29 National Semiconductor Corporation Four-state I/O control circuit
JPH025613A (en) * 1988-06-23 1990-01-10 Nec Corp Three-state output circuit
JPH0254617A (en) * 1988-08-18 1990-02-23 Nec Ic Microcomput Syst Ltd Input/output buffer circuit
JPH0382218A (en) * 1989-08-25 1991-04-08 Fujitsu Ltd Two-way buffer
JPH05259879A (en) * 1991-03-15 1993-10-08 Hitachi Ltd Input output buffer
US5450356A (en) * 1994-10-25 1995-09-12 At&T Corp. Programmable pull-up buffer

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5952850A (en) * 1996-09-25 1999-09-14 Kabushiki Kaisha Toshiba Input/output circuit and a method for controlling an input/output signal
US6127840A (en) * 1998-03-17 2000-10-03 International Business Machines Corporation Dynamic line termination clamping circuit
US6281706B1 (en) * 1998-03-30 2001-08-28 National Semiconductor Corp. Programmable high speed quiet I/O cell
US6448812B1 (en) * 1998-06-11 2002-09-10 Infineon Technologies North America Corp. Pull up/pull down logic for holding a defined value during power down mode
US6351172B1 (en) * 2000-02-29 2002-02-26 Dmel Inc. High-speed output driver with an impedance adjustment scheme
US20090179684A1 (en) * 2006-06-22 2009-07-16 Mediatek Inc. Voltage converter with auto-isolation function
US20100081484A1 (en) * 2006-10-12 2010-04-01 Hisateru Kobatake Communication apparatus, semiconductor integrated circuit, and electronic device
US20090073619A1 (en) * 2007-09-18 2009-03-19 Yu-Chen Chen Esd/eos protection circuit and related integrated circuit
US7742266B2 (en) * 2007-09-18 2010-06-22 Ali Corporation ESD/EOS protection circuit and related integrated circuit
US20120119816A1 (en) * 2010-11-17 2012-05-17 Rogers Aaron S Variable-width power gating module
US8415972B2 (en) * 2010-11-17 2013-04-09 Advanced Micro Devices, Inc. Variable-width power gating module
US11264989B1 (en) 2020-08-07 2022-03-01 Kabushiki Kaisha Toshiba Semiconductor device

Also Published As

Publication number Publication date
JPH0879047A (en) 1996-03-22
KR100197388B1 (en) 1999-06-15
KR960012462A (en) 1996-04-20

Similar Documents

Publication Publication Date Title
US5017807A (en) Output buffer having capacitive drive shunt for reduced noise
EP0844737B1 (en) Input buffer circuit and bidirectional buffer circuit for plural voltage systems
US5900741A (en) CMOS buffer having stable threshold voltage
US5041741A (en) Transient immune input buffer
US4760292A (en) Temperature compensated output buffer
US5192879A (en) MOS transistor output circuit
US5614842A (en) Semiconductor integrated circuit with buffer circuit and manufacturing method thereof
US4823029A (en) Noise controlled output buffer
US6664814B1 (en) Output driver for an integrated circuit
US6157215A (en) Method and apparatus for controlling impedance
US5880617A (en) Level conversion circuit and semiconductor integrated circuit
US6268755B1 (en) MOSFET predrive circuit with independent control of the output voltage rise and fall time, with improved latch immunity
US6153914A (en) Output circuit for integrated circuits
US5850153A (en) Tristatable output driver for use with 3.3 or 5 volt CMOS logic
US5767697A (en) Low-voltage output circuit for semiconductor device
EP0704972B1 (en) Output circuit for gunning transceiver logic
JP3146829B2 (en) Semiconductor integrated circuit
US4626712A (en) High speed MOS input circuit with precision input-output characteristics
US20030164722A1 (en) System and method for compensating for the effects of process, voltage, and temperature variations in a circuit
US6472906B2 (en) Open drain driver having enhanced immunity to I/O ground noise
US5838168A (en) 3V/5V input buffer
EP0320779A2 (en) Sense amplifier
US6798235B2 (en) Bus control circuit
JP2545995B2 (en) Logic circuit
JPH05327465A (en) Semiconductor integrated circuit

Legal Events

Date Code Title Description
AS Assignment

Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DOKE, KATSURO;SEI, TOSHIKAZU;UMEMOTO, YASUNOBU;AND OTHERS;REEL/FRAME:007753/0981

Effective date: 19951106

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12