US5612260A - Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures - Google Patents

Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures Download PDF

Info

Publication number
US5612260A
US5612260A US08/353,456 US35345694A US5612260A US 5612260 A US5612260 A US 5612260A US 35345694 A US35345694 A US 35345694A US 5612260 A US5612260 A US 5612260A
Authority
US
United States
Prior art keywords
silicon carbide
layer
sacrificial layer
silicon
oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/353,456
Inventor
John W. Palmour
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wolfspeed Inc
Original Assignee
Cree Research Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/893,642 external-priority patent/US5459107A/en
Application filed by Cree Research Inc filed Critical Cree Research Inc
Priority to US08/353,456 priority Critical patent/US5612260A/en
Application granted granted Critical
Publication of US5612260A publication Critical patent/US5612260A/en
Assigned to CREE, INC. reassignment CREE, INC. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: CREE RESEARCH, INC.
Anticipated expiration legal-status Critical
Assigned to WOLFSPEED, INC. reassignment WOLFSPEED, INC. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: CREE, INC.
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/045—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide passivating silicon carbide surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/148—Silicon carbide
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/931—Silicon carbide semiconductor

Definitions

  • the present invention relates to a method of passivating microelectronic structures and in particular relates to passivation of silicon carbide structures using silicon dioxide.
  • Silicon carbide has a number of theoretical and practical advantages that make its use desirable in microelectronic devices. These advantages are fairly well known and include a wide band gap, a high breakdown field, high thermal conductivity, high electron drift velocity, excellent thermal stability, and excellent radiation resistance or "hardness.” These advantages have been recognized and described thoroughly in the patent and nonpatent literature.
  • silicon carbide One of the chemical advantages of silicon carbide is its ability to form a stable and well understood oxide, namely silicon dioxide (SiO 2 ), that can be used to passivate silicon carbide structure and devices.
  • an appropriate thermally-grown oxide passivation layer provides an associated advantageous oxide-semiconductor interface that largely eliminates the presence of dangling bonds (sometimes referred to as dangling valences) on the semiconductor surface, and thus largely eliminates the associated problems such as interface charges and traps.
  • n-channel MOSFETs where the electrical integrity of the oxide layers over the aluminum doped p-type channel region are extremely important, the high interface trap density and fixed oxide charge tend to cause the transistors to have high threshold voltages, low transconductances, low channel mobilities at room temperature, and all of which properties tend to change dramatically with temperature. As these MOSFETs are heated, their behavior improves because the increasing density of thermally generated carriers tend to fill the interface traps.
  • carbon-oxygen compounds are generated by the oxidation of silicon carbide during passivation that are not generated during passivation of silicon. Although not known for certain, these carbon-oxygen species may have their own degrading effect on the electrical integrity of silicon dioxide layers grown on silicon carbide, possibly contributing to fixed oxide charge and premature electric breakdown or wear out.
  • n-type dopants such as nitrogen tend to pile up severely during thermal oxidation of silicon carbide, resulting in an interfacial concentration more than ten times higher than the bulk of the material. Such dopant pile up could additionally have a profound effect on the electrical characteristics of devices such as MOSFETs.
  • the object of the present invention is to provide a method, and resulting structures, of obtaining high quality passivation layers on silicon carbide surfaces, and their associated high quality oxide-semiconductor interfaces in which the oxide passivation layers are substantially free of dopants and carbon-oxygen by-product species that would otherwise degrade the electrical integrity of the oxide layer.
  • the invention meets this object by oxidizing a sacrificial layer of a silicon-containing material on a silicon carbide portion of a device structure to substantially consume the sacrificial layer to produce an oxide passivation layer on the silicon carbide portion that is substantially free of dopants and of carbon-oxygen by-product species that would otherwise degrade the electrical integrity of the oxide layer.
  • the invention comprises oxidizing a device structure formed of a layer of silicon dioxide of a desired thickness on a silicon carbide portion of the device structure to slightly extend the interface between the silicon dioxide and the silicon carbide into the silicon carbide portion. Further to this embodiment, the method comprises depositing a layer of silicon dioxide of a desired thickness on the silicon carbide portion of the device structure without oxidizing the silicon carbide portion prior to the step of oxidizing the device structure.
  • the invention comprises a silicon carbide based device precursor structure comprising a silicon carbide portion and a sacrificial layer of a silicon-containing material on the silicon carbide portion in which the sacrificial layer is selected from the group consisting of polycrystalline silicon (Si), silicon nitride (Si 3 N 4 ), or undoped silicon carbide.
  • the invention comprises a silicon carbide-based device structure having passivation areas that are substantially free of the impurities normally associated with oxides grown on silicon carbide in which the structure comprises a silicon carbide portion and a thermally grown oxidation layer on the silicon carbide portion in which the oxidation layer is substantially free of aluminum and of carbon-oxygen by-products typically associated with thermal oxidation of silicon carbide.
  • FIGS. 1(a)-1(c) are plots of drain current-voltage characteristics of a 6H-SiC inversion-mode MOSFET at (a) 298K, (b) 473K, and (c) 673K;
  • FIGS. 2(a)-2(c) are plots of drain current-voltage characteristics for a 6H-SiC n-channel inversion-mode MOSFET showing the effects of reducing aluminum in the oxide and measured at (a) 298K, (b) 423K, and (c) 573K;
  • FIGS. 3(a) and 3(b) are the initial and final device structures for an n-channel planar MOSFET structure incorporating the present invention
  • FIGS. 4(a), (b), and (c) are progressive cross-sectional views of the processing methodology for a hi-lo IMPATT diode incorporating the present invention.
  • the present invention is a method of obtaining high quality passivation layers on silicon carbide surfaces.
  • the method comprises oxidizing a sacrificial layer of a silicon-containing material on a silicon carbide portion of a device structure to substantially consume the sacrificial layer to produce an oxide passivation layer on the silicon carbide portion that is substantially free of dopants and carbon-oxygen byproduct species that would otherwise degrade the electrical integrity of the oxide layer.
  • the method further comprises the step of forming the sacrificial layer of a silicon containing material on a silicon carbide portion of a device structure prior to the step of thermally oxidizing the sacrificial layer.
  • the step of forming the sacrificial layer comprises forming the sacrificial layer from the group consisting of polycrystalline silicon, silicon nitride or undoped silicon carbide.
  • an undoped layer of silicon carbide would preferably have a carrier concentration of 5E16 (5 ⁇ 10 -16 cm -3 ) or less.
  • Silicon is the most preferred material for the sacrificial layer because it is free of carbon to begin with, and hence substantially eliminates the presence of carbon-oxygen byproducts when oxidized. Furthermore, silicon oxidizes much faster than silicon carbide, so that at an appropriate oxidation rate for silicon, the oxidation effectively stops when the silicon has been consumed, but before any appreciable amount of silicon carbide will be consumed. As a result, a high quality SiO 2 -SiC interface can be controllably formed.
  • the step of forming a sacrificial layer comprises forming a sacrificial layer of a predetermined desired thickness and wherein the step of thermally oxidizing the sacrificial layer comprises thermally oxidizing the sacrificial layer for a time sufficient to substantially consume the sacrificial layer at the rate of thermal oxidation being used.
  • the silicon carbide portion of the device structure comprises a silicon carbide portion having a polytype selected from the group consisting of the 6H, 3C, 4H, 2H and 15R polytypes of silicon carbide.
  • the step of oxidizing the sacrificial layer comprises thermally oxidizing the sacrificial layer, and most preferably while avoiding oxidation of the underlying silicon carbide portion.
  • the thermal oxidation should desirably produce an oxide layer having a thickness sufficient to have substantially consumed the sacrificial layer based on the thickness of the sacrificial layer and the oxide consumption factor of the silicon containing material in the sacrificial layer.
  • the consumption factor for the silicon-containing material's oxidation represents the ratio of the density of silicon atoms in silicon dioxide to the density of silicon atoms in the silicon-containing material.
  • the step of thermally oxidizing the sacrificial layer comprises oxidizing the layer on the basis of the layer's thickness and the oxide consumption factor for the silicon-containing material.
  • the step of forming a sacrificial layer preferably comprises forming the sacrificial layer on a p-type portion of silicon carbide, and most preferably on an aluminum doped p-type portion of silicon carbide.
  • the use of the sacrificial layer of the present invention eliminates the potential for dopant redistribution in the underlying SiC during thermal oxidation, a problem that can arise when the SiC layer is oxidized directly.
  • the method can comprise the step of depositing a boron-doped silicon carbide layer between the silicon carbide portion and the sacrificial silicon layer when silicon is used as the sacrificial layer.
  • the boron-doped silicon carbide layer can be selected from the group consisting of semi-insulating boron-doped silicon carbide layers and p-type boron-doped silicon carbide layers.
  • the sacrificial layer can be formed entirely of a boron-doped silicon carbide epitaxial layer.
  • boron (B) is a p-type dopant for silicon carbide, but one which has little or no negative effect on the electronic properties of silicon dioxide. Additionally, because such a layer has p-type characteristics, it need not be entirely consumed during oxidation when used over another p-type SiC layer or substrate.
  • the method comprises oxidizing the silicon layer to produce an oxide passivation layer having an aluminum dopant concentration of 3E17 (3 ⁇ 10 -17 cm -3 ) or less.
  • the method of the invention can comprise oxidizing a device structure formed of a layer of silicon dioxide of a desired thickness on a silicon carbide portion of the device structure to slightly extend the interface between the silicon dioxide and the silicon carbide into the silicon carbide portion.
  • the oxidizing step preferably comprises thermal oxidation of the device structure.
  • the method of this embodiment further comprises the step of depositing the layer of silicon dioxide of a desired thickness on the silicon carbide portion of the device structure without oxidizing the silicon carbide portion prior to the step of oxidizing the overall device structure.
  • the preferred method of depositing a layer of silicon dioxide of a desired thickness on the silicon carbide portion comprises depositing the layer by chemical vapor deposition.
  • the silicon carbide portion preferably has a polytype selected from the group consisting of the 6H, 3C, 4H, 2H and 15R polytypes of silicon carbide.
  • the invention has been found to be most useful when the step of depositing the layer of silicon dioxide comprises depositing the layer on an aluminum doped, p-type portion of silicon carbide.
  • the invention comprises a silicon carbide-based device precursor structure comprising a silicon carbide portion and a sacrificial layer of a silicon-containing material on the silicon carbide portion, with the sacrificial layer being selected from the group consisting of polycrystalline silicon, polycrystalline silicon nitride or undoped silicon carbide (polycrystalline or epitaxial).
  • the sacrificial layer comprises undoped silicon carbide having a carrier concentration of 5E16 (5 ⁇ 10 -16 cm -3 ) or less.
  • the invention comprises a silicon carbide base device structure having passivation areas that are substantially free of the impurities normally associated with oxides grown on silicon carbide.
  • the structure comprises a silicon carbide portion, and a thermally grown oxidation layer upon the silicon carbide portion, the oxidation layer being substantially free of aluminum and of carbon-oxygen by-products typically associated with thermal oxidation of silicon carbide.
  • the oxidation layer has an aluminum dopant concentration of 3E17 (3 ⁇ 10 -17 cm -3 ) or less.
  • the silicon carbide portion of the device structure can be selected from the group consisting of substrates, epitaxial layers, mesa sidewalls, implanted or diffused wells, and any combination of these structural elements.
  • FIGS. 1 and 2 although not representing identical devices, demonstrate some of the advantages of the present invention.
  • FIG. 1 is a set of three plots of drain current versus drain voltage at selected gate voltages for a 6H-SiC inversion-mode MOSFET at temperatures of 298K, 473K, and 673K. The techniques of the present invention were not used in producing the MOSFET characterized by FIG. 1, and FIG. 1 is thus included for comparative purposes.
  • FIG. 2 represents the same information as FIG. 1 taken at 298K, 423K, and 573K in which an attempt was made to eliminate aluminum entirely from the oxide. This was first attempted on some planar MOSFETs fabricated on the Si-face of silicon carbide and utilizing ion implanted n + source and drain wells.
  • the device of FIG. 1 was produced using dry oxide techniques, while that of FIG. 2 was produced by a wet oxide process. Furthermore, the p-channel of the FIG. 2 device contained less aluminum than the p-channel of the FIG. 1 device.
  • the purpose of including this layer is to consume it during oxidation so that the SiO 2 /SiC interface stops at a point very close to the p-type material or only one or two monolayers into it.
  • the device wafers were oxidized in wet oxygen at 1200° C. for 49 minutes, yielding an oxide thickness of 62 nanometers. Assuming an oxide consumption factor of 0.47, and the loss of about 6 nanometers in a previous reactive ion etching (RIE) step, this thickness would have brought the SiO 2 /SiC interface to within about 2 nm of the p-type material. Although it could not be specifically confirmed whether such dimensions were really the case or whether the interface had aluminum present, it was certain that there was much less aluminum present in the oxide than in previous MOSFETs.
  • RIE reactive ion etching
  • FIGS. 1 and 2 show the improvements provided by the invention in such devices.
  • the maximum transconductance was 0.25 millisiemens per millimeter (mS/mm) at a gate voltage of +24 volts (V).
  • the on-current at a gate voltage of +16 V was 0.5 milliamps (mA).
  • the room temperature drain current at a gate voltage of 16 volts was 18.6 mA and the transconductance at that gate voltage was 2.8 mS/mm.
  • the threshold voltage was about 1.9 volts, which is much lower than the 9 to 12 volts obtained for the device in FIG. 1.
  • the channel mobility was measured to be about 46 cm 2 /V-sec, and the subthreshold leakage current (gate voltage equals 0 volts) was 560 nanoamps (nA).
  • FIGS. 2(b) and 2(c) show the comparative operation of the device at higher temperatures.
  • the temperature was raised to 150° C., as shown in FIG. 2(b)
  • both the current and transconductance at a gate voltage of 16 volts increased to 29 mA and 3.6 mS/mm, and the threshold voltage decreased to about -0.2 volts.
  • This trend continued up to 300° C., as shown in FIG. 2(c).
  • the current and transconductance at the gate voltage of 16 volts were 35 mA and 3.9 mS/mm, respectively.
  • the threshold voltage of the device fell to -0.8 volts
  • the drain current at a gate voltage of 0 volts was only 47 microamps ( ⁇ A).
  • the channel mobility at 300° C. decreased to about 43.5 cm 2 /V-sec.
  • FIGS. 3 and 4 further illustrate the use of the invention and the resulting product.
  • FIG. 3(a) shows a device precursor broadly designated at 10 formed of an n-type 6H-SiC substrate 11 and a p-type 6H epitaxial layer 12.
  • a sacrificially undoped epitaxial layer (“epilayer”) 13 is added upon the p-type epitaxial layer 12.
  • FIG. 3(b) again illustrates the n-type substrate 11 and p-type epitaxial layer 12, but also shows respective n + implanted wells 14 and 15, a metallic source contact 16, a metallic drain contact 17, and a metallic gate contact 18.
  • the source and drain contacts 16,17 are formed of nickel and the gate contact 18 of molybdenum.
  • the oxide layer 19 resulting from the oxidation of the undoped epitaxial layer 13, is also illustrated in FIG. 3(a). By incorporating the method of the present invention, the oxide layer 19 is formed from the undoped layer 13 rather than from the p-type layer 12 to thus minimize the dopant concentration in the oxide and any associated problems.
  • FIG. 4 shows the progressive formation of a mesa type IMPATT (impact avalanche transit time) device broadly designated at 20 and incorporating the method of the present invention.
  • FIG. 4(a) illustrates an n-type 6H SiC substrate 21, an n-type epilayer 22, a second n-type epilayer 23, and a p-type epilayer 24.
  • the first n-type epitaxial layer 22 has a carrier concentration of between about 2 and 3E16
  • the second n-type epitaxial layer 23 has a carrier concentration of about 7E17
  • the p-type epitaxial layer has a carrier concentration of 5E18 or higher.
  • FIG. 4(b) illustrates the same structure but with the addition of a thin layer of polysilicon 25 to both the mesa and rear portions of the device.
  • the thin polysilicon layer 25 is, of course, the sacrificial layer referred to herein.
  • a thin boron-doped silicon carbide layer can be added between the polysilicon layer 25 and the surface or edges of the respective SiC layers 21, 22, 23 and 24.
  • the boron-doped layer should be thick enough to keep aluminum from the interface while otherwise remaining as thin as possible. An appropriate thickness presently appears to be between about 1 and 50 nm.
  • FIG. 4(c) illustrates a completed device after incorporation of the invention.
  • the difference from FIG. 4(b) is the consumption of the polysilicon layer on the mesa portion of the device to form the passivation oxide layer 26.
  • the dopant concentration in the oxide layer 26 can be kept very low, particularly adjacent the heavily doped p-type epitaxial layer 24. As set forth earlier, if the oxide layer 26 had a sufficient carrier concentration, a short circuit could occur between layers 24 and 23, thus incapacitating the device.
  • FIG. 4 also illustrates an ohmic contact 27 to the substrate, preferably formed of nickel, and an ohmic contact 28 to the p-type epitaxial layer on the mesa, and preferably formed of an aluminum alloy.
  • the invention can also be applied to any vertical power MOSFET design in SiC, such as DDMOS (double diffused MOS), UMOS (U-channel MOS), or VMOS (V-channel MOS), that would require use of aluminum as the channel dopant.
  • DDMOS double diffused MOS
  • UMOS U-channel MOS
  • VMOS V-channel MOS

Abstract

A method of obtaining high quality passivation layers on silicon carbide surfaces by oxidizing a sacrificial layer of a silicon-containing material on a silicon carbide portion of a device structure to substantially consume the sacrificial layer to produce an oxide passivation layer on the silicon carbide portion that is substantially free of dopants that would otherwise degrade the electrical integrity of the oxide layer.

Description

This invention was made with Government support and the Government has certain rights in this invention.
This is a continuation of Ser. No. 07/893,642; filed Jun. 5, 1991, now U.S. Pat. No. 5,459,107.
FIELD OF THE INVENTION
The present invention relates to a method of passivating microelectronic structures and in particular relates to passivation of silicon carbide structures using silicon dioxide.
BACKGROUND OF THE INVENTION
Silicon carbide (SIC) has a number of theoretical and practical advantages that make its use desirable in microelectronic devices. These advantages are fairly well known and include a wide band gap, a high breakdown field, high thermal conductivity, high electron drift velocity, excellent thermal stability, and excellent radiation resistance or "hardness." These advantages have been recognized and described thoroughly in the patent and nonpatent literature.
One of the chemical advantages of silicon carbide is its ability to form a stable and well understood oxide, namely silicon dioxide (SiO2), that can be used to passivate silicon carbide structure and devices. As known to those familiar with electronic devices, an appropriate thermally-grown oxide passivation layer provides an associated advantageous oxide-semiconductor interface that largely eliminates the presence of dangling bonds (sometimes referred to as dangling valences) on the semiconductor surface, and thus largely eliminates the associated problems such as interface charges and traps.
There are, however, some problems that arise from silicon dioxide passivation on silicon carbide because of certain properties of silicon carbide. In particular, a common p-type dopant for silicon carbide is aluminum. Although aluminum gives the highest p-type conductivity in silicon carbide, it recently has been discovered that the presence of aluminum incorporated into the thermally grown oxide passivation layers on p-type silicon carbide tend to cause high fixed oxide charge and high trap density at the silicon dioxide-silicon carbide interface. If the aluminum concentration is sufficiently high (for example when an oxide is grown on p+ silicon carbide) the resulting oxide can have very high leakage currents, rendering it disadvantageous or even useless for passivation or electrical isolation. This problem does not occur when passivating silicon with silicon dioxide because aluminum is not a common dopant for silicon.
As a result of these characteristics, when thermally grown oxides have been used to passivate structures such as mesa p+ n- junctions in silicon carbide, the resulting devices tend to demonstrate excessive leakage currents in reverse bias at relatively high voltages (i.e., greater than 50 volts). This leakage current is apparently caused by the poor quality of the passivation on the p+ side of the junction, causing what effectively amounts to a short circuit around the junction. In some p-channel MOSFETs (metal-oxide-semiconductor field effect transistor), the gate contact has been observed to short entirely through the oxide where it overlaps the p+ source and drain wells.
Additionally, in n-channel MOSFETs, where the electrical integrity of the oxide layers over the aluminum doped p-type channel region are extremely important, the high interface trap density and fixed oxide charge tend to cause the transistors to have high threshold voltages, low transconductances, low channel mobilities at room temperature, and all of which properties tend to change dramatically with temperature. As these MOSFETs are heated, their behavior improves because the increasing density of thermally generated carriers tend to fill the interface traps.
Another problem that arises from the difference between silicon carbide and silicon is that carbon-oxygen compounds are generated by the oxidation of silicon carbide during passivation that are not generated during passivation of silicon. Although not known for certain, these carbon-oxygen species may have their own degrading effect on the electrical integrity of silicon dioxide layers grown on silicon carbide, possibly contributing to fixed oxide charge and premature electric breakdown or wear out.
Finally, earlier work has demonstrated that n-type dopants such as nitrogen tend to pile up severely during thermal oxidation of silicon carbide, resulting in an interfacial concentration more than ten times higher than the bulk of the material. Such dopant pile up could additionally have a profound effect on the electrical characteristics of devices such as MOSFETs.
Therefore, there exists the need to develop a method for passivating silicon carbide device structures advantageously with silicon dioxide while avoiding the aforementioned problems.
OBJECT AND SUMMARY OF THE INVENTION
The object of the present invention is to provide a method, and resulting structures, of obtaining high quality passivation layers on silicon carbide surfaces, and their associated high quality oxide-semiconductor interfaces in which the oxide passivation layers are substantially free of dopants and carbon-oxygen by-product species that would otherwise degrade the electrical integrity of the oxide layer.
The invention meets this object by oxidizing a sacrificial layer of a silicon-containing material on a silicon carbide portion of a device structure to substantially consume the sacrificial layer to produce an oxide passivation layer on the silicon carbide portion that is substantially free of dopants and of carbon-oxygen by-product species that would otherwise degrade the electrical integrity of the oxide layer.
In another embodiment, the invention comprises oxidizing a device structure formed of a layer of silicon dioxide of a desired thickness on a silicon carbide portion of the device structure to slightly extend the interface between the silicon dioxide and the silicon carbide into the silicon carbide portion. Further to this embodiment, the method comprises depositing a layer of silicon dioxide of a desired thickness on the silicon carbide portion of the device structure without oxidizing the silicon carbide portion prior to the step of oxidizing the device structure.
In another embodiment, the invention comprises a silicon carbide based device precursor structure comprising a silicon carbide portion and a sacrificial layer of a silicon-containing material on the silicon carbide portion in which the sacrificial layer is selected from the group consisting of polycrystalline silicon (Si), silicon nitride (Si3 N4), or undoped silicon carbide.
In another embodiment, the invention comprises a silicon carbide-based device structure having passivation areas that are substantially free of the impurities normally associated with oxides grown on silicon carbide in which the structure comprises a silicon carbide portion and a thermally grown oxidation layer on the silicon carbide portion in which the oxidation layer is substantially free of aluminum and of carbon-oxygen by-products typically associated with thermal oxidation of silicon carbide.
The foregoing and other objects, advantages and features of the invention, and the manner in which the same are accomplished, will become more readily apparent upon consideration of the following detailed description of the invention taken in conjunction with the accompanying drawings which illustrate preferred and exemplary embodiments, and wherein:
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1(a)-1(c) are plots of drain current-voltage characteristics of a 6H-SiC inversion-mode MOSFET at (a) 298K, (b) 473K, and (c) 673K;
FIGS. 2(a)-2(c) are plots of drain current-voltage characteristics for a 6H-SiC n-channel inversion-mode MOSFET showing the effects of reducing aluminum in the oxide and measured at (a) 298K, (b) 423K, and (c) 573K;
FIGS. 3(a) and 3(b) are the initial and final device structures for an n-channel planar MOSFET structure incorporating the present invention; and FIGS. 4(a), (b), and (c) are progressive cross-sectional views of the processing methodology for a hi-lo IMPATT diode incorporating the present invention.
DETAILED DESCRIPTION
The present invention is a method of obtaining high quality passivation layers on silicon carbide surfaces. In one embodiment, the method comprises oxidizing a sacrificial layer of a silicon-containing material on a silicon carbide portion of a device structure to substantially consume the sacrificial layer to produce an oxide passivation layer on the silicon carbide portion that is substantially free of dopants and carbon-oxygen byproduct species that would otherwise degrade the electrical integrity of the oxide layer. In the preferred embodiment, the method further comprises the step of forming the sacrificial layer of a silicon containing material on a silicon carbide portion of a device structure prior to the step of thermally oxidizing the sacrificial layer. In preferred embodiments, the step of forming the sacrificial layer comprises forming the sacrificial layer from the group consisting of polycrystalline silicon, silicon nitride or undoped silicon carbide. As used herein, an undoped layer of silicon carbide would preferably have a carrier concentration of 5E16 (5×10-16 cm-3) or less.
Silicon is the most preferred material for the sacrificial layer because it is free of carbon to begin with, and hence substantially eliminates the presence of carbon-oxygen byproducts when oxidized. Furthermore, silicon oxidizes much faster than silicon carbide, so that at an appropriate oxidation rate for silicon, the oxidation effectively stops when the silicon has been consumed, but before any appreciable amount of silicon carbide will be consumed. As a result, a high quality SiO2 -SiC interface can be controllably formed.
Further to the preferred embodiment, the step of forming a sacrificial layer comprises forming a sacrificial layer of a predetermined desired thickness and wherein the step of thermally oxidizing the sacrificial layer comprises thermally oxidizing the sacrificial layer for a time sufficient to substantially consume the sacrificial layer at the rate of thermal oxidation being used.
Additionally, in preferred embodiments, the silicon carbide portion of the device structure comprises a silicon carbide portion having a polytype selected from the group consisting of the 6H, 3C, 4H, 2H and 15R polytypes of silicon carbide.
In the preferred embodiments, the step of oxidizing the sacrificial layer comprises thermally oxidizing the sacrificial layer, and most preferably while avoiding oxidation of the underlying silicon carbide portion. In this regard, the thermal oxidation should desirably produce an oxide layer having a thickness sufficient to have substantially consumed the sacrificial layer based on the thickness of the sacrificial layer and the oxide consumption factor of the silicon containing material in the sacrificial layer. As used herein, the consumption factor for the silicon-containing material's oxidation represents the ratio of the density of silicon atoms in silicon dioxide to the density of silicon atoms in the silicon-containing material. Thus, the step of thermally oxidizing the sacrificial layer comprises oxidizing the layer on the basis of the layer's thickness and the oxide consumption factor for the silicon-containing material.
As discussed in the background, the method of the invention is most useful in avoiding contamination of aluminum into the oxide. Accordingly, the step of forming a sacrificial layer preferably comprises forming the sacrificial layer on a p-type portion of silicon carbide, and most preferably on an aluminum doped p-type portion of silicon carbide.
As a further advantage, the use of the sacrificial layer of the present invention eliminates the potential for dopant redistribution in the underlying SiC during thermal oxidation, a problem that can arise when the SiC layer is oxidized directly.
In an alternative embodiment, the method can comprise the step of depositing a boron-doped silicon carbide layer between the silicon carbide portion and the sacrificial silicon layer when silicon is used as the sacrificial layer. The boron-doped silicon carbide layer can be selected from the group consisting of semi-insulating boron-doped silicon carbide layers and p-type boron-doped silicon carbide layers.
In another alternative embodiment, the sacrificial layer can be formed entirely of a boron-doped silicon carbide epitaxial layer. As known to those familiar with silicon carbide and silicon dioxide, boron (B) is a p-type dopant for silicon carbide, but one which has little or no negative effect on the electronic properties of silicon dioxide. Additionally, because such a layer has p-type characteristics, it need not be entirely consumed during oxidation when used over another p-type SiC layer or substrate.
In a preferred embodiment, when a silicon layer is used as the sacrificial layer, the method comprises oxidizing the silicon layer to produce an oxide passivation layer having an aluminum dopant concentration of 3E17 (3×10-17 cm-3) or less.
In an alternative embodiment, the method of the invention can comprise oxidizing a device structure formed of a layer of silicon dioxide of a desired thickness on a silicon carbide portion of the device structure to slightly extend the interface between the silicon dioxide and the silicon carbide into the silicon carbide portion. As in the previous embodiment, the oxidizing step preferably comprises thermal oxidation of the device structure. Most preferably, the method of this embodiment further comprises the step of depositing the layer of silicon dioxide of a desired thickness on the silicon carbide portion of the device structure without oxidizing the silicon carbide portion prior to the step of oxidizing the overall device structure. In this regard, the preferred method of depositing a layer of silicon dioxide of a desired thickness on the silicon carbide portion comprises depositing the layer by chemical vapor deposition. As in the previous embodiment, the silicon carbide portion preferably has a polytype selected from the group consisting of the 6H, 3C, 4H, 2H and 15R polytypes of silicon carbide. Similarly, the invention has been found to be most useful when the step of depositing the layer of silicon dioxide comprises depositing the layer on an aluminum doped, p-type portion of silicon carbide.
In another embodiment, the invention comprises a silicon carbide-based device precursor structure comprising a silicon carbide portion and a sacrificial layer of a silicon-containing material on the silicon carbide portion, with the sacrificial layer being selected from the group consisting of polycrystalline silicon, polycrystalline silicon nitride or undoped silicon carbide (polycrystalline or epitaxial). The carrier concentrations preferred for undoped silicon carbide in the previous embodiments would similarly be preferred for this embodiment. In particular, in a preferred embodiment of the device precursor structure of the invention, the sacrificial layer comprises undoped silicon carbide having a carrier concentration of 5E16 (5×10-16 cm-3) or less.
In another embodiment, the invention comprises a silicon carbide base device structure having passivation areas that are substantially free of the impurities normally associated with oxides grown on silicon carbide. The structure comprises a silicon carbide portion, and a thermally grown oxidation layer upon the silicon carbide portion, the oxidation layer being substantially free of aluminum and of carbon-oxygen by-products typically associated with thermal oxidation of silicon carbide. In the most preferred device structure, the oxidation layer has an aluminum dopant concentration of 3E17 (3×10-17 cm-3) or less. As known to those familiar with silicon carbide and with microelectronic device structures, the silicon carbide portion of the device structure can be selected from the group consisting of substrates, epitaxial layers, mesa sidewalls, implanted or diffused wells, and any combination of these structural elements.
FIGS. 1 and 2, although not representing identical devices, demonstrate some of the advantages of the present invention. FIG. 1 is a set of three plots of drain current versus drain voltage at selected gate voltages for a 6H-SiC inversion-mode MOSFET at temperatures of 298K, 473K, and 673K. The techniques of the present invention were not used in producing the MOSFET characterized by FIG. 1, and FIG. 1 is thus included for comparative purposes.
By way of such comparison, FIG. 2 represents the same information as FIG. 1 taken at 298K, 423K, and 573K in which an attempt was made to eliminate aluminum entirely from the oxide. This was first attempted on some planar MOSFETs fabricated on the Si-face of silicon carbide and utilizing ion implanted n+ source and drain wells. By way of further comparison, the device of FIG. 1 was produced using dry oxide techniques, while that of FIG. 2 was produced by a wet oxide process. Furthermore, the p-channel of the FIG. 2 device contained less aluminum than the p-channel of the FIG. 1 device.
Appropriate techniques for producing bulk silicon carbide, epitaxial layers of silicon carbide, ion implantation of silicon carbide, and dry etching of silicon carbide are set forth in numerous prior patents that are either assigned or exclusively licensed to the assignee of the present invention and specifically U.S. Pat. Nos. 4,912,063; 4,912,064; 4,865,685; 4,866,005; and 5,087,576. These patents are incorporated entirely herein by reference.
The major difference between the MOSFETs formed in the attempt to eliminate aluminum from the oxide and previous MOSFETs was the incorporation of a very thin layer of undoped 6H-SiC grown on top of the p-channel layer. The p-type layer was first grown and measured to have p=4.3×1015 cm-3. Next, an epitaxial layer of undoped silicon carbide only 37 nanometers (nm) thick (n=2-8×1015 cm-3) was grown on top. As previously described herein, the purpose of including this layer is to consume it during oxidation so that the SiO2 /SiC interface stops at a point very close to the p-type material or only one or two monolayers into it.
After fabricating the devices and implanting the wells, the device wafers were oxidized in wet oxygen at 1200° C. for 49 minutes, yielding an oxide thickness of 62 nanometers. Assuming an oxide consumption factor of 0.47, and the loss of about 6 nanometers in a previous reactive ion etching (RIE) step, this thickness would have brought the SiO2 /SiC interface to within about 2 nm of the p-type material. Although it could not be specifically confirmed whether such dimensions were really the case or whether the interface had aluminum present, it was certain that there was much less aluminum present in the oxide than in previous MOSFETs.
FIGS. 1 and 2 show the improvements provided by the invention in such devices. For the device characterized in FIG. 1, the maximum transconductance was 0.25 millisiemens per millimeter (mS/mm) at a gate voltage of +24 volts (V). The on-current at a gate voltage of +16 V was 0.5 milliamps (mA). In the invention, and as indicated in FIG. 2, the room temperature drain current at a gate voltage of 16 volts was 18.6 mA and the transconductance at that gate voltage was 2.8 mS/mm. The threshold voltage was about 1.9 volts, which is much lower than the 9 to 12 volts obtained for the device in FIG. 1. The channel mobility was measured to be about 46 cm2 /V-sec, and the subthreshold leakage current (gate voltage equals 0 volts) was 560 nanoamps (nA).
FIGS. 2(b) and 2(c) show the comparative operation of the device at higher temperatures. When the temperature was raised to 150° C., as shown in FIG. 2(b), both the current and transconductance at a gate voltage of 16 volts increased to 29 mA and 3.6 mS/mm, and the threshold voltage decreased to about -0.2 volts. This trend continued up to 300° C., as shown in FIG. 2(c). At this temperature, the current and transconductance at the gate voltage of 16 volts were 35 mA and 3.9 mS/mm, respectively. Although the threshold voltage of the device fell to -0.8 volts, the drain current at a gate voltage of 0 volts was only 47 microamps (μA). The channel mobility at 300° C. decreased to about 43.5 cm2 /V-sec.
FIGS. 3 and 4 further illustrate the use of the invention and the resulting product.
FIG. 3(a) shows a device precursor broadly designated at 10 formed of an n-type 6H-SiC substrate 11 and a p-type 6H epitaxial layer 12. In accordance with the invention, and in preparation for passivation, a sacrificially undoped epitaxial layer ("epilayer") 13 is added upon the p-type epitaxial layer 12.
After oxidation and further processing the finished device, again designated at 10 for the sake of consistency, is illustrated in FIG. 3(b). FIG. 3(b) again illustrates the n-type substrate 11 and p-type epitaxial layer 12, but also shows respective n+ implanted wells 14 and 15, a metallic source contact 16, a metallic drain contact 17, and a metallic gate contact 18. In preferred embodiments, the source and drain contacts 16,17 are formed of nickel and the gate contact 18 of molybdenum. The oxide layer 19 resulting from the oxidation of the undoped epitaxial layer 13, is also illustrated in FIG. 3(a). By incorporating the method of the present invention, the oxide layer 19 is formed from the undoped layer 13 rather than from the p-type layer 12 to thus minimize the dopant concentration in the oxide and any associated problems.
FIG. 4 shows the progressive formation of a mesa type IMPATT (impact avalanche transit time) device broadly designated at 20 and incorporating the method of the present invention. FIG. 4(a) illustrates an n-type 6H SiC substrate 21, an n-type epilayer 22, a second n-type epilayer 23, and a p-type epilayer 24. In a typical embodiment, the first n-type epitaxial layer 22 has a carrier concentration of between about 2 and 3E16, the second n-type epitaxial layer 23 has a carrier concentration of about 7E17, and the p-type epitaxial layer has a carrier concentration of 5E18 or higher.
FIG. 4(b) illustrates the same structure but with the addition of a thin layer of polysilicon 25 to both the mesa and rear portions of the device. The thin polysilicon layer 25 is, of course, the sacrificial layer referred to herein. As set forth earlier herein, in certain embodiments a thin boron-doped silicon carbide layer can be added between the polysilicon layer 25 and the surface or edges of the respective SiC layers 21, 22, 23 and 24. The boron-doped layer should be thick enough to keep aluminum from the interface while otherwise remaining as thin as possible. An appropriate thickness presently appears to be between about 1 and 50 nm.
FIG. 4(c) illustrates a completed device after incorporation of the invention. The difference from FIG. 4(b) is the consumption of the polysilicon layer on the mesa portion of the device to form the passivation oxide layer 26. Again, by incorporating the invention, the dopant concentration in the oxide layer 26 can be kept very low, particularly adjacent the heavily doped p-type epitaxial layer 24. As set forth earlier, if the oxide layer 26 had a sufficient carrier concentration, a short circuit could occur between layers 24 and 23, thus incapacitating the device.
To complete the device, FIG. 4 also illustrates an ohmic contact 27 to the substrate, preferably formed of nickel, and an ohmic contact 28 to the p-type epitaxial layer on the mesa, and preferably formed of an aluminum alloy.
It will be understood to those familiar with such devices that the invention can also be applied to structures in addition to those illustrated herein, including p-channel planar MOSFETs having implanted p-type wells, and those in which the p-type source and drain are formed from epilayers that have been partially etched away. In either case, an oxide typically will border both a p-portion and an n-portion of the device so that any leakage through the oxide portion will essentially short the device, the avoidance of which is one of the main advantages of the present invention.
The invention can also be applied to any vertical power MOSFET design in SiC, such as DDMOS (double diffused MOS), UMOS (U-channel MOS), or VMOS (V-channel MOS), that would require use of aluminum as the channel dopant.
In the drawings and specifications, there have been disclosed typical preferred embodiments of the invention and, although specific terms have been employed, they have been used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims (10)

That which is claimed is:
1. A method of obtaining high quality passivation layers on silicon carbide surfaces, the method comprising:
forming a sacrificial layer of silicon carbide on a silicon carbide portion of a device structure, wherein the silicon carbide has a concentration of impurities that can affect the electrical characteristics of the oxidized material of no more than 5E16 (5×10-16 cm-3); and
oxidizing the sacrificial layer on the basis of the thickness of the sacrificial layer and the oxide consumption factor for silicon carbide to substantially consume the sacrificial layer to produce an oxide passivation layer on the silicon carbide portion that is substantially free of dopants and other species that would otherwise degrade the electrical integrity of the oxide layer, and that has a thickness sufficient to have substantially consumed the sacrificial layer based upon the thickness of the sacrificial layer and the oxide consumption factor of silicon carbide.
2. A method according to claim 1 wherein the step of oxidizing the sacrificial layer comprises thermally oxidizing the sacrificial layer.
3. A method according to claim 2 wherein the step of thermally oxidizing the sacrificial layer to substantially consume the sacrificial layer comprises thermally oxidizing the sacrificial layer while avoiding oxidation of the underlying silicon carbide portion.
4. A method according to claim 1 wherein the step of forming a sacrificial layer of silicon carbide on a silicon carbide portion of a device structure comprises forming the sacrificial layer on a silicon carbide portion having a polytype selected from the group consisting of: the 6H, 3C, 4H, 2H, and 15R polytypes of silicon carbide.
5. A method according to claim 1 wherein the consumption factor for silicon carbide is the ratio of the density of silicon atoms in silicon dioxide to the density of silicon atoms in silicon carbide.
6. A method according to claim 1 wherein the step of forming a sacrificial layer of silicon carbide on a silicon carbide portion of a device structure comprises forming the sacrificial layer on a p-type portion of silicon carbide.
7. A method according to claim 6 wherein the step of forming the sacrificial layer on a p-type portion of silicon carbide comprises forming the sacrificial layer on an aluminum-doped p-type portion of silicon carbide.
8. A method of obtaining high quality passivation layers on silicon carbide surfaces, the method comprising:
depositing a thin boron-doped silicon carbide epitaxial layer on a p-type silicon carbide portion of a device structure;
forming a sacrificial layer of silicon on the boron-doped silicon carbide epitaxial layer; and
thermally oxidizing the silicon layer while avoiding oxidation of the underlying p-type silicon carbide portion to substantially consume the silicon layer to produce an oxide passivation layer on the silicon carbide portion that is substantially free of dopants and carbon-oxygen by-product species that would otherwise degrade the electrical integrity of the oxide layer;
wherein the boron-doped silicon carbide spitaxial layer is thick enough to prevent aluminum from reaching the resulting oxide while otherwise remaining as thin as possible.
9. A method according to claim 8 wherein the step of depositing a boron-doped silicon carbide epitaxial layer comprises depositing a layer selected from the group consisting of: semi-insulating boron-doped silicon carbide layers and p-type boron-doped silicon carbide layers.
10. A method according to claim 8 wherein the step of thermally oxidizing the silicon layer comprises oxidizing the silicon layer to produce an oxide passivation layer on the silicon carbide portion in which the oxide layer has an aluminum dopant concentration of 3E17 (3×10-17 cm-3) or less.
US08/353,456 1992-06-05 1994-12-09 Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures Expired - Lifetime US5612260A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US08/353,456 US5612260A (en) 1992-06-05 1994-12-09 Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/893,642 US5459107A (en) 1992-06-05 1992-06-05 Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures
US08/353,456 US5612260A (en) 1992-06-05 1994-12-09 Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US07/893,642 Continuation US5459107A (en) 1992-06-05 1992-06-05 Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures

Publications (1)

Publication Number Publication Date
US5612260A true US5612260A (en) 1997-03-18

Family

ID=25401850

Family Applications (3)

Application Number Title Priority Date Filing Date
US08/353,456 Expired - Lifetime US5612260A (en) 1992-06-05 1994-12-09 Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures
US08/352,887 Expired - Lifetime US5629531A (en) 1992-06-05 1994-12-09 Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures
US08/752,716 Expired - Lifetime US5776837A (en) 1992-06-05 1996-11-19 Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures

Family Applications After (2)

Application Number Title Priority Date Filing Date
US08/352,887 Expired - Lifetime US5629531A (en) 1992-06-05 1994-12-09 Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures
US08/752,716 Expired - Lifetime US5776837A (en) 1992-06-05 1996-11-19 Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures

Country Status (1)

Country Link
US (3) US5612260A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6165822A (en) * 1998-01-05 2000-12-26 Denso Corporation Silicon carbide semiconductor device and method of manufacturing the same
US6711191B1 (en) 1999-03-04 2004-03-23 Nichia Corporation Nitride semiconductor laser device
US6835956B1 (en) 1999-02-09 2004-12-28 Nichia Corporation Nitride semiconductor device and manufacturing method thereof
US20090278165A1 (en) * 2008-05-09 2009-11-12 National Chiao Tung University Light emitting device and fabrication method therefor
US20110049530A1 (en) * 2009-08-27 2011-03-03 Cree, Inc. Transistors with a gate insulation layer having a channel depleting interfacial charge and related fabrication methods
US20110073834A1 (en) * 2009-09-25 2011-03-31 International Business Machines Corporation Activation of graphene buffer layers on silicon carbide by ultra low temperature oxidation
US20110169141A1 (en) * 2010-01-11 2011-07-14 International Business Machines Corporation Insulating layers on different semiconductor materials
US8592841B2 (en) 1997-07-25 2013-11-26 Nichia Corporation Nitride semiconductor device

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6344663B1 (en) * 1992-06-05 2002-02-05 Cree, Inc. Silicon carbide CMOS devices
US6573534B1 (en) 1995-09-06 2003-06-03 Denso Corporation Silicon carbide semiconductor device
US5903020A (en) * 1997-06-18 1999-05-11 Northrop Grumman Corporation Silicon carbide static induction transistor structure
US5877041A (en) * 1997-06-30 1999-03-02 Harris Corporation Self-aligned power field effect transistor in silicon carbide
US6096663A (en) * 1998-07-20 2000-08-01 Philips Electronics North America Corporation Method of forming a laterally-varying charge profile in silicon carbide substrate
JP3428459B2 (en) * 1998-09-01 2003-07-22 富士電機株式会社 Silicon carbide n-channel MOS semiconductor device and method of manufacturing the same
JP4186337B2 (en) 1998-09-30 2008-11-26 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
SE9900358D0 (en) * 1999-02-03 1999-02-03 Ind Mikroelektronikcentrum Ab A lateral field effect transistor of SiC, a method of production thereof and a use of such a transistor
SE9900882D0 (en) * 1999-03-12 1999-03-12 Ind Mikroelektronikcentrum Ab A high power IMPATT diode
US6373076B1 (en) * 1999-12-07 2002-04-16 Philips Electronics North America Corporation Passivated silicon carbide devices with low leakage current and method of fabricating
US6956238B2 (en) * 2000-10-03 2005-10-18 Cree, Inc. Silicon carbide power metal-oxide semiconductor field effect transistors having a shorting channel and methods of fabricating silicon carbide metal-oxide semiconductor field effect transistors having a shorting channel
US7221010B2 (en) 2002-12-20 2007-05-22 Cree, Inc. Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors
US6979863B2 (en) * 2003-04-24 2005-12-27 Cree, Inc. Silicon carbide MOSFETs with integrated antiparallel junction barrier Schottky free wheeling diodes and methods of fabricating the same
US7074643B2 (en) * 2003-04-24 2006-07-11 Cree, Inc. Silicon carbide power devices with self-aligned source and well regions and methods of fabricating same
US7118970B2 (en) * 2004-06-22 2006-10-10 Cree, Inc. Methods of fabricating silicon carbide devices with hybrid well regions
US7414268B2 (en) 2005-05-18 2008-08-19 Cree, Inc. High voltage silicon carbide MOS-bipolar devices having bi-directional blocking capabilities
US7615801B2 (en) * 2005-05-18 2009-11-10 Cree, Inc. High voltage silicon carbide devices having bi-directional blocking capabilities
US7391057B2 (en) * 2005-05-18 2008-06-24 Cree, Inc. High voltage silicon carbide devices having bi-directional blocking capabilities
US20060261346A1 (en) * 2005-05-18 2006-11-23 Sei-Hyung Ryu High voltage silicon carbide devices having bi-directional blocking capabilities and methods of fabricating the same
US7528040B2 (en) 2005-05-24 2009-05-05 Cree, Inc. Methods of fabricating silicon carbide devices having smooth channels
US20060267043A1 (en) * 2005-05-27 2006-11-30 Emerson David T Deep ultraviolet light emitting devices and methods of fabricating deep ultraviolet light emitting devices
US7598576B2 (en) * 2005-06-29 2009-10-06 Cree, Inc. Environmentally robust passivation structures for high-voltage silicon carbide semiconductor devices
US7855401B2 (en) * 2005-06-29 2010-12-21 Cree, Inc. Passivation of wide band-gap based semiconductor devices with hydrogen-free sputtered nitrides
US7525122B2 (en) * 2005-06-29 2009-04-28 Cree, Inc. Passivation of wide band-gap based semiconductor devices with hydrogen-free sputtered nitrides
US7883949B2 (en) * 2006-06-29 2011-02-08 Cree, Inc Methods of forming silicon carbide switching devices including P-type channels
US8432012B2 (en) 2006-08-01 2013-04-30 Cree, Inc. Semiconductor devices including schottky diodes having overlapping doped regions and methods of fabricating same
US7728402B2 (en) * 2006-08-01 2010-06-01 Cree, Inc. Semiconductor devices including schottky diodes with controlled breakdown
EP2631951B1 (en) 2006-08-17 2017-10-11 Cree, Inc. High power insulated gate bipolar transistors
US8835987B2 (en) 2007-02-27 2014-09-16 Cree, Inc. Insulated gate bipolar transistors including current suppressing layers
KR20110014996A (en) * 2008-05-08 2011-02-14 바스프 에스이 Layered structures comprising silicon carbide layers, a process for their manufacture and their use
US8232558B2 (en) 2008-05-21 2012-07-31 Cree, Inc. Junction barrier Schottky diodes with current surge capability
US8288220B2 (en) * 2009-03-27 2012-10-16 Cree, Inc. Methods of forming semiconductor devices including epitaxial layers and related structures
US8294507B2 (en) 2009-05-08 2012-10-23 Cree, Inc. Wide bandgap bipolar turn-off thyristor having non-negative temperature coefficient and related control circuits
US8193848B2 (en) 2009-06-02 2012-06-05 Cree, Inc. Power switching devices having controllable surge current capabilities
US8629509B2 (en) * 2009-06-02 2014-01-14 Cree, Inc. High voltage insulated gate bipolar transistors with minority carrier diverter
US8541787B2 (en) * 2009-07-15 2013-09-24 Cree, Inc. High breakdown voltage wide band-gap MOS-gated bipolar junction transistors with avalanche capability
WO2011010608A1 (en) * 2009-07-24 2011-01-27 三菱電機株式会社 Method for manufacturing silicon carbide semiconductor device
US8354690B2 (en) 2009-08-31 2013-01-15 Cree, Inc. Solid-state pinch off thyristor circuits
US9117739B2 (en) 2010-03-08 2015-08-25 Cree, Inc. Semiconductor devices with heterojunction barrier regions and methods of fabricating same
US8415671B2 (en) 2010-04-16 2013-04-09 Cree, Inc. Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices
US9029945B2 (en) 2011-05-06 2015-05-12 Cree, Inc. Field effect transistor devices with low source resistance
US9142662B2 (en) 2011-05-06 2015-09-22 Cree, Inc. Field effect transistor devices with low source resistance
US9640617B2 (en) 2011-09-11 2017-05-02 Cree, Inc. High performance power module
US9373617B2 (en) 2011-09-11 2016-06-21 Cree, Inc. High current, low switching loss SiC power module
JP2014531752A (en) 2011-09-11 2014-11-27 クリー インコーポレイテッドＣｒｅｅ Ｉｎｃ． High current density power module with transistors having improved layout
US8618582B2 (en) 2011-09-11 2013-12-31 Cree, Inc. Edge termination structure employing recesses for edge termination elements
US8664665B2 (en) 2011-09-11 2014-03-04 Cree, Inc. Schottky diode employing recesses for elements of junction barrier array
US8680587B2 (en) 2011-09-11 2014-03-25 Cree, Inc. Schottky diode
US9812338B2 (en) 2013-03-14 2017-11-07 Cree, Inc. Encapsulation of advanced devices using novel PECVD and ALD schemes
US9991399B2 (en) 2012-10-04 2018-06-05 Cree, Inc. Passivation structure for semiconductor devices
US8994073B2 (en) 2012-10-04 2015-03-31 Cree, Inc. Hydrogen mitigation schemes in the passivation of advanced devices

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3911168A (en) * 1973-06-01 1975-10-07 Fairchild Camera Instr Co Method for forming a continuous layer of silicon dioxide over a substrate
DE3434727A1 (en) * 1983-09-24 1985-04-11 Sharp K.K., Osaka Process for fabricating silicon carbide (SiC)/metal oxide semiconductor (MOS) components
US4757028A (en) * 1985-10-07 1988-07-12 Agency Of Industrial Science And Technology Process for preparing a silicon carbide device
US4866005A (en) * 1987-10-26 1989-09-12 North Carolina State University Sublimation of silicon carbide to produce large, device quality single crystals of silicon carbide
US4865685A (en) * 1987-11-03 1989-09-12 North Carolina State University Dry etching of silicon carbide
US4912063A (en) * 1987-10-26 1990-03-27 North Carolina State University Growth of beta-sic thin films and semiconductor devices fabricated thereon
US4912064A (en) * 1987-10-26 1990-03-27 North Carolina State University Homoepitaxial growth of alpha-SiC thin films and semiconductor devices fabricated thereon
EP0363944A1 (en) * 1988-10-12 1990-04-18 Fujitsu Limited Method of manufacturing a semiconductor device having a silicon carbide layer
DE4009837A1 (en) * 1989-03-27 1990-10-11 Sharp Kk METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE
JPH039534A (en) * 1989-06-07 1991-01-17 Sharp Corp Field effect transistor using silicon carbide
US5087576A (en) * 1987-10-26 1992-02-11 North Carolina State University Implantation and electrical activation of dopants into monocrystalline silicon carbide
US5216264A (en) * 1989-06-07 1993-06-01 Sharp Kabushiki Kaisha Silicon carbide MOS type field-effect transistor with at least one of the source and drain regions is formed by the use of a schottky contact
US5272107A (en) * 1983-09-24 1993-12-21 Sharp Kabushiki Kaisha Manufacture of silicon carbide (SiC) metal oxide semiconductor (MOS) device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3874919A (en) * 1974-03-13 1975-04-01 Ibm Oxidation resistant mask layer and process for producing recessed oxide region in a silicon body
US3899373A (en) * 1974-05-20 1975-08-12 Ibm Method for forming a field effect device
CA1165014A (en) * 1981-04-13 1984-04-03 Kei Kurosawa Method for manufacturing semiconductor device
US4735824A (en) * 1985-05-31 1988-04-05 Kabushiki Kaisha Toshiba Method of manufacturing an MOS capacitor
JP2534525B2 (en) * 1987-12-19 1996-09-18 富士通株式会社 Method for manufacturing β-silicon carbide layer
US4851370A (en) * 1987-12-28 1989-07-25 American Telephone And Telegraph Company, At&T Bell Laboratories Fabricating a semiconductor device with low defect density oxide
US4907041A (en) * 1988-09-16 1990-03-06 Xerox Corporation Intra-gate offset high voltage thin film transistor with misalignment immunity
US5061972A (en) * 1988-12-14 1991-10-29 Cree Research, Inc. Fast recovery high temperature rectifying diode formed in silicon carbide
US5225032A (en) * 1991-08-09 1993-07-06 Allied-Signal Inc. Method of producing stoichiometric, epitaxial, monocrystalline films of silicon carbide at temperatures below 900 degrees centigrade
US5371026A (en) * 1992-11-30 1994-12-06 Motorola Inc. Method for fabricating paired MOS transistors having a current-gain differential

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3911168A (en) * 1973-06-01 1975-10-07 Fairchild Camera Instr Co Method for forming a continuous layer of silicon dioxide over a substrate
DE3434727A1 (en) * 1983-09-24 1985-04-11 Sharp K.K., Osaka Process for fabricating silicon carbide (SiC)/metal oxide semiconductor (MOS) components
US5272107A (en) * 1983-09-24 1993-12-21 Sharp Kabushiki Kaisha Manufacture of silicon carbide (SiC) metal oxide semiconductor (MOS) device
US4757028A (en) * 1985-10-07 1988-07-12 Agency Of Industrial Science And Technology Process for preparing a silicon carbide device
US4912064A (en) * 1987-10-26 1990-03-27 North Carolina State University Homoepitaxial growth of alpha-SiC thin films and semiconductor devices fabricated thereon
US4912063A (en) * 1987-10-26 1990-03-27 North Carolina State University Growth of beta-sic thin films and semiconductor devices fabricated thereon
US5087576A (en) * 1987-10-26 1992-02-11 North Carolina State University Implantation and electrical activation of dopants into monocrystalline silicon carbide
US4866005A (en) * 1987-10-26 1989-09-12 North Carolina State University Sublimation of silicon carbide to produce large, device quality single crystals of silicon carbide
US4865685A (en) * 1987-11-03 1989-09-12 North Carolina State University Dry etching of silicon carbide
EP0363944A1 (en) * 1988-10-12 1990-04-18 Fujitsu Limited Method of manufacturing a semiconductor device having a silicon carbide layer
US4994413A (en) * 1988-10-12 1991-02-19 Fujitsu Limited Method of manufacturing a semiconductor device having a silicon carbide layer
DE4009837A1 (en) * 1989-03-27 1990-10-11 Sharp Kk METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE
US5135885A (en) * 1989-03-27 1992-08-04 Sharp Corporation Method of manufacturing silicon carbide fets
JPH039534A (en) * 1989-06-07 1991-01-17 Sharp Corp Field effect transistor using silicon carbide
US5216264A (en) * 1989-06-07 1993-06-01 Sharp Kabushiki Kaisha Silicon carbide MOS type field-effect transistor with at least one of the source and drain regions is formed by the use of a schottky contact

Non-Patent Citations (8)

* Cited by examiner, † Cited by third party
Title
6H Silicon Carbide Transistors for High Temperature Operation, J. W. Palmour et al., Proceedings, First International High Temperature Electronics Conference, Jun. 16 20, 1991, pp. 511 518. *
6H-Silicon Carbide Transistors for High Temperature Operation, J. W. Palmour et al., Proceedings, First International High Temperature Electronics Conference, Jun. 16-20, 1991, pp. 511-518.
Dopant Redistribution During Thermal Oxidation of Monocrystalline Beta SiC Thin Films, J. W. Palmour et al., Journal of Electrochemical Society, vol. 136, No. 2, Feb. 1989, pp. 502 507. *
Dopant Redistribution During Thermal Oxidation of Monocrystalline Beta-SiC Thin Films, J. W. Palmour et al., Journal of Electrochemical Society, vol. 136, No. 2, Feb. 1989, pp. 502-507.
SiC Electronics For High Temperature Control Systems, D. M. Brown et al., (4pages), presented at GOMAC 91, Nov. 4 7, 1991, Orlando, FL. *
SiC Electronics For High Temperature Control Systems, D. M. Brown et al., (4pages), presented at GOMAC-91, Nov. 4-7, 1991, Orlando, FL.
Wet and Dry Oxidation of Single Crystal SiC: Kinetics and Interface Characteristics, J. W. Palmour et al., Mat. Res. Soc. Symp. Proc., vol. 54, pp. 553 559. *
Wet and Dry Oxidation of Single Crystal β-SiC: Kinetics and Interface Characteristics, J. W. Palmour et al., Mat. Res. Soc. Symp. Proc., vol. 54, pp. 553-559.

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8592841B2 (en) 1997-07-25 2013-11-26 Nichia Corporation Nitride semiconductor device
US6165822A (en) * 1998-01-05 2000-12-26 Denso Corporation Silicon carbide semiconductor device and method of manufacturing the same
US6452228B1 (en) 1998-01-05 2002-09-17 Denso Corporation Silicon carbide semiconductor device
US6835956B1 (en) 1999-02-09 2004-12-28 Nichia Corporation Nitride semiconductor device and manufacturing method thereof
US20040101986A1 (en) * 1999-03-04 2004-05-27 Nichia Corporation Nitride semiconductor laser device
US20060078022A1 (en) * 1999-03-04 2006-04-13 Tokuya Kozaki Nitride semiconductor laser device
US6711191B1 (en) 1999-03-04 2004-03-23 Nichia Corporation Nitride semiconductor laser device
US20090278165A1 (en) * 2008-05-09 2009-11-12 National Chiao Tung University Light emitting device and fabrication method therefor
US7977687B2 (en) 2008-05-09 2011-07-12 National Chiao Tung University Light emitter device
US20110049530A1 (en) * 2009-08-27 2011-03-03 Cree, Inc. Transistors with a gate insulation layer having a channel depleting interfacial charge and related fabrication methods
US8841682B2 (en) * 2009-08-27 2014-09-23 Cree, Inc. Transistors with a gate insulation layer having a channel depleting interfacial charge and related fabrication methods
US9343540B2 (en) 2009-08-27 2016-05-17 Cree, Inc. Transistors with a gate insulation layer having a channel depleting interfacial charge
US20110073834A1 (en) * 2009-09-25 2011-03-31 International Business Machines Corporation Activation of graphene buffer layers on silicon carbide by ultra low temperature oxidation
US8242030B2 (en) 2009-09-25 2012-08-14 International Business Machines Corporation Activation of graphene buffer layers on silicon carbide by ultra low temperature oxidation
US20110169141A1 (en) * 2010-01-11 2011-07-14 International Business Machines Corporation Insulating layers on different semiconductor materials
US8592325B2 (en) 2010-01-11 2013-11-26 International Business Machines Corporation Insulating layers on different semiconductor materials

Also Published As

Publication number Publication date
US5776837A (en) 1998-07-07
US5629531A (en) 1997-05-13

Similar Documents

Publication Publication Date Title
US5612260A (en) Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures
US5459107A (en) Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures
US5506421A (en) Power MOSFET in silicon carbide
Sridevan et al. Lateral n-channel inversion mode 4H-SiC MOSFETs
US9552997B2 (en) Silicon carbide switching devices including P-type channels
JP3462506B2 (en) Unit cell of silicon carbide metal insulator semiconductor field effect transistor and silicon carbide metal insulator semiconductor field effect transistor comprising the same
US6084268A (en) Power MOSFET device having low on-resistance and method
US6297100B1 (en) Method of manufacturing silicon carbide semiconductor device using active and inactive ion species
JP3385938B2 (en) Silicon carbide semiconductor device and method of manufacturing the same
US6940110B2 (en) SiC-MISFET and method for fabricating the same
US5900648A (en) Semiconductor device having an insulated gate
JP2003318398A (en) Silicon carbide semiconductor device
US9343540B2 (en) Transistors with a gate insulation layer having a channel depleting interfacial charge
KR100762545B1 (en) Self-aligned silicon carbide lmosfet
JP2644028B2 (en) Silicon carbide MOSFET
CN104241374B (en) Deep-energy-level impurity tunneling field-effect transistor (TFET) and preparation method thereof
JP2001298189A (en) Semiconductor device and manufacturing method thereof
US5574295A (en) Dielectrically isolated SiC mosfet
WO1997049124A1 (en) A method for producing a channel region layer in a voltage controlled semiconductor device
Noborio et al. 4H-SiC MIS Capacitors and MISFETs With Deposited $\hbox {SiN} _ {x}/\hbox {SiO} _ {2} $ Stack-Gate Structures
US5516589A (en) Silicon carbide thin film circuit element and method of manufacturing the same
JP3285997B2 (en) Insulated gate power semiconductor device
EP4333027A1 (en) Method of manufacturing ohmic contacts of an electronic device, with thermal budget optimization
CN117637457A (en) Method of fabricating ohmic contacts for electronic devices with thermal budget optimization
CA1312148C (en) Metal-semiconductor field-effect transistor formed in silicon carbide

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAT HLDR NO LONGER CLAIMS SMALL ENT STAT AS INDIV INVENTOR (ORIGINAL EVENT CODE: LSM1); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

AS Assignment

Owner name: CREE, INC., NORTH CAROLINA

Free format text: CHANGE OF NAME;ASSIGNOR:CREE RESEARCH, INC.;REEL/FRAME:010832/0545

Effective date: 19991201

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: WOLFSPEED, INC., NORTH CAROLINA

Free format text: CHANGE OF NAME;ASSIGNOR:CREE, INC.;REEL/FRAME:057891/0880

Effective date: 20211001