US5559457A

US5559457A - Double-balanced mixer circuit

Info

Publication number: US5559457A
Application number: US08/215,193
Authority: US
Inventors: Hisanori Uda; Tetsuro Sawai; Toshikazu Imaoka; Toshikazu Hirai; Yasoo Harada
Original assignee: Sanyo Electric Co Ltd
Current assignee: Sanyo Electric Co Ltd
Priority date: 1993-03-26
Filing date: 1994-03-21
Publication date: 1996-09-24
Anticipated expiration: 2014-03-21
Also published as: JPH06334440A

Abstract

A double-balanced mixer circuit which consumes less power, and is capable of operating on a low voltage power source, because an output of a first signal having a phase lag of 90° from a first frequency signal and an output of a second signal having a phase lead of 90° over the first frequency signal are provided by means of a first phase shifter, an output of a third signal having a phase lag of 90° from a second frequency signal and an output of fourth signal having a phase lead of 90° over the second frequency signal are provided by means of a second phase shifter, thereby generating a radio frequency signal by mixing the first signal and the third signal in a first dual gate circuit, and generating a radio frequency signal by mixing the second signal and the fourth signal in a second dual gate circuit.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a double-balanced mixer circuit used for mixing signals of different frequencies.

2. Description of Related Art

In a portable telephone, for example, a local oscillation frequency signal and an intermediate frequency signal are mixed in a mixer circuit to generate a radio frequency signal which is to be transmitted. Because mixing of signals having different frequencies is based on a non-linear characteristic, outputs from the mixer circuit include, in addition to the radio frequency signal obtained by mixing, the individual local oscillation frequency signal which is not mixed and the individual intermediate frequency signal which is not mixed. In order to suppress the individual local oscillation frequency signal and the individual intermediate frequency signal, a double-balanced mixer circuit is commonly used for the mixer circuit.

FIG. 1 shows a circuit diagram of a conventional double-balanced mixer circuit. The double-balanced mixer circuit comprises a differential amplifier circuit DFA1 which outputs a signal LO₁ of the same phase as the local oscillation frequency signal LO and a signal #LO₁ obtained by an 180° phase shift on the local oscillation frequency signal LO upon input of the local oscillation frequency signal LO (frequency LO), a differential amplifier circuit DFA2 which outputs a signal IF₁ of the same phase as the intermediate frequency signal IF (frequency IF) and a signal #IF₁ obtained by 180° phase shift on the intermediate frequency signal IF upon input of the intermediate frequency signal IF, and an analog multiplier circuit ALG which mixes the local oscillation frequency signal LO and the intermediate frequency signal IF upon input of the signals LO₁ and #LO₁ which are output from the differential amplifier circuit DFA1 and the signals IF₁ and #IF₁ which are output from the differential amplifier circuit DFA2.

In the differential amplifier circuit DFA1, a power supply V_DD is grounded via ann series circuit of an FET (field effect transistor) 2 and a resistor R₁, and is grounded via a series circuit of a resistor R₂, an FET 3 and an FET 4. In parallel with the series circuit of the resistor R₂ and the FET 3, a series circuit of a resistor R₃ and a FET 5 is connected. The power supply V_DD is further grounded via a series circuit of an FET 6 and a resistor R₄, with a capacitor C₁ being connected in parallel with the resistor R₄. The junction of the FET 2 and the resistor R₁ is connected to one terminal of the capacitor C₂ and to the gate of the FET 3. The local oscillation frequency signal LO is fed to the other terminal of the capacitor C₂. The gate of the FET 5 is connected to the junction of the FET 6, the resistor R₄ and the capacitor C₁. The signal LO₁ of the same phase as the local oscillation frequency signal LO is output from the junction of the resistor R₂ and the FET 3, and the signal #LO₁ of the phase being shifted from that of the local oscillation frequency signal LO by 180° is output from the junction of the resistor R₃ and the FET 5.

The differential amplifier circuit DFA2 is made in a similar constitution as that of the differential amplifier circuit DFA1, and identical components are assigned the same numerals. In the differential amplifier circuit DFA2, the intermediate frequency signal IF is supplied to other terminal of the capacitor C₂. The signal IF₁ of the same phase as the intermediate frequency signal IF is output from the junction of the resistor R₂ and the FET 3, and a signal #IF₁ of the phase being shifted from that of the intermediate frequency signal IF by 180° is output from the junction of the resistor R₃ and the FET 5.

In the analog multiplier circuit ALG, a power source V_CC is connected to one terminal of a current source 10 via a series circuit of a resistor R₁₀ (R₁₁), a transistor Q₁ (Q₄) and a transistor Q₅ (Q₆), with another terminal of the current source 10 being grounded. The junction of the resistor R₁₀ (R₁₁) and the transistor Q₁ (Q₄) is connected to the junction of the transistor Q₄ (Q₁) and the transistor Q₆ (Q₅) via the transistor Q₃ (Q₂). The bases of the transistors Q₂ and Q₃ are connected to each other and the bases of the transistors Q₁ and Q₄ are connected to each other. The radio frequency signal RF generated by mixing the local oscillation frequency signal LO and the intermediate frequency signal IF is output from the junction of the resistor R₁₁, the transistor Q₂ and the transistor Q₄.

On the other hand, the signal LO₁ (#LO₁) from the differential amplifier circuit DFA1 is inputted to the bases of the transistors Q₂ and Q₃ (Q₁ and Q₄), and the signal IF₁ (#IF₁) from the differential amplifier circuit DFA2 is inputted to the bases of the transistor Q₆ (Q₅).

The operation of the double-balanced mixer circuit will now be described below.

When the local oscillation frequency signal LO is inputted to the differential amplifier circuit DFA1, the signal LO₁ having the same phase as the local oscillation frequency LO and the signal #LO₁ having a phase 180° shifted from the local oscillation frequency LO are inputted from the differential amplifier circuit DFA1 to the analog multiplier circuit ALG. When the intermediate frequency signal IF is inputted to the differential amplifier circuit DFA2, the signal IF₁ having the same phase as the intermediate frequency signal IF and the signal #IF₁ having a phase 180° shifted from the intermediate frequency signal IF are inputted from the differential amplifier circuit DFA2 to the analog multiplier circuit ALG. Then the analog multiplier circuit ALG outputs the radio frequency signals RF having frequencies of LO+IF and LO-IF generated by mixing the local oscillation frequency signal LO and the intermediate frequency signal IF.

The signal LO₁ and the signal #LO₁ cancel each other, and the signal IF₁ and the signal #IF₁ cancel each other, so that the signals LO₁, #LO₁, IF₁ and #IF₁ are not output individually, thereby improving the S/N ratio of the radio frequency signal RF.

The phase of a signal to be mixed can also be shifted by changing the path length. And the required change in the path length decreases as the frequency becomes higher. Therefore the method of changing the path length is employed in applications with frequencies 10 GHz or higher, in consideration of the degree of circuit integration.

Such a circuit is also employed in which phase inverter circuits are employed for the differential amplifier circuits DFA1 and DFA2 for phase shift. FIG. 2 shows a circuit diagram of a phase inverter circuit. The power supply V_DD is grounded via a circuit comprising a parallel connection of a series circuit of a resistor R₂₀ and a resistor R₂₁, a series circuit of a resistor R₂₂, an FET 10 and a resistor R₂₃, a series circuit of an FET 11 and a resistor R₂₄, and a series circuit of an FET 12 and a resistor R₂₅.

The junction of the resistors R₂₀ and R₂₁ is connected to one terminal of a capacitor C₁₀ and to the gate of the FET 10, while the local oscillation frequency signal LO or the intermediate frequency signal IF is fed to the other terminal of the capacitor C₁₀.

The junction of the resistor R₂₂ and the FET 10 is connected to the gate of the FET 12, and the junction of the FET 10 and the resistor R₂₃ is connected to the gate of the FET 11. The signal LO₁ having the same phase as that of the local oscillation frequency signal LO or the signal IF₁ having the same phase as that of the intermediate frequency signal IF is output from the junction of the FET 12 and the resistor R₂₅ via the capacitor C₁₁. The signal #LO₁ having a phase being shifted by 180° from the local oscillation frequency signal LO or the signal #IF₁ having a phase being shifted by 180° from the intermediate frequency signal IF is output from the junction of the FET 11 and the resistor R₂₄ via the capacitor C₁₂.

Also in the case where this phase inverter circuit is used, similarly to the case where the differential amplifier circuit is employed, the signal LO₁ of the same phase as the local oscillation frequency signal LO and the signal #LO₁ obtained by 180° phase shift from the local oscillation frequency signal LO are obtained from the phase inverter circuit upon input of the local oscillation frequency signal LO, and the signal IF₁ of the same phase as that of the intermediate frequency signal IF and the signal #IF₁ obtained by 180° phase shift from the intermediate frequency signal IF are obtained from the phase inverter circuit upon input of the intermediate frequency signal IF.

The conventional double-balanced mixer circuit as described above is capable of good double-balanced mixing operation with less signal attenuation. However, because the conventional double-balanced mixer circuit comprises the differential amplifier circuits or the phase inverter circuit employing a number of FETs and the analog multiplier circuit employing a number of transistors, it consumes a considerable amount of power, and is therefore not suitable for the application in a portable telephone which has a limitation in the power consumption. Because the differential amplifier circuit, the phase inverter circuit and the analog multiplier circuit employ cascaded FETs and transistors, a significant voltage drop occurs and it is difficult to drive the portable telephone by a low-voltage power source, for example a 3 V power source, which is required in the portable telephone.

Also because a portable telephone uses the radio frequency signal RF having a frequency of 1.9 GHz, a GaAs MESFET (Metal Semiconductor FET) which has excellent high-frequency characteristics is more suitable than transistors based on Si. However, a GaAs MESFET is likely to depart from the linear small signal operation region when a signal having voltage amplitude greater than a certain level (for example, 0.1 to 0.2 V or higher) is inputted to the gate thereof, making it impossible to obtain a linear output. Because the local oscillation frequency signal and the intermediate frequency signal commonly used in a portable telephone have voltage amplitude of 0.1 V or higher, in a differential amplifier circuit made by using GaAs MESFETs as described above, a gate of the GaAs MESFET receives an input voltage higher than the level which gives a linear output, and results in such a problem as the distortion of the phase-shifted signals.

SUMMARY OF THE INVENTION

The invention has been conceived to solve the problems described above, and has a major object of providing a double-balanced mixer circuit which consumes a small amount of power and is capable of using a low voltage power source, by reducing the number of FETs (or transistors) being used.

Another object of the invention is to provide a double-balanced mixer circuit which is capable of outputting the radio frequency signal which has a high S/N ratio by means of a circuit wherein no FET (or transistor) is used in the first phase shifter and the second phase shifter.

The double-balanced mixer circuit of the invention comprises two phase shifters outputting signals whose phases are different from each other by 180° and two dual gate FETs to which said signals are inputted.

The double-balanced mixer circuit of the invention has a first phase shifter which outputs a first signal having a phase lag of 90° from a first frequency signal and a second signal having a phase lead of 90° over the first frequency signal upon input of the first frequency signal, and a second phase shifter which outputs a third signal having a phase lag of 90° from a second frequency signal and a fourth signal having a phase lead of 90° over the second frequency signal upon input of the second frequency signal which has a frequency different from that of the first signal. The first signal and the third signal are inputted to a first dual gate circuit and are mixed in the first dual gate circuit. Said second signal and said fourth signal are inputted to a second dual gate circuit and are mixed in the second dual gate circuit. The first dual gate circuit and the second dual gate circuit are arranged so that the output signals thereof are superposed with each other.

In the double-balanced mixer circuit having the constitution as described above, when the first frequency signal is inputted to the first phase shifter, the first phase shifter outputs the first signal having a phase lag of 90° from the first frequency signal and a second signal having a phase lead of 90° over the first frequency signal. When the second frequency signal is inputted to the second phase sifter, the second phase shifter outputs the third signal having a phase lag of 90° from the second frequency signal and the fourth signal having a phase lead of 90° over the second frequency signal.

The dual gate circuit is applied as a means for mixing signals based on non-linear characteristic. The dual gate circuit comprises a dual gate FET to use the non-linear characteristic of the dual gate FET. The principle will be briefly described below. Generally, the non-linear characteristic is capable of approximating the output by expanding the input in a progression. In the progression expansion expression, the first degree term shows the signals amplified and damped original signals, the second degree term shows the sum signal and the difference signal obtained the product of input signals, which are also amplified and damped. Although the signals corresponding to the third or higher degree term are output, these signals are small enough in amplitude to be disregarded.

The first dual gate circuit which has received the inputs of the first signal and the third signal outputs a signal generated by mixing the first signal and the third signal, the individual first signal and the individual third signal. The second dual gate circuit which has received the inputs of the second signal and the fourth signal outputs a signal generated by mixing the second signal and the fourth signal, the individual second signal and the individual fourth signal. The sum signal obtained by mixing the second signal and the fourth signal has the same phase as the sum signal obtained by mixing the first signal and the third signal. The difference signal obtained by mixing the second signal and the fourth signal has the same phase as the difference signal obtained by mixing the first signal and the third signal. When the signals output by the first dual gate circuit and the signals output by the second dual gate circuit are superposed, the original first and the individual second signals cancel each other and vanish because they are out of phase by 180°. Similarly, the individual third and the individual fourth signals cancel each other and vanish because they are out of phase by 180°. By superposing the sum signal of the first signal and the third signal and the sum signal of the second signal and the fourth signal, the signal whose amplitude is twice the sum signal of the first signal and the third signal is generated. By superposing the difference signal of the first signal and the third signal and the difference signal of the second signal and the fourth signal, the signal whose amplitude is twice the difference signal of the first signal and the third signal is generated. Consequently, only the radio frequency signal generated by mixing the first frequency signal and the second frequency signal is output.

The dual gate circuit which mixes the signals whose phases are different by 180° needs less FETs and transistors than the prior art, and needs no cascaded circuit of FETs, so that it is capable of reducing the power consumption in the circuit and using a lower voltage power source. The invention does not employ FETs (or transistors) in the first phase shifter and the second phase shifter. Consequently, it is capable of driving the double-balanced mixer circuit by even less power consumption and lower voltage, and also capable of obtaining an output signal which has a high S/N ratio because phase-shifted signals are not distorted.

Further another object of the invention is to provide a double-balanced mixer circuit capable of preventing the signal output from one duel gate circuit from entering the other dual gate circuit.

The double-balanced mixer circuit of the invention is further made in such a way that it includes, in addition to the first phase shifter, the second phase shifter, the first dual gate circuit and the second dual gate circuit, a coupler which, when the output signal of the first dual gate circuit and the output signal of the second dual gate circuit are inputted thereto, provides the superposed signal of the outputs on the output side thereof.

In this double-balanced mixer circuit, when the output signal of the first dual gate circuit and the output signal of the second dual gate circuit are inputted to the coupler, the radio frequency signal generated by superposing these signals is output.

Consequently, in view of the output side of the coupler, the possibility of the reverse flow of the radio frequency signal which is output from the coupler into the first dual gate circuit or the second dual gate circuit is reduced by setting the sum of the impedance of the components of the coupler and the output impedance of the FET which constitutes the dual gate circuit to a value higher than the impedance of the external circuit connected to the radio frequency output terminals.

The above and further objects and features of the invention will more fully be apparent from the following detailed description with accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a conventional double-balanced mixer circuit.

FIG. 2 is a circuit diagram of a phase inverter circuit.

FIG. 3 is a block circuit diagram illustrative of the constitution of the double-balanced mixer circuit of the invention.

FIG. 4 is a phase characteristic diagram of an output signal of a phase shifter.

FIG. 5 is an actual circuit diagram of the double-balanced mixer circuit of the invention.

FIG. 6 is an equivalent circuit diagram of a phase shifter comprising resistors and capacitors.

FIG. 7 is an actual circuit diagram illustrative of another constitution of the double-balanced mixer circuit of the invention.

FIG. 8 is an actual circuit diagram illustrative of further another constitution of the double-balanced mixer circuit of the invention.

FIG. 9 is an equivalent circuit diagram of a phase shifter comprising coils, resistors and capacitors.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Now the invention will be described in detail below with reference to the drawings illustrative of the preferred embodiments.

FIG. 3 is a block circuit diagram illustrative of the construction of a double-balanced mixer circuit of the invention. A local oscillation frequency signal LO having a frequency LO is inputted to a phase shifter PS1 comprising only passive elements, and an intermediate frequency signal IF having a frequency IF is inputted to a phase shifter PS2 comprising only passive elements. The phase shifter PS1 is made to output a signal LO' (frequency LO) with a phase lag of 90° from the local oscillation frequency signal LO and a signal #LO' (frequency LO) with a phase lead of 90° over the local oscillation frequency signal LO. The phase shifter PS2 is made to output a signal IF' (frequency IF) with a phase lag of 90° from the intermediate frequency signal IF and a signal #IF' (frequency IF) with a phase lead of 90° over the intermediate frequency signal IF.

The signal LO' output by the phase shifter PS1 is inputted to one input terminal of a dual gate circuit DG1 provided with, for example, a dual gate FET and the signal IF' output by the phase shifter PS2 is inputted to the other terminal of the dual gate circuit DG1. The signal output by #LO' of the phase shifter PS1 is inputted to one input terminal of a dual gate circuit DG2 provided with, for example, a dual gate FET and the signal #IF' output by the phase shifter PS2.

The dual gate circuit DG1 is made to mix the signal LO' and the signal IF', and the dual gate circuit DG2 is made to mix the signal #LO' and the signal #IF'. An output terminal of the dual gate circuit DG1 and an output terminal of the dual gate circuit DG2 are connected to each other, so that the signal output from the dual gate circuit DG1 and the signal output from the dual gate circuit DG2 are superposed. Then the radio frequency signal RF obtained by this superposition is output.

The operation of the double-balanced mixer circuit will now be described below with reference to FIG. 4 illustrative of the phase characteristic of the phase shifter PS1 (PS2).

When the local oscillation frequency signal LO is inputted to the phase shifter PS1, the phase shifter PS1 outputs a signal LO' with a phase lag of 90° from the local oscillation frequency signal LO and a signal #LO' with a phase lead of 90° over the local oscillation frequency signal LO as shown in FIG. 4. The signal LO' is inputted to one input terminal of the dual gate circuit DG1 and the signal #LO' is inputted to one input terminal of the dual gate circuit DG2. Similarly, when the intermediate frequency signal IF is inputted to the phase shifter PS2, the phase shifter PS2 outputs the signal IF' with a phase lag of 90° from the intermediate frequency signal IF and a signal #IF' with a phase lead of 90° over the intermediate frequency signal IF. The signal IF' is inputted to the other input terminal of the dual gate circuit DG1 and the signal #IF' is inputted to the other input terminal of the dual gate circuit DG2.

The dual gate circuit DG1 mixes the signal LO' and the signal IF' which have been inputted, and outputs signals LO'+IF' and LO'-IF' which are obtained by mixing and the individual signals LO' and IF'. The dual gate circuit DG2 mixes the signal #LO' and the signal #IF' which have been inputted, and outputs signals #LO'+#IF' and #LO'-#IF' which are obtained by mixing and the individual signals #LO' and #IF'.

These signals LO'+IF', LO'-IF', LO', IF', #LO'+#IF', #LO'-#IF', #LO' and #IF' are superposed (added) on the output side of the dual gate circuits DG1, DG2. The signal LO' and the signal #LO' cancel out each other because they have a phase difference of 180°, similarly the signal IF' and the signal #IF' cancel out each other because they have a phase difference of 180°, so that the individual signals LO', #LO', IF' and #IF' disappear.

The signal LO'+IF' and the signal LO'-IF' are generated from the component of the product of the signal LO' and the signal IF' by the dual gate FET applying the effect of the non-linear characteristic. Similarly the signal #LO'+#IF' and the signal #LO'-#IF' are generated from the component of the product of the signal #LO' and the signal #IF' by the dual gate FET applying the effect of the non-linear characteristic. The product of the signal #LO' having a phase being shifted by 180° from the signal LO' and the signal #IF' having a phase being shifted by 180° from the signal IF' has the same phase as the product of the signal LO' and the signal IF', so that the signal LO'+IF' is identical with the signal #LO'+#IF'. Similarly the signal LO'-IF' is identical with the signal #LO'-#IF'. Therefore the signal obtained by superposing the signals output by the dual gate circuit has twice in amplitude the signal output by the dual gate circuit.

Thus only the radio frequency signal RF which is generated by mixing is output with a high signal level, making it possible to obtain the output of the radio frequency signal RF of a high S/N ratio.

Also according to the invention, both the phase shifters PS1, PS2 are made by employing passive elements without using FETs, and the dual gate circuit is made by using a single dual gate FET. Therefore power consumption in the phase shifters PS1, PS2 and in the dual gate circuits DG1, DG2 can be greatly reduced. Also because no significant voltage drop occurs unlike the prior art wherein cascaded FETs are used, a low voltage power source can be used.

Moreover, the radio frequency signal RF is not subjected to distortion because phase shift is applied to the signals by using passive elements only. Furthermore, the circuit construction can be simplified because the dual gate circuit does not use many FETs. The dual gate FET provides excellent isolation of the local oscillation frequency signal LO and the intermediate frequency signal IF.

FIG. 5 shows a circuit diagram illustrative of an actual circuit of the double-balanced mixer circuit of the invention mounted on a GaAs substrate. Numerical figures appearing in parentheses in FIG. 5 are the values of resistance or capacitance in the conventional units of ohms or pico farads.

An input terminal t_L for the local oscillation frequency signal LO is grounded via a resistor R₅₀ (50), and is grounded via a series circuit of a resistor R₅₁ (800), a resistor R₅₂ (800) and a capacitor C₅₀ (0.12). The junction of the resistor R₅₁ (800) and the resistor R₅₂ (800) is grounded via the capacitor C₅₁ (0.12). An input terminal t_L is connected to one terminal of a resistor R₅₃ (720) via a series circuit of a capacitor C₅₂ (0.24) and a capacitor C₅₃ (0.24). The junction of the capacitors C₅₂ and C₅₃ is grounded via a resistor R₅₄ (400) and the junction of the capacitor C₅₃ and the resistor R₅₃ is grounded via a resistor R₅₅ (400). The phase shifter PS1 comprises the resistors R₅₁, R₅₂, R₅₃, R₅₄ and R₅₅ and the capacitors C₅₀, C₅₁, C₅₂ and C₅₃.

An input terminal t_I for the intermediate frequency signal IF is grounded via a resistor R₅₆ (50), and is grounded via a series circuit of a resistor R₅₇ (1200), a resistor R₅₈ (1200) and a capacitor C₅₄ (0.5). The junction of the resistor R₅₇ (1200) and the resistor R₅₈ (1200) is grounded via a capacitor C₅₅ (0.5). The input terminal t_I is connected to one terminal of a resistor R₅₉ (1080) via a series circuit of a capacitor C₅₆ (1.0) and a capacitor C₅₇ (1.0). The junction of the capacitor C₅₆ (1.0) and the capacitor C₅₇ (1.0) is grounded via a resistor R₆₀ (600) and the junction of the capacitor C₅₇ (1.0) and the resistor R₅₉ (1080) is grounded via a resistor R₆₁ (600). The phase shifter PS2 comprises the resistors R₅₇, R₅₈, R₅₉, R₆₀ and R₆₁ and the capacitors C₅₄, C₅₅, C₅₆ and C₅₇.

The power supply V_DD is grounded via a series circuit of a resistor R₆₂ (5k) and a resistor R₆₃ (620), and is grounded via a series circuit of a resistor R₆₄ (5k) and a resistor R₆₅ (620). The junction of the resistor R₆₄ (5k) and the resistor R₆₅ (620) is connected to one input terminal (gate) of a dual gate FET 100 via a resistor R₆₆ (5k), and the junction of the resistor R₆₂ (5k) and the resistor R₆₃ (620) is connected to the other input terminal (gate) of a dual gate FET 100 via a resistor R₆₇ (5k). One output lead (source) of the dual gate FET 100 is grounded via a parallel circuit of a resistor R₆₈ (82) and a capacitor C₅₈ (14).

The gate width Wg of the dual gate FET 100 is made to be 600 μm, and both pairs of the gate and the source are biased to -0.3 V. The dual gate circuit DG1 comprises the dual gate FET 100, the resistors R₆₂, R₆₃, R₆₄, R₆₅, R₆₆, R₆₇, R₆₈ and the capacitor C₅₈.

The power supply V_DD is grounded via a series circuit of a resistor R₆₉ (5k) and a resistor R₇₀ (620), and is grounded via a series circuit of a resistor R₇₁ (5k) and a resistor R₇₂ (620). The junction of the resistor R₇₁ (5k) and the resistor R₇₂ (620) is connected to one input terminal (gate) of a dual gate FET 101 via a resistor R₇₃ (5k). The junction of the resistor R₆₉ (5k) and the resistor R₇₀ (620) is connected to the other input terminal (gate) of the dual gate FET 101 via a resistor R₇₄ (5k).

One output terminal (source) of the dual gate FET 101 is grounded via a parallel circuit of a resistor R₇₅ (82) and a capacitor C₅₉ (14). The width of the gates Wg of the dual gate FET 101 are made to be 600 μm, and both pairs of the gate and the source are biased to -0.3 V. The dual gate circuit DG2 comprises the dual gate FET 101, the resistors R₆₉, R₇₀, R₇₁, R₇₂, R₇₃, R₇₄, R₇₅ and the capacitor C₅₉.

The junction of the resistor R₅₂ (800) and the capacitor C₅₀ (0.12) of the phase shifter PS1 is connected to one input terminal of the dual gate FET 100, and the junction of the resistor R₅₈ (1200) and the capacitor C₅₄ (0.5) of the phase shifter PS2 is connected to the other input terminal of the dual gate FET 100. The other terminal of the resistor R₅₃ (720) of the phase shifter PS1 is connected to one input terminal of the dual gate FET 101, and the other terminal of the resistor R₅₉ (1080) of the phase shifter PS2 is connected to the other input terminal of the dual gate FET 101.

The other output (drain) of the dual gate FET 100 and the other input (drain) of the dual gate FET 101 are combined and connected to a radio frequency output terminal t_H whereon the radio frequency signal RF is output. The radio frequency output terminal t_H is grounded via a series circuit of a resistor R₇₆ (50) and a capacitor C₆₀ (14). The junction of the resistor R₇₆ (50) and the capacitor C₆₀ (14) is connected to the power supply V_DD via a parallel circuit of a capacitor C₆₁ (2.34) and a coil L of 3 nH. The voltage of the power supply V_DD is set to 3 V.

FIG. 6 shows an equivalent circuit diagram explanatory of the conditions to determine the values of the resistors and capacitors of the phase shifters PS1, PS2. Resistors R₅₁, R₅₂ of the phase shifter PS1 shown in FIG. 5 correspond to R_B, R_B, resistors R₅₄, R₅₅ correspond to R_A, R_A, capacitors C₅₀, C₅₁ correspond to C_B, C_B, and capacitors C₅₂, C₅₃ correspond to C_A, C_A. Resistors R₅₇, R₅₈ of the phase shifter PS2 correspond to R_B, R_B, resistors R₆₀, R₆₁ correspond to R_A, R_A, capacitors C₅₄, C₅₅ correspond to C_B, C_B, and capacitors C₅₆, C₅₇ correspond to C_A, C_A. The values of the resistors and the capacitors are determined by the following formulae.

R.sub.B =2·R.sub.A                                (1)

C.sub.B =(1/2)·C.sub.A                            (2)

where

1/(R.sub.A ·C.sub.A)=1/(R.sub.B ·C.sub.B)=2πf(3)

must be satisfied. Frequency f is 1.65 GHz for the local oscillation frequency signal LO, and 0.25 GHz for the intermediate frequency signal IF.

When the local oscillation frequency signal LO and the intermediate frequency signal IF are inputted to the double-balanced mixer circuit having the construction as described above, the phase shifter PS1 outputs a signal LO' with a phase lag of 90° from the local oscillation frequency signal LO and a signal #LO' with a phase lead of 90° over the local oscillation frequency signal LO, and the phase shifter PS2 outputs a signal IF' with a phase lag of 90° from the intermediate frequency signal IF and a signal #IF' with a phase lead of 90° over the intermediate frequency signal IF, as described previously. The dual gate circuit DG1 mixes the signal LO' and the signal IF', and the dual gate circuit DG2 mixes the signal #LO' and the signal #IF'.

Mixed signals LO'+IF', LO'-IF', #LO'+#IF' and #LO'-#IF' are output from the dual gate circuits DG1, DG2, and are superposed to produce the radio frequency signals RF, having frequencies of LO+IF and LO-IF and twice the amplitude of the original signal, which are output at the radio frequency output terminal t_H. The signals LO' and IF' which are output individually from the dual gate circuit DG1 and the signals #LO' and #IF' which are output individually from the dual gate circuit DG2 cancel out each other and disappear.

It was verified with this actual circuit that, when the local oscillation frequency signal LO having a frequency of 1.65 GHz and the intermediate frequency signal IF having a frequency of 0.25 GHz were inputted with a level of -5 dBm, radio frequency signal RF having a frequency of 1.9 GHz was obtained with a voltage amplitude of 50 mV.

As described above, because the dual gate circuits and the phase shifters which do not employ FETs and transistors but passive elements are used in the double-balanced mixer circuit of the invention, power consumption can be greatly reduced. Also because no significant voltage drop occurs in the phase shifters and the dual gate circuits, a low voltage power source can be used. Moreover, even when signals having large amplitudes are inputted to the phase shifter, distortion of the signal is prevented by building the phase shifter of passive elements.

FIG. 7 shows an actual circuit diagram illustrative of another embodiment of the double-balanced mixer circuit of the invention. Numerical figures indicated in parentheses in FIG. 7 are the values of inductance, resistance and capacitance in units of nH, ohms and pico farads, respectively.

An input terminal t_L for the local oscillation frequency signal LO is grounded via a series circuit of a coil L₃₀ (6.3) and a capacitor C₃₀ (0.3). A matching circuit MC1 comprises the coil L₃₀ (6.3) and the capacitor C₃₀ (0.3). The junction of the coil L₃₀ (6.3) and the capacitor C₃₀ (0.3) is grounded via a series circuit of a resistor R₃₀ (200), a resistor R₃₁ (200) and a capacitor C₃₂ (0.482), and the junction of the resistor R₃₀ (200) and the resistor R₃₁ (200) is grounded via a capacitor C₃₁ (0.482).

The junction of the coil L₃₀ (6.3) and the capacitor C₃₀ (0.3) is grounded via a series circuit of the capacitor C₃₃ (0.964) the capacitor C₃₄ (0.964) and the resistor R₃₃ (100). The junction of the capacitor C₃₃ (0.964) and the capacitor C₃₄ (0.964) is grounded via the resistor R₃₂ (100). The junction of the capacitor C₃₄ (0.964) and the resistor R₃₃ (100) is connected to one lead of the capacitor C₃₅ (1.0). The phase shifter PS1 comprises the resistors R₃₀, R₃₁, R₃₂, R₃₃ and the capacitors C₃₁, C₃₂, C₃₃, C₃₄, C₃₅.

An input terminal t_I for the intermediate frequency signal IF is grounded via a series circuit of a coil L₃₁ (100), a capacitor C₃₆ (1000) and a capacitor C₃₇ (3.1). The coil L₃₁ (100) and the capacitor C₃₆ (1000) are connected on the outside. A matching circuit MC2 comprises the coil L₃₁ and the capacitors C₃₆, C₃₇. The junction of the capacitor C₃₆ (1000) and the capacitor C₃₇ (3.1) is grounded via a series circuit of a capacitor C₃₈ (1.06), a capacitor C₃₉ (1.06) and a resistor R₃₅ (600). The junction of the capacitor C₃₈ (1.06) and the capacitor C₃₉ (1.06) is grounded via the resistor R₃₄ (600). The junction of the capacitor C₃₉ (1.06) and the resistor R₃₅ (600) is connected to one terminal of a capacitor C₄₀ (1.0).

The junction of the capacitor C₃₆ (1000) and the capacitor C₃₇ (3.1) is grounded via a series circuit of a resistor R₃₆ (1200), a resistor R₃₇ (1200) and a capacitor C₄₂ (0.53). The junction of the resistor R₃₆ (1200) and the resistor R₃₇ (1200) is grounded via a capacitor C₄₁ (0.53). The phase shifter PS2 comprises the resistors R₃₄, R₃₅, R₃₆, R₃₇ and the capacitors C₃₈, C₃₉, C₄₀, C₄₁ and C₄₂.

The junction of the resistor R₃₁ (200) and the capacitor C₃₂ (0.482) of the phase shifter PS1 is connected to one terminal (gate) of the dual gate FET 102, and the other terminal of the capacitor C₄₀ (1.0) of the phase shifter PS2 is connected to the other input terminal (gate) of the dual gate FET 102. One input terminal of the dual gate FET 102 is grounded via a resistor R₃₈ (3k), and the other input terminal is grounded via a resistor R₃₉ (3k). The gate width Wg of the dual gate FET 102 is made to be 400 μm, and the gate length of one input terminal 0.7 μm and the gate length of the other input terminal 0.5 μm.

The junction of the resistor R₃₇ (1200) and the capacitor C₄₂ (0.53) of the phase shifter PS2 is connected to one input terminal (gate) of the dual gate FET 103, and the other terminal of the capacitor C₃₅ (1.0) of the phase shifter PS1 is connected to the other input terminal (gate) of the dual gate FET 103. One input terminal of the dual gate FET 103 is grounded via a resistor R₄₁ (3k), and the other input terminal is grounded via a resistor R₄₀ (3k). The gate width Wg of the dual gate FET 103 is made to be 400 μm, and the gate length of one input lead 0.7 μm and gate length of the other input terminal 0.5 μm.

The dual gate circuit DG1 comprises the dual gate FET 102 and the resistors R₃₈, R₃₉, and the dual gate circuit DG2 comprises the dual gate FET 103 and the resistors R₄₀, R₄₁. One output terminal (source) of each of the dual gate FET 102 and the dual gate FET 103 is grounded. A capacitor C₄₃ (0.47) is inserted between the other output terminal (drain) of the dual gate FET 102 and the other output terminal (drain) of the dual gate FET 103, and the capacitor C₄₃ (0.47) is connected with a parallel pair of a series circuit of a coil L₃₁ (5.0) and a coil L₃₂ (5.0) and a series circuit of a capacitor C₄₄ (0.5) and a capacitor C₄₅ (0.5).

A coupler CPL comprises the capacitor C₄₃, the coils L₃₁, L₃₂ and the capacitors C₄₄, C₄₅. The junction of the capacitor C₄₄ (0.5) and the capacitor C₄₅ (0.5) is connected with a radio frequency output terminal t_H where the radio frequency signal RF is output, via a parallel circuit of a capacitor C₄₆ (0.4) and a coil L₃₃ (8.0). The junction of the coil L₃₁ (5.0) and the coil L₃₂ (5.0) is connected the power supply V_DD via a coil L₃₄ (200) which is connected on the outside. A matching circuit MC3 comprises the capacitor C₄₆ and the coil L₃₃.

The coupler CPL are constructed so that the impedance of the coupler CPL at the radio frequency output terminal t_H side plus the output impedance of the dual gate FET 102 is greater than the impedance of the circuit to be connected to the radio frequency output terminal t_H.

When the local oscillation frequency signal LO and the intermediate frequency signal IF are inputted to the double-balanced mixer circuit of the constitution as described above, the phase shifter PS1 outputs the signal LO' having a phase lag of 90° from the local oscillation frequency signal LO and the signal #LO' having a phase lead of 90° over the local oscillation frequency signal LO, and the phase shifter PS2 outputs the signal IF' having a phase lag of 90° from the intermediate frequency signal IF and the signal #IF' having a phase lead of 90° over the intermediate frequency signal IF, similarly as described previously. The dual gate circuit DG1 mixes the signal LO' and the signal IF', and the dual gate circuit DG2 mixes the signal #LO' and the signal #IF'.

Mixed signals LO'+IF', LO'-IF', #LO'+#IF', #LO'-#IF', and the individual signals LO', IF', #LO', #IF' are output from the dual gate circuits DG1, DG2, and are superposed on the output side of the coupler CPL, to provide the radio frequency signals RF, having frequencies of LO+IF and LO-IF and twice the amplitude of the original signal, at the radio frequency output terminal t_H.

The signals LO' and IF' which are output individually from the dual gate circuit DG1 and the signals #LO' and #IF' which are output individually from the dual gate circuit DG2 cancel out each other thereby to disappear.

By providing the coupler CPL, it is made less likely that the signals LO'+IF', LO'-IF' which are output from the dual gate circuit DG1 via the capacitor C₄₄ (0.5) flow to the dual gate circuit DG2. It is also made less likely that the signals #LO'+#IF', #LO'-#IF' which are output from the dual gate circuit DG2 via the capacitor C₄₅ (0.5) flow to the dual gate circuit DG1. Therefore, the levels of the mixed signals LO'+IF', LO'-IF', #LO'+#IF', #LO'-#IF' do not decrease on the output side of the coupler CPL, and these signals can be superposed with high efficiency and output at the radio frequency output terminal t_H.

It was verified experimentally that, when the power voltage V_DD was set to 3 V, the frequency of the local oscillation frequency signal LO was set to 1.65 GHz, the frequency of the intermediate frequency signal IF was set to 0.25 GHz, and the frequency of the radio frequency signal RF was set to 1.9 GHz, conversion gain of 0 dBm was obtained from the input of the local oscillation frequency signal LO of 5 dBm and the input of the intermediate frequency signal IF of 0 dBm.

FIG. 8 shows an actual circuit diagram illustrative of further another constitution of the double-balanced mixer circuit of the invention. Numerical figures indicated in parentheses in FIG. 8 are the values of inductance, resistance and capacitance in the unit of nH, ohm and pico farad, respectively.

An input terminal t_L for the local oscillation frequency signal LO is grounded via a parallel circuit of a capacitor C₈₀ (0.5) and a resistor R₈₀ (35) and a series circuit of a coil L₈₀ (5.0) and a resistor R₈₁ (100). The junction of the coil L₈₀ (5.0) and the resistor R₈₁ (100) is grounded via a capacitor C₈₁ (1.86). The junction of the capacitor C₈₀ (0.5), the resistor R₈₀ (35) and the coil L₈₀ (5.0) is grounded via a series circuit of a capacitor C₈₂ (1.86) and a resistor R₈₂ (100), and the junction of the capacitor C₈₂ (1.86) and the resistor R₈₂ (100) is grounded via a coil L₈₁ (5.0). A matching circuit MC1 comprises the capacitor C₈₀ and the resistor R₈₀. The phase shifter PS1 comprises the coils L₈₀, L₈₁, the capacitors C₈₁, C₈₂ and the resistor R₈₁, R₈₂.

An input terminal t_I for the intermediate frequency signal IF is grounded via a series circuit of a coil L₈₂ (100), a capacitor C₈₃ (1000), a capacitor C₈₄ (1.06), a capacitor C₈₅ (1.06) and a resistor R₈₄ (600). The junction of the capacitor C₈₄ (1.06) and the capacitor C₈₅ (1.06) is grounded via a resistor R₈₃ (600). The junction of the resistor R₈₄ (600) the and capacitor C₈₅ (1.06) is connected to one terminal of a capacitor C₈₆ (1.0).

The junction of the capacitor C₈₃ (1000) and the capacitor C₈₄ (1.06) is grounded via a series circuit of a resistor R₈₅ (1200), a resistor R₈₆ (1200) and a capacitor C₈₈ (0.53), and the junction of the resistor R₈₅ (1200) and the resistor R₈₆ (1200) is grounded via a capacitor C₈₇ (0.53). The coil L₈₂ and the capacitor C₈₃ are connected on the outside, and a matching circuit MC2 comprises the coil L₈₂ and the capacitor C₈₃. The phase shifter PS2 comprises the capacitors C₈₄, C₈₅, C₈₆, C₈₇, C₈₈ and the resistors R₈₃, R₈₄, R₈₅, R₈₆.

The junction of the coil L₈₀ (5.0), the capacitor C₈₁ (1.86) and the resistor R₈₁ (100) of the phase shifter PS1 is connected to one terminal (gate) of the dual gate FET 104. The other terminal of the capacitor C₈₆ (1.0) of the phase shifter PS2 is connected to the other input lead (gate) of the dual gate FET 104. One input terminal of the dual gate FET 104 is grounded via a resistor R₈₇ (3k), and the other input terminal is grounded via a resistor R₈₈ (3k). The gate width Wg of the dual gate FET 104 is made to be 200 or 400 μm. The dual gate circuit DG1 comprises the dual gate FET 104, resistors R₈₇ and R₈₈.

The junction of the resistor R₈₆ (1200) and the capacitor C₈₈ (0.53) of the phase shifter PS2 is connected to one input terminal (gate) of the dual gate FET 105. The junction of the capacitor C₈₂ (1.86), the coil L₈₁ (5.0) and the resistor R₈₂ (100) of the phase shifter PS1 is connected to the other input terminal (gate) of the dual gate FET 105. One input terminal of the dual gate FET 105 is grounded via a resistor R₉₀ (3k), and the other input terminal is grounded via a resistor R₈₉ (3k). The gate width of the dual gate FET 105 is made to be 200 or 400 μm. The dual gate circuit DG2 comprises the dual gate FET 105, the resistors R₈₉ and R₉₀.

One output terminal (source) of the dual gate FET 104 and one output terminal (source) of the dual gate FET 105 are grounded. A capacitor C₈₉ (0.47) is inserted between the other output terminal (drain) of the dual gate FET 104 and the other output terminal (drain) of the dual gate FET 105. The capacitor C₈₉ (0.47) is connected to a parallel combination of a series circuit of the coil L₈₂ (5.0) and the coil L₈₃ (5.0) and a series circuit of a capacitor C₉₀ (0.5) and a capacitor C₉₁ (0.5).

A coupler CPL comprises the capacitors C₈₉, C₉₀, C₉₁ and the coils L₈₂, L₈₃. The junction of the capacitor C₉₀ (0.5) and the capacitor C₉₁ (0.5) is connected with the radio frequency output terminal t_H, where the radio frequency signal RF is output, via a parallel circuit of a capacitor C₉₂ (0.4) and a coil L₈₄ (8.0). A matching circuit MC3 comprises the capacitor C₉₂ and the coil L₈₄. The junction of the coil L₈₂ (5.0) and the coil L₈₃ (5.0) is connected to the power supply V_DD via a coil L₈₅ (200).

The coupler CPL is constructed so that the impedance of the coupler CPL at the radio frequency output terminal t_H side plus the output impedance of the dual gate FET 104 is greater than the impedance of the circuit to be connected to the radio frequency output terminal t_H.

FIG. 9 shows an equivalent circuit diagram explanatory of the conditions to determine the values of the coils, resistors and capacitors of the phase shifter PS1. The coils L₈₀, L₈₁ of the phase shifter PS1 shown in FIG. 8 correspond to L_A, L_A, the resistors R₈₁, R₈₂ correspond to R_C, R_C, and the capacitors C₈₁, C₈₂ correspond to C_C, C_C. The values of the coils, resistors and capacitors are determined by the following formula.

(L.sub.A ·C.sub.C).sup.-1/2 =2πf               (4)

Where frequency f is 1.65 GHz for the local oscillation frequency signal LO, and 0.25 GHz for the intermediate frequency signal IF.

When the local oscillation frequency signal LO and the intermediate frequency signal IF are inputted to the double-balanced mixer circuit of the constitution as described above, the phase shifter PS1 outputs a signal LO' having a phase lag of 90° from the local oscillation frequency signal LO and a signal #LO' with a phase lead of 90° over the local oscillation frequency signal LO, similarly as described previously. And the phase shifter PS2 outputs a signal IF' having a phase lag of 90° from the intermediate frequency signal IF and a signal #IF' having a phase lead of 90° over the intermediate frequency signal IF, similarly as described previously. The dual gate circuit DG1 mixes the signal LO' and the signal IF', and the dual gate circuit DG2 mixes the signal #LO' and the signal #IF'. This is followed by an operation similar to that described previously, to provide the radio frequency signal RF having frequencies of LO+IF and LO-IF at the radio frequency output terminal t_H.

The voltage gain of the phase shifter PS1, which is the ratio of the output voltage to the input voltage thereof, is determined by the values of the coils, resistors and capacitors which constitute the phase shifter. When the values of the coils, resistors and capacitors which constitute the phase shifter PS1 are as shown in FIG. 8, the voltage gain of 5.6 dB is obtained for the phase shifter PS1 with a coefficient X for determining the voltage gain being given by the formula (5) from which X=0.26 is obtained.

X=(L.sub.A /C.sub.C).sup.1/2 /(2·R.sub.C)         (5)

Thus a voltage gain comparable to that obtained with a phase shifter comprising resistors and capacitors can be obtained, thereby verifying that the phase shifter having the construction as described above can be used in a practical application similarly to the phase shifter comprising resistors and capacitors.

Because this embodiment has, in addition to the effects of foregoing embodiments, the effect of making it less likely that the signal which is output to the output side of the coupler flow to the dual gate circuit, the signal level does not decrease at the output side of the coupler, thereby enabling it to efficiently superpose the signals on the output side of the coupler.

Although one phase shifter PS1 comprises the coils, resistors and capacitors and another phase shifter PS2 comprises the resistors and capacitors in this embodiment, the phase shifter PS2 can also be made from coils, resistors and capacitors. While the coil becomes larger in size in this case which makes it impossible to incorporate it in the MMIC (Monolithic Micro wave IC), connecting the phase shifter to the IC on the outside makes this construction applicable to practical use.

Although a case of mixing the local oscillation frequency signal and the intermediate frequency signal is described in this embodiment, the invention can also be applied with similar effects, for example, to a reception signal mixer circuit, an analog multiplier circuit, a frequency conversion circuit or the like where it is required to mix signals of different frequencies.

Although the phase shifters comprises only passive elements in foregoing embodiments, the phase shifters can also comprise FETs. In this case power consumption is larger than foregoing embodiments, but it can be made smaller than the prior art because the dual gate circuit is used for performing the double-balance.

As this invention may be embodied in several forms without departing from the spirit of essential characteristics thereof, the present embodiment is therefore illustrative and not restrictive, since the scope of the invention is defined by the appended claims rather than by the description preceding them, and all changes that fall within metes and bounds of the claims, or equivalence of such metes and bounds thereof are therefore intended to be embraced by the claims.

Claims

What is claimed is:

1. A double-balanced mixer circuit for mixing a first input signal of a first frequency and a second input signal of a second frequency comprising:

a first phase shifter, comprising passive elements, having an input, and receiving at said input the first input signal and providing as outputs a first output signal having a phase lag of 90° from said first input signal and a second output signal having a phase lead of 90° from said first input signal;

a second phase shifter, comprising passive elements, having an input, and receiving at said input the second input signal and providing as outputs a third output signal having a phase lag of 90° from said second input signal and a fourth output signal having a phase lead of 90° from said second input signal;

wherein the passive elements forming each of said first and second phase shifters comprise only resistors and capacitors between said input and an output of a respective said phase shifter, the passive elements of each said phase shifter having an equivalent electrical circuit represented by first and second branches originating from said input of a respective said phase shifter;

said first branch of the equivalent electrical circuit having first and second resistances each of value R₃ connected in series at a junction and in series with said phase shifter input, a capacitance of value C_B connected from the junction of said first and second resistances to a common potential point, and another capacitance of value C_B connected from the end of the resistance remote from the said phase shifter input to the common potential point,

said second branch of the electrical equivalent circuit having first and second capacitances each of a value C_A connected in series at a junction and in series to said phase shifter input, and a resistance of a value R_A connected from the junction of the first and second capacitances to the common potential point and another resistance of value R_A connected from the end of the capacitance remote from the input to the common potential point, and wherein

R.sub.B =2·R.sub.A                                ( 1)

C.sub.B =(1/2)·C.sub.A                            ( 2)

where

1/(R.sub.A ·C.sub.A)=1/(R.sub.B C.sub.B)=2πf   (3)

and where f is the frequency of one of the signals of a first frequency and a second frequency;

a first dual gate mixer circuit having an input and an output and a dual gate FET receiving as inputs said first and third output signals and mixing the same to produce at said output said first output signal and said third output signal;

a second dual gate mixer circuit having an input and an output and a dual gate FET receiving as inputs said second output signal and said fourth output signal and mixing the same to produce at said output said second output signal and said fourth output signal; and

combining means coupled to said output of each of said first dual gate mixer circuit and said second dual gate mixer circuit for providing a combined output signal by combining said first output signal outputted from said first dual gate mixer circuit and said second output signal outputted from said second dual gate mixer circuit to cancel each other, and said third output signal outputted from said first dual gate mixer circuit and said fourth output signal outputted from said second dual gate mixer circuit to cancel each other.

2. A double-balanced mixer circuit as claimed in claim 1, further comprising an output terminal connected to said combining means and means for producing at said output terminal a further output signal of a frequency corresponding to a selected one of the sum of and the difference between the first frequency and the second frequency.

3. A double-balanced mixer circuit as in claim 1 wherein said first dual gate mixer circuit also produces as outputs fifth and sixth output signals which are respectively the sum and difference of said first and third output signals and further outputs said first input signal, and said second dual gate mixer circuit also produces as outputs seventh and eighth output signals which are respectively the sum and difference of said second and fourth output signals and further outputs said second input signal, and

said combining means cancelling said fifth and seventh output signals outputted respectively from said first and second dual gate mixer circuits and cancelling said sixth and eighth output signals outputted respectively from said first and second dual gate mixer circuits and producing a signal having a frequency corresponding to a selected one of the sum of and the difference between the first frequency and the second frequency.

4. A double-balanced mixer circuit for mixing a first input signal of a first frequency and a second input signal of a second frequency comprising:

said first branch of the equivalent electrical circuit having first and second resistances each of value R_B connected in series at a junction and in series with said phase shifter input, a capacitance of value C_B connected from the junction of said first and second resistances to a common potential point, and another capacitance of value C_B connected from the end of the resistance remote from the said phase shifter input to the common potential point,

said second branch of the electrical equivalent circuit having first and second capacitances each of a value C_A connected in series at a junction and in series to said phase shifter input, and a resistance of a value R_A connected from the junction of the first and second capacitances to the common potential point, and another resistance of value R_A connected from the end of the capacitance remote from the input to the common potential point, and wherein

R.sub.B =2·R.sub.A                                ( 1)

C.sub.B =(1/2)·C.sub.A                            ( 2)

where

1/(R.sub.A ·C.sub.A)=1/(R.sub.B ·C.sub.B)=2πf(3)

and where f is the frequency and one of the signals of a first frequency and a second frequency;

a coupler for combining the output signals of the first dual gate mixer circuit and the output signals of the second dual gate mixer circuit and to output to an output terminal a resultant signal whose frequency is a selected one of a sum of and a difference between the signal of a first frequency and the signal of a second frequency for supply to an external circuit.

5. A double-balanced mixer circuit for mixing a first input signal of a first frequency and a second input signal of a second frequency comprising:

the passive elements forming at least one of said phase shifters comprising only resistors, capacitors and inductors between said input and output of said at least one phase shifter,

the passive elements of said at least one phase shifter having an equivalent electrical circuit represented by first and second branches originating from said input of said at least one phase shifter,

said first branch of the electrical equivalent circuit having an inductance of value L_A with one end connected to said input of said at least one phase shifter and a capacitance of value C_C and a resistance of value R_C connected in parallel from the other end of the inductance to a point of reference potential and

said second branch of said equivalent electrical circuit having a capacitance of value C_C with one end connected to said input of said at least one phase shifter and an inductance of value L_A and a resistance of value R_C connected in parallel from the other end of said capacitance to the point of reference potential, wherein

(L.sub.A ·C.sub.C).sup.-1/2 =2πf

and where f is the frequency of one of the signals of a first frequency and second frequency;

means coupled to the output of each of said first dual gate mixer circuit and second dual gate mixer circuit for combining the first signal outputted from the first dual gate mixer circuit and the second signal outputted from the second dual gate mixer circuit to cancel each other, and to combine the third signal outputted from the first dual gate mixer circuit and the fourth signal outputted from the second dual gate mixer circuit to cancel each other.

6. A double-balanced mixer as in claim 5 wherein the phase shifter has a voltage gain X given by

X=(L.sub.A /C.sub.C).sup.1/2 /(2·CR.sub.C).

7. A double-balanced mixer circuit as in claim 5 wherein said first dual gate mixer circuit also produces at its output fifth and sixth signals which are respectively the sum and difference of said first and third signals and further outputs said signal of a first frequency, and said second dual gate mixer circuit also produces at its output seventh and eighth signals which are respectively the sum and difference of said second and fourth signals and further outputs said signal of a second frequency, and

said combining means cancelling said fifth and seventh signals outputted respectively from said first and second dual gate mixer circuits and cancelling said sixth and eighth signals outputted respectively from said first and second dual gate mixer circuits and producing a signal having a frequency corresponding to a selected one of the sum of and the difference between the signal of a first frequency and the signal of a second frequency.

8. A double-balanced mixer circuit as in claim 5 wherein said means for combining also has an output terminal at which it produces a resultant signal whose frequency is a selected one of the sum of and the difference between the signal of a first frequency and the signal of a second frequency.

9. A double-balanced mixer circuit for mixing a first input signal of a first frequency and a second input signal of a second frequency comprising:

(L.sub.A ·C.sub.C).sup.-1/2 =2πf

and where f is one of the signals of the first frequency and second frequency;

a coupler for combining the output signals of the first dual gate mixer circuit and the output signals of the second dual gate mixer circuit and to output to an output terminal a resultant signal whose frequency is a selected one of the sum of and the difference between the signal of a first frequency and the signal of a second frequency for supply to an external circuit; and

wherein the impedance of the components forming the coupler plus the output impedances of the FET of the first mixer circuit and the second mixer circuit is greater than the impedance of an external circuit connected to the coupler output terminal.

10. A double-balanced mixer as in claim 9 wherein the phase shifter has a voltage gain X given by

X=(L.sub.A /C.sub.C).sup.1/2 /(2·CR.sub.C).

11. A double-balanced mixer circuit as in claim 9 wherein said coupler includes means for combining the first signal outputted from said first dual gate mixer circuit and the second signal outputted from said second dual gate circuit to cancel each other, and the first signal outputted from said first dual gate mixer circuit and the fourth signal outputted from said second dual gate mixer circuit to cancel each other.