|Publication number||US5530873 A|
|Application number||US 08/100,753|
|Publication date||25 Jun 1996|
|Filing date||2 Aug 1993|
|Priority date||2 Oct 1992|
|Also published as||CA2103988A1, CA2103988C, DE69325334D1, DE69325334T2, EP0593154A2, EP0593154A3, EP0593154B1|
|Publication number||08100753, 100753, US 5530873 A, US 5530873A, US-A-5530873, US5530873 A, US5530873A|
|Original Assignee||Hudson Soft Co. Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (78), Classifications (13), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to a method and an apparatus for processing interruption and, more particularly, to an information processing method and an information processing apparatus which responds to external processing such as interruption in a computer system.
An information processing apparatus comprises various registers for informing a system of a hardware structure or data format, and having specific areas on a memory for administrating processing status by the system.
If the contents of the routine followed by the registers are unduly broken off, the system does not work properly. Even if control is shifted to an external processing such as by an interruption, the contents of the registers can be utilized even at a routine for a jumped destination.
In an ordinary system, however, a former status is broken off, because the processing for the jumped destination uses the registers at the routine. Therefore, when the processing shifts to an external routine, the contents of the registers are preserved, and the control must be returned to the original routine, after the preserved registers are restored to the original state at the time of the return to the original routine.
FIG. 1 shows the shift of controls at an interruption process, and the state of registers at that time. When the interruption occurs, the control of a CPU shifts to an interruption routine. When the interruption finishes, the control usually returns to an instruction following an instruction which caused the interruption.
At this time, the registers are restored to their state at which the interruption started, so that the processing of the original routine continues with the ordinary operation routine subsequent to operation which occurred just prior to the start of the interruption. The preservation of the registers in the state they were in at the interruption routine is carried out for only the registers to be used at the interruption routine. There is no necessity to carry it out for all registers.
At any rate, a conventional information processing apparatus is provided with a memory having a work area for preserving the contents of the registers at interruption routine, wherein the preserved contents are broken off in the work area at the end of the interruption routine. For this reason, the store of the contents and the restore thereof are repeated in the work area each time there is an interruption routine.
In the case of a computer game machine, subsequent image process must be carried out during V and H blanks (vertical and horizontal retrace periods) having no image on a video screen. Even more, the process is an interruption process such as V blank interruption, H blank interruption, etc.
FIG. 2 shows an image display on a TV screen realized by scanning lines.
The scanning line runs left to right, and, when it reaches to the right end, it returns to the left end during a horizontal retrace period having no displayed image on the screen. On the other hand, the scanning line moves from the top to the bottom of the displayed image. When it reaches the bottom, it returns to the top of the image during a vertical retrace period having no displayed image on the screen.
Even a relatively long V blank occurring once in a 1/60 sec. period has a period of 3/242 sec. The H blank is extremely short as approximately 10M sec. Therefore, a time for the store and restore of registers is not negligible, because the processing of images to be next displayed must be done in these short periods. Therefore, there is a disadvantage in the conventional information processing apparatus in that a part of the process to be carried out in the retrace periods is omitted.
Accordingly, it is an object of the invention to provide a method and an apparatus for processing an interruption in which the store and the restore of registers are carried out with high speed at interruption routine.
According to a feature of the invention, a method for processing the interruption, comprises the steps of:
decoding an instruction of the interruption;
changing a use of an ordinary register to a use of a shadow register, a content of the ordinary register being held;
processing the interruption by using a content or routine in the shadow register; and
returning to the use of the ordinary register, following the end of the interruption routine.
According to another feature of the invention, an apparatus for processing an interruption, comprises:
a CPU for processing the interruption;
an ordinary register for storing a predetermined content; and
a shadow register for storing a content or routine necessary for carrying out the interruption, the shadow register being provided in the CPU;
wherein the shadow register is used, when the interruption is processed by the CPU.
A process to be carried out at the time of the jump to the interruption routine is defined as prologue and a process to be carried out at the time of the return to the jump source is defined as epilogue.
For the prologue,
(1) the store of registers, and,
(2) an initial value-set of a register to be used at the interruption routine are carried out, and
for the epilogue,
(3) the restore of the registers is carried out.
The above process is carried out each time of the shift to interruption routine. At the same routine, the same process is normally repeated. If a part of the process can be omitted, the process can be increased in speed.
In accordance with the above considerations the invention provides a CPU with a shadow register, so that interruption process starts without access to a register at the occurrence of the interruption.
The number of registers is large, and only a register to be used mainly at the time of the interruption routine is a shadow register. FIG. 3 shows a position of the shadow register.
When the control shifts to the interruption processing routine, a portion of the ordinary registers is changed to a shadow register, and a register (the portion in FIG. 3) corresponding to the shadow register can be no longer used.
Consequently, the store and the restore of a register at each time of occurrence is of interruptions become unnecessary, and there is no necessity to initialize a content of the shadow register, when the content of the shadow register is used at the former state.
The invention will be explained in more detail in conjunction with the appended drawings, wherein:
FIG. 1 is an explanatory diagram showing a conventional interruption processing, and the transition of a content of a register,
FIG. 2 is an explanatory diagram showing H and V blanking,
FIG. 3 is an explanatory diagram showing a position where a shadow register is provided,
FIG. 4 is a block diagram showing a system of a computer game machine in a preferred embodiment according to the invention,
FIG. 5 is an explanatory diagram showing a format of a shadow register included in a CPU in the preferred embodiment,
FIG. 6 is an explanatory diagram showing the invention using an interruption process and a register in the preferred embodiment, and
FIG. 7 is an explanatory diagram showing the interruption process having plurality of steps and a register in the preferred embodiment.
FIG. 4 is a block diagram showing a system for a voice and image processingapparatus in the preferred embodiment according to the invention. A CPU controls each IC (integrated circuit) apparatus represented by rectangularblocks in FIG. 4.
This processing apparatus comprises a game soft storing medium, such as CD-ROM, etc., a CPU of 32 bits, a control unit for transfer-control of image and voice data and for interfacing each apparatus, an image data extension and transformation unit, an image data output unit, a voice dataoutput unit, a video encoder unit, a video display unit, etc. Each unit is an IC apparatus, and has a memory such as K-RAM, M-RAM, R-RAM, V-RAM, etc.
The CPU has a memory control function for controlling the DRAM via a memorysupport, an I/O control function for communicating with various peripheral devices via I/O ports, and an interruption control function, and is provided with a timer, parallel input and output ports, etc.
The video display unit reads display-data written into the V-RAM by the CPU. The read data is supplied to the video encoder unit to be displayed on the screen.
The controller unit has a built-in SCSI controller, into which image and voice data are supplied From an external memory apparatus such as the CD-ROM, etc., the supply being via an SCSI interface. The supplied data are once buffer stored in the K-RAM.
The priority of background image data for a natural picture is determined in the controller unit to be supplied to the video encoder unit by a one dot data unit.
Data-compressed motion picture (full color, pallet) data is supplied to theimage data extension unit. The image data extension unit extends the data, and the extended data is supplied to the video encoder unit.
The video encoder unit carries out the process such as super-impose, color pallet regeneration, special effect, D/A conversion, etc., on data of VDP image, natural picture background image, and motion picture (full color, pallet) supplied from the video display unit, the controller unit, and theimage data extension unit. Image signals encoded by the NTSC converter, to become NTSC signals, are supplied to the screen.
ADPCM video data read from the CD-ROM, etc. is buffer stored in the K-RAM in the same manner as image data, and is supplied to the video data outputunit to be reproduced therein by the controller unit.
In the above embodied apparatus, each unit is an IC apparatus having an independent function. In addition, at each time when an H or V blank interruption occurs, each unit functions in accordance with interruption process during non-display periods.
For this purpose, the CPU is provided with shadow registers, each of which is assigned to a corresponding IC apparatus. FIG. 5 shows how the shadow register are provided to have the same contents therein.
Each ordinary register stores words of 32 bits, and each shadow register has the same formation as that of the ordinary register in a memory of theCPU. In this preferred embodiment, eight shadow registers are prepared to be used during an interruption routine.
When the control shifts to the interruption processing routine corresponding to each IC apparatus, the CPU automatically changes from theordinary registers to the shadow registers corresponding to the IC apparatus.
In this interruption routine, no store and no restore of the registers are carried out. The shadow registers are directly used.
FIG. 6 shows a flow of the operation, in the preferred embodiment. The initial setting of the shadow registers is not set out in the flow chart, because the former state can be used without change. However, there is a case where the initial set thereof is required.
Although FIG. 6 shows a parallel interruption process of the control unit and the image data extension unit, a case where the image data extension unit is called up from the control unit can be processed without problem.
The latter case is explained in FIG. 7, wherein the control is transferred from the control unit to the image data extension unit by generating an interruption. When the control shifts to the interruption routine, the CPUchanges to the shadow registers, so that the preservation state is held in the registers (including shadow registers) at the occurrence of the interruption, corresponding to the state of the shadow registers.
consequently, even if the control is returned from the interruption routineto the former routine, the control can re-start from a state just prior to the occurrence of the interruption, because the contents of the registers have been held.
In case of a computer game machine, an interruption occurs in a hardware system during an H or V blanking period, so that the explanations of the shadow registers have been made in connection with an interruption processso far. However, the concept of the shadow registers can be frequency used for an external process routine.
There are two points for shadow registers in the invention. The first pointis that a special area is provided in a CPU. The second point is that the CPU automatically carries out the change-over to comply with respective processings.
That is, the store and the restore of registers which are carried out in the conventional processing apparatus become unnecessary to be carried outin the invention. It is not necessary to make a sense of shadow registers by a program due to the fact that the change-over is made in a hardware system, so that the same method of using a program as in the conventional processing method can be adopted in the invention.
For this reason, there are advantages in the invention in that processing speed becomes high, and the descriptions or writing of a program becomes simple. Especially, the advantages of the invention are significant in thecase where subsequent image processing must be finished in a short time as required in a television game machine, etc.
Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modification and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4103329 *||28 Dec 1976||25 Jul 1978||International Business Machines Corporation||Data processing system with improved bit field handling|
|US4410939 *||16 Jul 1980||18 Oct 1983||Matsushita Electric Industrial Co. Ltd.||System for program interrupt processing with quasi-stack of register-sets|
|US4434461 *||15 Sep 1980||28 Feb 1984||Motorola, Inc.||Microprocessor with duplicate registers for processing interrupts|
|US4905190 *||7 Aug 1987||27 Feb 1990||Nec Corporation||Multiprogram control information processing system with process roll-in from main memory|
|JPS5933558A *||Title not available|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5640570 *||26 Jan 1996||17 Jun 1997||International Business Machines Corporation||Information handling system for transmitting contents of line register from asynchronous controller to shadow register in another asynchronous controller determined by shadow register address buffer|
|US5701493 *||3 Aug 1995||23 Dec 1997||Advanced Risc Machines Limited||Exception handling method and apparatus in data processing systems|
|US5987258 *||27 Jun 1997||16 Nov 1999||Lsi Logic Corporation||Register reservation method for fast context switching in microprocessors|
|US6128728 *||12 Dec 1997||3 Oct 2000||Micron Technology, Inc.||Virtual shadow registers and virtual register windows|
|US6243804 *||22 Jul 1998||5 Jun 2001||Scenix Semiconductor, Inc.||Single cycle transition pipeline processing using shadow registers|
|US6282638||31 Aug 2000||28 Aug 2001||Micron Technology, Inc.||Virtual shadow registers and virtual register windows|
|US6370640||28 Aug 2000||9 Apr 2002||Micron Technology, Inc.||Virtual shadow registers and virtual register windows|
|US6487654 *||12 Dec 2001||26 Nov 2002||Micron Technology, Inc.||Virtual shadow registers and virtual register windows|
|US6697979 *||21 Jun 2000||24 Feb 2004||Pact Xpp Technologies Ag||Method of repairing integrated circuits|
|US6799269||28 Oct 2002||28 Sep 2004||Micron Technology, Inc.||Virtual shadow registers and virtual register windows|
|US6968452||24 Feb 2003||22 Nov 2005||Pact Xpp Technologies Ag||Method of self-synchronization of configurable elements of a programmable unit|
|US6986028 *||17 Jul 2002||10 Jan 2006||Texas Instruments Incorporated||Repeat block with zero cycle overhead nesting|
|US6990555||24 Jan 2004||24 Jan 2006||Pact Xpp Technologies Ag||Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)|
|US7003660||13 Jun 2001||21 Feb 2006||Pact Xpp Technologies Ag||Pipeline configuration unit protocols and communication|
|US7010667||5 Apr 2002||7 Mar 2006||Pact Xpp Technologies Ag||Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity|
|US7028107||7 Oct 2002||11 Apr 2006||Pact Xpp Technologies Ag||Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like)|
|US7036036||4 Mar 2003||25 Apr 2006||Pact Xpp Technologies Ag||Method of self-synchronization of configurable elements of a programmable module|
|US7174443||31 Jan 2000||6 Feb 2007||Pact Xpp Technologies Ag||Run-time reconfiguration method for programmable units|
|US7210129||28 Sep 2001||24 Apr 2007||Pact Xpp Technologies Ag||Method for translating programs for reconfigurable architectures|
|US7237087||28 May 2002||26 Jun 2007||Pact Xpp Technologies Ag||Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells|
|US7266725||28 Sep 2001||4 Sep 2007||Pact Xpp Technologies Ag||Method for debugging reconfigurable architectures|
|US7444531||5 Mar 2002||28 Oct 2008||Pact Xpp Technologies Ag||Methods and devices for treating and processing data|
|US7480825||3 Sep 2002||20 Jan 2009||Pact Xpp Technologies Ag||Method for debugging reconfigurable architectures|
|US7493478 *||5 Dec 2002||17 Feb 2009||International Business Machines Corporation||Enhanced processor virtualization mechanism via saving and restoring soft processor/system states|
|US7650448||19 Jan 2010||Pact Xpp Technologies Ag||I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures|
|US7657861||23 Jul 2003||2 Feb 2010||Pact Xpp Technologies Ag||Method and device for processing data|
|US7657877||20 Jun 2002||2 Feb 2010||Pact Xpp Technologies Ag||Method for processing data|
|US7782087||24 Aug 2010||Martin Vorbach||Reconfigurable sequencer structure|
|US7822881||26 Oct 2010||Martin Vorbach||Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)|
|US7822968||26 Oct 2010||Martin Vorbach||Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs|
|US7840842||3 Aug 2007||23 Nov 2010||Martin Vorbach||Method for debugging reconfigurable architectures|
|US7844796||30 Aug 2004||30 Nov 2010||Martin Vorbach||Data processing device and method|
|US7849298||12 Jan 2009||7 Dec 2010||International Business Machines Corporation||Enhanced processor virtualization mechanism via saving and restoring soft processor/system states|
|US7899962||1 Mar 2011||Martin Vorbach||I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures|
|US7928763||14 Jul 2010||19 Apr 2011||Martin Vorbach||Multi-core processing system|
|US7996827||16 Aug 2002||9 Aug 2011||Martin Vorbach||Method for the translation of programs for reconfigurable architectures|
|US8058899||13 Feb 2009||15 Nov 2011||Martin Vorbach||Logic cell array and bus system|
|US8069373||15 Jan 2009||29 Nov 2011||Martin Vorbach||Method for debugging reconfigurable architectures|
|US8099618||23 Oct 2008||17 Jan 2012||Martin Vorbach||Methods and devices for treating and processing data|
|US8127061||18 Feb 2003||28 Feb 2012||Martin Vorbach||Bus systems and reconfiguration methods|
|US8145881||24 Oct 2008||27 Mar 2012||Martin Vorbach||Data processing device and method|
|US8156284||24 Jul 2003||10 Apr 2012||Martin Vorbach||Data processing method and device|
|US8156312||19 Jun 2007||10 Apr 2012||Martin Vorbach||Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units|
|US8195856||5 Jun 2012||Martin Vorbach||I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures|
|US8209653||26 Jun 2012||Martin Vorbach||Router|
|US8230411||13 Jun 2000||24 Jul 2012||Martin Vorbach||Method for interleaving a program over a plurality of cells|
|US8250503||17 Jan 2007||21 Aug 2012||Martin Vorbach||Hardware definition method including determining whether to implement a function as hardware or software|
|US8281108||20 Jan 2003||2 Oct 2012||Martin Vorbach||Reconfigurable general purpose processor having time restricted configurations|
|US8281265||19 Nov 2009||2 Oct 2012||Martin Vorbach||Method and device for processing data|
|US8301872||4 May 2005||30 Oct 2012||Martin Vorbach||Pipeline configuration protocol and configuration unit communication|
|US8310274||4 Mar 2011||13 Nov 2012||Martin Vorbach||Reconfigurable sequencer structure|
|US8312200||21 Jul 2010||13 Nov 2012||Martin Vorbach||Processor chip including a plurality of cache elements connected to a plurality of processor cores|
|US8312301||13 Nov 2012||Martin Vorbach||Methods and devices for treating and processing data|
|US8407525||24 Oct 2011||26 Mar 2013||Pact Xpp Technologies Ag||Method for debugging reconfigurable architectures|
|US8429385||19 Sep 2002||23 Apr 2013||Martin Vorbach||Device including a field having function cells and information providing cells controlled by the function cells|
|US8468329||8 Jun 2012||18 Jun 2013||Martin Vorbach||Pipeline configuration protocol and configuration unit communication|
|US8471593||4 Nov 2011||25 Jun 2013||Martin Vorbach||Logic cell array and bus system|
|US8686475||9 Feb 2011||1 Apr 2014||Pact Xpp Technologies Ag||Reconfigurable elements|
|US8686549||30 Sep 2009||1 Apr 2014||Martin Vorbach||Reconfigurable elements|
|US8726250||10 Mar 2010||13 May 2014||Pact Xpp Technologies Ag||Configurable logic integrated circuit having a multidimensional structure of configurable elements|
|US8803552||25 Sep 2012||12 Aug 2014||Pact Xpp Technologies Ag||Reconfigurable sequencer structure|
|US8812820||19 Feb 2009||19 Aug 2014||Pact Xpp Technologies Ag||Data processing device and method|
|US8819505||30 Jun 2009||26 Aug 2014||Pact Xpp Technologies Ag||Data processor having disabled cores|
|US8869121||7 Jul 2011||21 Oct 2014||Pact Xpp Technologies Ag||Method for the translation of programs for reconfigurable architectures|
|US8914590||30 Sep 2009||16 Dec 2014||Pact Xpp Technologies Ag||Data processing method and device|
|US9037807||11 Nov 2010||19 May 2015||Pact Xpp Technologies Ag||Processor arrangement on a chip including data processing, memory, and interface elements|
|US9047440||28 May 2013||2 Jun 2015||Pact Xpp Technologies Ag||Logical cell array and bus system|
|US9075605||17 Oct 2012||7 Jul 2015||Pact Xpp Technologies Ag||Methods and devices for treating and processing data|
|US20030056085 *||28 May 2002||20 Mar 2003||Entire Interest||Unit for processing numeric and logic operations for use in central processing units (CPUS), multiprocessor systems, data-flow processors (DSPS), systolic processors and field programmable gate arrays (FPGAS)|
|US20030093662 *||7 Oct 2002||15 May 2003||Pact Gmbh||Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three-dimensional programmable cell architectures (FPGAS, DPGAS, and the like)|
|US20030200423 *||17 Jul 2002||23 Oct 2003||Ehlig Peter N.||Repeat block with zero cycle overhead nesting|
|US20040111591 *||5 Dec 2002||10 Jun 2004||International Business Machines Corp.||Enhanced processor virtualization mechanism via saving and restoring soft processor/system states|
|US20070074013 *||20 Aug 2004||29 Mar 2007||Lonnie Goff||Dynamic retention of hardware register content in a computer system|
|US20090157945 *||12 Jan 2009||18 Jun 2009||Ravi Kumar Arimilli||Enhanced Processor Virtualization Mechanism Via Saving and Restoring Soft Processor/System States|
|USRE44365||21 Oct 2010||9 Jul 2013||Martin Vorbach||Method of self-synchronization of configurable elements of a programmable module|
|USRE44383||24 Apr 2008||16 Jul 2013||Martin Vorbach||Method of self-synchronization of configurable elements of a programmable module|
|USRE45109||21 Oct 2010||2 Sep 2014||Pact Xpp Technologies Ag||Method of self-synchronization of configurable elements of a programmable module|
|USRE45223||21 Oct 2010||28 Oct 2014||Pact Xpp Technologies Ag||Method of self-synchronization of configurable elements of a programmable module|
|U.S. Classification||710/260, 710/261, 703/26, 712/E09.06, 712/228|
|International Classification||G06F9/48, G06F9/46, G06F9/38|
|Cooperative Classification||G06F9/462, G06F9/3861, G06F9/30116|
|European Classification||G06F9/38H, G06F9/46G2|
|27 Sep 1993||AS||Assignment|
Owner name: HUDSON SOFT CO. LTD., JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TAKANO, TOSHIYA;REEL/FRAME:006738/0028
Effective date: 19930916
|20 Sep 1999||FPAY||Fee payment|
Year of fee payment: 4
|29 Jul 2003||FPAY||Fee payment|
Year of fee payment: 8
|31 Dec 2007||REMI||Maintenance fee reminder mailed|
|25 Jun 2008||LAPS||Lapse for failure to pay maintenance fees|
|12 Aug 2008||FP||Expired due to failure to pay maintenance fee|
Effective date: 20080625