US5386562A - Circular scheduling method and apparatus for executing computer programs by moving independent instructions out of a loop - Google Patents
Circular scheduling method and apparatus for executing computer programs by moving independent instructions out of a loop Download PDFInfo
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- US5386562A US5386562A US07/882,427 US88242792A US5386562A US 5386562 A US5386562 A US 5386562A US 88242792 A US88242792 A US 88242792A US 5386562 A US5386562 A US 5386562A
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F8/40—Transformation of program code
- G06F8/41—Compilation
- G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
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______________________________________ LOOP: ______________________________________ ldc1 $f4,0(r3) addiu r3,r3,8 add.d $f6,$f4,$f12 < 3 cycle interlock > sdc1 $f6,-8(r3) bne r3,r2,LOOP ______________________________________
______________________________________ LOOP: ______________________________________ ldc1 $f4,0(r3) addiu r3,r3,8 add.d $f6,$f4,$f12 bne r3,r2,LOOP < 2 cycle interlock > sdc1 $f6,-8(r3) ______________________________________
TABLE 1 ______________________________________ Instruction Object Number Code Meaning ______________________________________ I ldc1 $f4,0(r3) Take the value stored in the address indicated by the contents of register r3, after augmenting the address by 0, and store it in variable f4 II addiu $r3,r3,8 Increment the contents of register r3 by 8 and store back into r3 III add.d $f6,$f4,$f12 Add, double precision, the numbers in variables f4 and f12 (f12 was previously defined as the constant "c") and store in f6 IV sdc1 $f6,-8(r3) Store the value in variable f6 in the memory location indi- cated by the address in r3, after decrementing the address by 8. V bne r3,r2,LOOP If the contents of r3 is not equal to the contents of r2, branch to the program location indicated by the marker "LOOP", otherwise, exit the loop. ______________________________________
______________________________________ LOOP: ______________________________________ add.d $f6,$f4,$f12 < 3 cycle interlock > sdc1 $f6,-8(r3) bne r3,r2,LOOP ldc1 $f4,0(r3) addiu r3,r3,8 ______________________________________
______________________________________ LOOP: ______________________________________ add.d $f6,$f4,$f12 ldc1 $f4,0(r3) addiu r3,r3,8 bne r3,r2,LOOP sdc1 $f6,-8(r3) ______________________________________
______________________________________ LOOP: addiu r3,r3,8 beq r3,r2,LEND prolog ldc1 $f18,-8,(r3) LBEG: add.d $f16,$f18,$f12 ldc1 $f18,0(r3) addiu r3,r3,8 loop body bne r3,r2,LBEG sdc1 $f16,-16(r3) LEND: add.d $f16,$f18,$f12 < 3 cycle interlock > epilog sdc1 $f16,-S(r3) ______________________________________
TABLE 2 ______________________________________ Percentage Improvement Kernal R3010 R6010 ______________________________________ 1 30 38 2 4 0 3 3 2 4 0 17 5 -1 -2 6 -2 -5 7 36 34 8 17 15 9 43 53 10 0 0 11 0 6 12 0 23 13 0 -2 14 9 13 15 1 0 16 1 0 17 0 0 18 30 17 19 2 -5 20 3 0 21 2 42 22 0 0 23 33 19 24 1 2 ______________________________________
TABLE 3 ______________________________________ % Improvement Benchmark R3010 R6010 ______________________________________ Linpack 0 23 la400 8.6 28 tomcatv (SPEC) 17.3 18.2 nasa7 (SPEC) 5.4 12.5 doduc (SPEC) 3.1 2.2 fpppp (SPEC) 2.4 2.3 ______________________________________
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US07/882,427 US5386562A (en) | 1992-05-13 | 1992-05-13 | Circular scheduling method and apparatus for executing computer programs by moving independent instructions out of a loop |
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Cited By (32)
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---|---|---|---|---|
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US5491823A (en) * | 1994-01-25 | 1996-02-13 | Silicon Graphics, Inc. | Loop scheduler |
US5619675A (en) * | 1994-06-14 | 1997-04-08 | Storage Technology Corporation | Method and apparatus for cache memory management using a two level scheme including a bit mapped cache buffer history table and circular cache buffer list |
WO1997036228A1 (en) * | 1996-03-28 | 1997-10-02 | Intel Corporation | Software pipelining a hyperblock loop |
US5758117A (en) * | 1995-12-14 | 1998-05-26 | International Business Machines Corporation | Method and system for efficiently utilizing rename buffers to reduce dispatch unit stalls in a superscalar processor |
US5794029A (en) * | 1996-08-07 | 1998-08-11 | Elbrus International Ltd. | Architectural support for execution control of prologue and eplogue periods of loops in a VLIW processor |
US5794062A (en) * | 1995-04-17 | 1998-08-11 | Ricoh Company Ltd. | System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization |
US5797013A (en) * | 1995-11-29 | 1998-08-18 | Hewlett-Packard Company | Intelligent loop unrolling |
US5835776A (en) * | 1995-11-17 | 1998-11-10 | Sun Microsystems, Inc. | Method and apparatus for instruction scheduling in an optimizing compiler for minimizing overhead instructions |
US5854933A (en) * | 1996-08-20 | 1998-12-29 | Intel Corporation | Method for optimizing a computer program by moving certain load and store instructions out of a loop |
US5867711A (en) * | 1995-11-17 | 1999-02-02 | Sun Microsystems, Inc. | Method and apparatus for time-reversed instruction scheduling with modulo constraints in an optimizing compiler |
US5887174A (en) * | 1996-06-18 | 1999-03-23 | International Business Machines Corporation | System, method, and program product for instruction scheduling in the presence of hardware lookahead accomplished by the rescheduling of idle slots |
US5924128A (en) * | 1996-06-20 | 1999-07-13 | International Business Machines Corporation | Pseudo zero cycle address generator and fast memory access |
US6044377A (en) * | 1995-11-07 | 2000-03-28 | Sun Microsystem, Inc. | User-defined object type and method of making the object type wherein a file associated with a rule is invoked by accessing the file which generates code at run time |
US6044222A (en) * | 1997-06-23 | 2000-03-28 | International Business Machines Corporation | System, method, and program product for loop instruction scheduling hardware lookahead |
US6253373B1 (en) * | 1997-10-07 | 2001-06-26 | Hewlett-Packard Company | Tracking loop entry and exit points in a compiler |
US20010020294A1 (en) * | 2000-03-03 | 2001-09-06 | Hajime Ogawa | Optimization apparatus that decreases delays in pipeline processing of loop and computer-readable storage medium storing optimization program |
US6289443B1 (en) * | 1998-01-28 | 2001-09-11 | Texas Instruments Incorporated | Self-priming loop execution for loop prolog instruction |
US6305014B1 (en) * | 1998-06-18 | 2001-10-16 | International Business Machines Corporation | Lifetime-sensitive instruction scheduling mechanism and method |
US6314493B1 (en) | 1998-02-03 | 2001-11-06 | International Business Machines Corporation | Branch history cache |
WO2002091177A1 (en) * | 2001-05-08 | 2002-11-14 | Sun Microsystems, Inc. | Transforming variable loops into constant loops |
US20030135848A1 (en) * | 2001-12-21 | 2003-07-17 | Hitachi, Ltd. | Use of multiple procedure entry and/or exit points to improve instruction scheduling |
US20060020925A1 (en) * | 2004-07-10 | 2006-01-26 | Hewlett-Pakard Development Company, L.P. | Analysing a multi stage process |
US20070067201A1 (en) * | 2005-07-15 | 2007-03-22 | Grzegorz Malewicz | Method and system for parallel scheduling of complex dags under uncertainty |
US20070074196A1 (en) * | 2005-09-28 | 2007-03-29 | Matsushita Electric Industrial Co., Ltd. | Compiler apparatus |
US20100050164A1 (en) * | 2006-12-11 | 2010-02-25 | Nxp, B.V. | Pipelined processor and compiler/scheduler for variable number branch delay slots |
US7797692B1 (en) * | 2006-05-12 | 2010-09-14 | Google Inc. | Estimating a dominant resource used by a computer program |
US20100235819A1 (en) * | 2009-03-10 | 2010-09-16 | Sun Microsystems, Inc. | One-pass compilation of virtual instructions |
US20120253482A1 (en) * | 2011-03-29 | 2012-10-04 | Honeywell International Inc. | Function block execution framework |
US20140297997A1 (en) * | 2013-03-14 | 2014-10-02 | Sas Institute Inc. | Automated cooperative concurrency with minimal syntax |
US8966457B2 (en) | 2011-11-15 | 2015-02-24 | Global Supercomputing Corporation | Method and system for converting a single-threaded software program into an application-specific supercomputer |
US11714620B1 (en) | 2022-01-14 | 2023-08-01 | Triad National Security, Llc | Decoupling loop dependencies using buffers to enable pipelining of loops |
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US5481683A (en) * | 1992-10-30 | 1996-01-02 | International Business Machines Corporation | Super scalar computer architecture using remand and recycled general purpose register to manage out-of-order execution of instructions |
US5491823A (en) * | 1994-01-25 | 1996-02-13 | Silicon Graphics, Inc. | Loop scheduler |
US5619675A (en) * | 1994-06-14 | 1997-04-08 | Storage Technology Corporation | Method and apparatus for cache memory management using a two level scheme including a bit mapped cache buffer history table and circular cache buffer list |
US20050268070A1 (en) * | 1995-04-17 | 2005-12-01 | Baxter Michael A | Meta-address architecture for parallel, dynamically reconfigurable computing |
US7493472B2 (en) | 1995-04-17 | 2009-02-17 | Ricoh Company Ltd. | Meta-address architecture for parallel, dynamically reconfigurable computing |
US5794062A (en) * | 1995-04-17 | 1998-08-11 | Ricoh Company Ltd. | System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization |
US6058469A (en) * | 1995-04-17 | 2000-05-02 | Ricoh Corporation | System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization |
US6044377A (en) * | 1995-11-07 | 2000-03-28 | Sun Microsystem, Inc. | User-defined object type and method of making the object type wherein a file associated with a rule is invoked by accessing the file which generates code at run time |
US5835776A (en) * | 1995-11-17 | 1998-11-10 | Sun Microsystems, Inc. | Method and apparatus for instruction scheduling in an optimizing compiler for minimizing overhead instructions |
US5867711A (en) * | 1995-11-17 | 1999-02-02 | Sun Microsystems, Inc. | Method and apparatus for time-reversed instruction scheduling with modulo constraints in an optimizing compiler |
US5797013A (en) * | 1995-11-29 | 1998-08-18 | Hewlett-Packard Company | Intelligent loop unrolling |
US5758117A (en) * | 1995-12-14 | 1998-05-26 | International Business Machines Corporation | Method and system for efficiently utilizing rename buffers to reduce dispatch unit stalls in a superscalar processor |
US5920724A (en) * | 1996-03-28 | 1999-07-06 | Intel Corporation | Software pipelining a hyperblock loop |
US6016399A (en) * | 1996-03-28 | 2000-01-18 | Intel Corporation | Software pipelining a hyperblock loop |
WO1997036228A1 (en) * | 1996-03-28 | 1997-10-02 | Intel Corporation | Software pipelining a hyperblock loop |
US5887174A (en) * | 1996-06-18 | 1999-03-23 | International Business Machines Corporation | System, method, and program product for instruction scheduling in the presence of hardware lookahead accomplished by the rescheduling of idle slots |
US5924128A (en) * | 1996-06-20 | 1999-07-13 | International Business Machines Corporation | Pseudo zero cycle address generator and fast memory access |
US5794029A (en) * | 1996-08-07 | 1998-08-11 | Elbrus International Ltd. | Architectural support for execution control of prologue and eplogue periods of loops in a VLIW processor |
US5854933A (en) * | 1996-08-20 | 1998-12-29 | Intel Corporation | Method for optimizing a computer program by moving certain load and store instructions out of a loop |
US6044222A (en) * | 1997-06-23 | 2000-03-28 | International Business Machines Corporation | System, method, and program product for loop instruction scheduling hardware lookahead |
US6253373B1 (en) * | 1997-10-07 | 2001-06-26 | Hewlett-Packard Company | Tracking loop entry and exit points in a compiler |
US6289443B1 (en) * | 1998-01-28 | 2001-09-11 | Texas Instruments Incorporated | Self-priming loop execution for loop prolog instruction |
US6314493B1 (en) | 1998-02-03 | 2001-11-06 | International Business Machines Corporation | Branch history cache |
US6305014B1 (en) * | 1998-06-18 | 2001-10-16 | International Business Machines Corporation | Lifetime-sensitive instruction scheduling mechanism and method |
US6993756B2 (en) * | 2000-03-03 | 2006-01-31 | Matsushita Electric Industrial Co., Ltd. | Optimization apparatus that decreases delays in pipeline processing of loop and computer-readable storage medium storing optimization program |
US20010020294A1 (en) * | 2000-03-03 | 2001-09-06 | Hajime Ogawa | Optimization apparatus that decreases delays in pipeline processing of loop and computer-readable storage medium storing optimization program |
US20040015915A1 (en) * | 2001-05-08 | 2004-01-22 | Sun Microsystems, Inc. | Method of transforming variable loops into constant loops |
US6988266B2 (en) | 2001-05-08 | 2006-01-17 | Sun Microsystems, Inc. | Method of transforming variable loops into constant loops |
WO2002091177A1 (en) * | 2001-05-08 | 2002-11-14 | Sun Microsystems, Inc. | Transforming variable loops into constant loops |
US20030135848A1 (en) * | 2001-12-21 | 2003-07-17 | Hitachi, Ltd. | Use of multiple procedure entry and/or exit points to improve instruction scheduling |
US20060020925A1 (en) * | 2004-07-10 | 2006-01-26 | Hewlett-Pakard Development Company, L.P. | Analysing a multi stage process |
US20070067201A1 (en) * | 2005-07-15 | 2007-03-22 | Grzegorz Malewicz | Method and system for parallel scheduling of complex dags under uncertainty |
US7908163B2 (en) | 2005-07-15 | 2011-03-15 | The Board Of Trustees Of The University Of Alabama | Method and system for parallel scheduling of complex dags under uncertainty |
US20070074196A1 (en) * | 2005-09-28 | 2007-03-29 | Matsushita Electric Industrial Co., Ltd. | Compiler apparatus |
US7827542B2 (en) * | 2005-09-28 | 2010-11-02 | Panasonic Corporation | Compiler apparatus |
US7797692B1 (en) * | 2006-05-12 | 2010-09-14 | Google Inc. | Estimating a dominant resource used by a computer program |
US20100050164A1 (en) * | 2006-12-11 | 2010-02-25 | Nxp, B.V. | Pipelined processor and compiler/scheduler for variable number branch delay slots |
US8959500B2 (en) * | 2006-12-11 | 2015-02-17 | Nytell Software LLC | Pipelined processor and compiler/scheduler for variable number branch delay slots |
US8561040B2 (en) | 2009-03-10 | 2013-10-15 | Oracle America, Inc. | One-pass compilation of virtual instructions |
US20100235819A1 (en) * | 2009-03-10 | 2010-09-16 | Sun Microsystems, Inc. | One-pass compilation of virtual instructions |
US8983632B2 (en) * | 2011-03-29 | 2015-03-17 | Honeywell International Inc. | Function block execution framework |
US20120253482A1 (en) * | 2011-03-29 | 2012-10-04 | Honeywell International Inc. | Function block execution framework |
US20170017476A1 (en) * | 2011-11-15 | 2017-01-19 | Global Supercomputing Corporation | Method and system for converting a single-threaded software program into an application-specific supercomputer |
US8966457B2 (en) | 2011-11-15 | 2015-02-24 | Global Supercomputing Corporation | Method and system for converting a single-threaded software program into an application-specific supercomputer |
US9495223B2 (en) | 2011-11-15 | 2016-11-15 | Global Supercomputing Corporation | Method and system for converting a single-threaded software program into an application-specific supercomputer |
US10146516B2 (en) * | 2011-11-15 | 2018-12-04 | Global Supercomputing Corporation | Method and system for converting a single-threaded software program into an application-specific supercomputer |
US10642588B2 (en) | 2011-11-15 | 2020-05-05 | Global Supercomputing Corporation | Method and system for converting a single-threaded software program into an application-specific supercomputer |
US11132186B2 (en) | 2011-11-15 | 2021-09-28 | Global Supercomputing Corporation | Method and system for converting a single-threaded software program into an application-specific supercomputer |
US11579854B2 (en) | 2011-11-15 | 2023-02-14 | Global Supercomputing Corporation | Method and system for converting a single-threaded software program into an application-specific supercomputer |
US20140297997A1 (en) * | 2013-03-14 | 2014-10-02 | Sas Institute Inc. | Automated cooperative concurrency with minimal syntax |
US9582256B2 (en) * | 2013-03-14 | 2017-02-28 | Sas Institute Inc. | Automated cooperative concurrency with minimal syntax |
US11714620B1 (en) | 2022-01-14 | 2023-08-01 | Triad National Security, Llc | Decoupling loop dependencies using buffers to enable pipelining of loops |
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