|Publication number||US5070473 A|
|Application number||US 07/077,442|
|Publication date||3 Dec 1991|
|Filing date||24 Jul 1987|
|Priority date||22 Aug 1986|
|Publication number||07077442, 077442, US 5070473 A, US 5070473A, US-A-5070473, US5070473 A, US5070473A|
|Inventors||Makoto Takano, Yasuhiko Hoshi, Keiichi Kurakazu, Shiro Baba|
|Original Assignee||Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (4), Non-Patent Citations (4), Referenced by (48), Classifications (5), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to a microprocessor, and more particularly, technology to be utilized in a microprocessor incorporating a program wait circuit for asynchronous data aquisition. The invention is particularly relevant to interfacing a central processor with a direct memory interface device.
In microprocessors of the 68000 series variety which incorporate a program wait circuit, data from peripheral devices, such as memory, is received in the following manner. At a state "0", specified by a clock (machine cycle) signal, an address bus is taken to a high impedance state. A read/write signal ("R/W") is made high to indicate the presence of the read cycle.
At a state "2", an address strobe signal (typically "AS") is made active, which is defined at a low level. This indicates that an effective address signal exists on the address bus. Peripheral devices, such as memory, together with the address bus, receive the address strobe signal, and individually determine whether they are selected. When a device is selected, it becomes active, and transmits an appropriate data signal onto the data bus.
A wait time of a program wait circuit is set, taking into account access time necessary for the particular selected device, such as the time necessary to access a selected memory. That is, one or more wait cycles are set for a selected device having a relatively low access speed.
At completion of the wait cycles, it is presumed that effective data exists on the data bus, and the data is read therefrom.
A microprocessor incorporating a program wait circuit as above-described is disclosed in, for example, "Hitachi Microcomputer Data Book, 8 bits/16 bits Microprocessor", pages 462-463, published in Sept. 1985 by Hitachi, Ltd.
When a bus control or bus master system is contained solely in a microprocessor, the selected device can be accessed without severe problems. However, if the system incorporates a device such as a slave microprocessor or a direct memory access device, a control circuit will be necessary to command the above-mentioned wait cycle.
An object of the invention is to provide a simplified microprocessor system, with which a memory access control system for use in a multiple controlled systems memory is to be implemented.
In accordance with the present invention, a wait signal is formed by an incorporated program wait circuit. The wait signal is transmitted to an external terminal. A device serves as a bus master which is utilized in a wait operation, and which works in conjunction with the wait signal.
In accordance with another aspect of the present invention, an output circuit enables wired logic configurations which are used as drive circuits to transmit a wait signal formed by the incorporated program wait circuit. The wait signal is then supplied from an external terminal, thereby allowing for variation in a wait function of a microprocessor.
An advantage of the present invention is the provision of a simplified device in which a plurality of devices may be more simply accessed to a bus by implementation of a bus control device.
Another advantage of the present invention is the provision of a microprocessor having variable wait function, which provides for access to slower and faster memory devices.
Another advantage of the present invention is that the program wait circuit can be utilized in a wait operation of a slave microprocessor or a direct memory access control device.
Further advantages will become apparent to one of ordinary skill in the art after a reading and understanding of the following specification.
The invention may take physical form in certain parts and arrangement of parts, a preferred embodiment of which will be described in detail in this specification and illustrated in the accompanying drawings which form a part hereof, and wherein:
FIG. 1 is a block diagram illustrating an embodiment of a bus control system of the present invention;
FIG. 2 is a block diagram illustrating another embodiment of the invention of FIG. 1;
FIGS. 3A and 3B are timing charts illustrating operation of the device of FIG. 2; and
FIG. 4 is a diagram illustrating an embodiment of the counter controller 2 shown in FIG. 2.
FIG. 1 is a block diagram illustrating a first embodiment of the present invention. A microprocessor MPU is suitably a microprocessor of the 68000 series. Incorporated therein is a central processor unit CPU, and a program wait circuit WAITC. A direct memory access control unit DMAC functions as a bus controller or master. Memory devices M1 and M2 are, for example, RAM (random access memory) or ROM (read only memory) devices. At least one is a memory device having relatively low access speed, such as is typically found in dynamic RAM. An input/output device I/O is, for example, a mass storage device such as a floppy disc memory.
The microprocessor MPU, the direct memory access control device DMAC, the memory devices M1, M2, and the input/output device I/O, are mutally connected by a bus system, BUS, comprised of an address bus, a data bus, a control bus or the like.
A suitable microprocessor MPU, which incorporates the program wait circuit WAITC, is readily available from the assignee of the present application, and is identified as product no. "HD64180."
The program wait circuit WAITC inserts a wait signal during selected machine cycles, defined as a preselected number of clock cycles, during accesses to relatively low speed memory devices such as the input/output device I/O as above-described. In this embodiment, the program wait circuit WAITC supplies a wait signal through an OR gate circuit G to the central processing unit CPU. The program wait circuit WAITC also supplies the wait signal to a bus made by transmitting it through a drive circuit DV to an external circuit.
A wait control signal output through the drive circuit DV is supplied to the direct memory access control device DMAC in the micropcomputer system of the embodiment. The drive circuit DV is suitably comprised of an open drain output circuit so that the wait signal can be supplied from an external terminal; i.e. wired logic at the output terminal. Consequently, a wait signal supplied from the external terminal may also be supplied through the OR gate circuit G to the central processing unit CPU. In this fashion, a wait period for the CPU may be supplemented by an external device such as the DMAC.
The program wait circuit WAITC receives a signal from the BUS, and directs the direct memory access control circuit DMAC to become a bus master.
The direct memory access control circuit DMAC functions as a timing means, and undertakes a microcomputer function as it assumes the functions of a bus master from the microprocessor MPU. After it commences this function, the DMAC oversees data transfers among such devices as memory devices M1, M2, and the input/output device I/O. If the access speed of the memory device M1 or M2 or the input/output device I/O is relatively slow, insertion of the above-mentioned wait signal by the circuit WAITC is required. In this embodiment, even when the direct memory access control device DMAC obtains bus use priority in place of the microprocessor MPU, the program wait circuit WAITC is started at a prescribed time. The program wait circuit WAITC generates a wait signal WAIT corresponding to a speed (access cycle) of the memory device or the input/output device to which access of the direct memory access control device DMAC is desired, and supplies it through the drive circuit DV to the direct memory access control device.
The direct memory access control device DMAC transmits the prescribed timing signal and address signal corresponding to the machine cycle. A peripheral device, such as a memory, receives the address signal and discerns whether it is selected. On a determination that is selected, the selected device is rendered active, and transmits a read signal to the data bus. The timing for memory access is therefore dictated by a combination of the direct memory access control.
The program wait circuit transmits a wait signal corresponding to a particular access time of the selected device. Consequently, the direct memory access control device DMAC executes one or more additional wait cycles prior to the data transfer cycle, and then deems that effective data exists on the data bus and enables a read thereof. That is, insertion of the assigned wait cycle extends the machine cycle (bus cycle).
FIG. 2 is a block diagram illustrating another embodiment of the present invention. A microprocessor MPU, a direct memory access control circuit DMAC, and a memory, are coupled through a system BUS. A wait circuit WAITC, incorported in the microprocessor MPU, includes an address comparator 1 for discerning whether an address signal on BUS is included in a prescribed address region; a counter controller 2 for determining the wait cycle number; a counter 3 for determining a start timing and an end timing of the wait signal; and a wait signal generator 4 for forming a wait signal. The counter 3 is a down counter, with its initial value being supplied by the counter controller 2.
A count down of counter 3 is started so as to correspond to a fall timing of an address strobe signal AS. From the fall timing of the address strobe signal AS until the counter value becomes 0, the wait signal generator 4 forms the wait signal WAIT at a low level.
The wait signal WAIT is transmitted through an output circuit DV' and an output terminal T1 for connection outside of the microprocessor. The wait signal WAIT, transmitted from the microprocessor MPU, is supplied through BUS to the direct memory access control device DMAC. A period of one machine cycle of the direct memory access control device DMAC is added corresponding to a period when the wait signal WAIT is at a low level.
The address strobe signal AS is supplied from the direct memory access control device DMAC to a memory to be accessed. If the address strobe signal AS falls, the accessed memory recognizes that the address signal on the BUS is established and it is taken in. Subsequently, a data read or write operation is executed. The address strobe signal AS is taken through the terminal T2 into the microprocessor MPU, and used to govern the operation timing of counter 3.
FIG. 3A shows a timing chart, illustrating when the direct memory access control device DMAC reads data from a high-speed memory coupled with the BUS. In the embodiment, a period of one machine cycle is defined as three cycles of the reference inner clock. In the first cycle T1, the direct memory access control circuit DMAC transmits an address signal onto the bus. After the address signal is transmitted, the address strobe signal AS falls, thereby the high-speed memory takes the address signal inside and a data read operation is started. Subsequently, in the third cycle T3, the read data is transmitted onto the BUS. The wait signal WAIT is made high during the period from the first cycle T1 to the third cycle T3. The address comparator 1, within the wait circuit WAITC, supervises the address signal through the terminal T3 so that the access state of the high-speed memory can be recognized. The counter controller 2 correspondingly sets the inital value 0 to the counter 3.
FIG. 3B illustrates the timing when the direct memory access control device DMAC reads data from a low-speed memory coupled with BUS. In the embodiment, a period of one machine cycle is defined at five cycles of the reference inner clock. That is, wait cycles TW1 and TW2 are added between the second cycle T2 and the third cycle T3, which corresponds to the operation speed of the low-speed memory. In the first cycle T1, the direct memory access control circuit DMAC transmits the address signal onto the bus. The address signal is transmitted and then the address strobe signal AS falls. The low-speed memory thereby takes in the address signal and a data read operation is commenced. The address comparator 1 within the wait circuit WAITC supervises the address signal so that an access state of the low-speed memory can be recognized.
The counter controller 2 correspondingly sets the initial value 2 to the counter 3. The initial value can be arbitrarily set to correspond to the operation speed of the accessed memory. As a result, the wait signal WAIT is made low during a period of approximately two cycles from the fall timing of the address strobe signal AS. Level detection timing of the wait signal WAIT is made of the fall time of clock after the second cycle T2. That is, since the wait signal WAIT is low at the fall time T1 of clock in the second cycle T2, the first wait cycle TW1 is added. Next, since the wait signal WAIT is low at the fall time T2 of clock in the wait cycle TW1, the second wait cycle TW2 is added. Next, since the wait signal WAIT is made high at the fall time T3 of clock in the second wait cycle TW2, the wait cycle is not added. During the wait cycle, the address signal and the address strobe signal AS maintain the previous state. Data is transmitted onto the BUS until the third cycle T3. Consequently, the direct memory access control device DMAC can take data on the bus in the third cycle T3 as effective data.
FIG. 4 is a block diagram of an embodiment of the counter controller 2 of FIG. 2. In the embodiment, four registers 1-4 are implemented to store the wait cycle number. The wait cycle number is written by the CPU. For example, in the register 1, "00" is written to indicate that the wait cycle number is 0; in the register 2, "01" is written to indicate that the wait cycle number is 1; in the register 3, "10" is written to indicate that the wait cycle number is 2; and in the register 4, "11" is written to indicate that the wait cycle number is 3. In order to select any of the registers, AND gates AG1-AG8 and OR gates OG1, OG2 are installed. For example, among output signal lines 1-4 of the address comparator 1, signal line 3 is made high. The AND gates AG3 and AG7, to which the signal line 3 is connected at respective input terminals, are thereby selected. As a result, the content "10" of the register 3 is supplied through the OR gates OG1, OG2 to the counter 3.
In FIG. 2, the CPU can execute the wait cycle not only by the wait signal formed at the wait circuit WAITC, but also by the wait signal formed outside of the MPU. That is, the terminal T1 serves an an input/output common terminal, and the output drive DV' enters a high-impedance state during the wait signal input. The wait signal is supplied through the gate G to the CPU. If at least one of the two input signals of the gate G is made low, a low output signal is formed.
In the microcomputer, which includes the microprocessor MPU, which in turn incorporates the program wait circuit WAITC as above-dscribed, when a direct memory access control device DMAC or a slave microprocessor serving as a bus master exists, the program wait circuit WAITC, incorporated in the master microprocessor, is utilized thereby simplifying the system. The circuit WAITC is disenabled when another device adopts the function of the bus master. Consequently, even if the program wait circuit WAITC is used in another device acting as a bus master, no problems will be produced.
Further, the signal formed by the program wait circuit WAITC is transmitted to the external terminal by the drive circuit DV so as to enable the wired logic. Thereby, if necessary, the microprocessor MPU can perform a wait operation from an externally installed wait control circuit.
Effects obtained from the above-mentioned embodiments are as follows:
(1) A wait signal formed by the incorporated program wait circuit is transmitted to an external terminal. A device to serve as a bus master, such as a slave microprocessor or a direct memory access control device, can be utilized in the wait operation. The microcomputer system comprised of a plurality of devices to be made into a bus master can be simplified.
(2) Output circuits to enable wired logic, such as in open drain configurations are used as drive circuits to transmit a wait signal formed by the incorporated program wait circuit to an external terminal. The wait signal can thereby be supplied from the external terminal. The wait function in the microprocessor may therefor be varied.
Various modifications of the subject device are easily implemented. The bus is adaptable to function such that a data signal and an address signal are transmitted during a time sequence. That is, the slave processor or the direct memory access control device may transmit address and data in a time division system to the address bus of the microprocessor. Further, the terminal to which output signal of the program wait circuit and the terminal which is installed, if necessary, and to which wait signal is supplied from outside, may be independent of each other.
The invention can be widely utilized in a microprocessor incorporating a program wait circuit.
Effects obtained by the invention are briefly described as follows. A wait signal formed by the incorporated program wait circuit is transmitted to the external circuit. Thereby a device to serve as another bus mask, such as a slave microprocessor or a direct memory access control device, can be utilized in the wait operation and the system can thus be simplified.
The invention has been described with reference to preferred embodiments. Obviously, modifications and alterations will occur to others upon reading and understanding of this specification. It is intended that all such modifications and alterations be included insofar as they come within the scope of the claims or the equivalents thereof.
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|International Classification||G06F13/42, G06F13/28|
|17 Jun 1991||AS||Assignment|
Owner name: HITACHI MICROCOMPUTER ENGINEERING LTD., JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:TAKANO, MAKOTO;HOSHI, YASUHIKO;KURAKAZU, KEIICHI;AND OTHERS;REEL/FRAME:005736/0748
Effective date: 19870803
Owner name: HITACHI, LTD., JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:TAKANO, MAKOTO;HOSHI, YASUHIKO;KURAKAZU, KEIICHI;AND OTHERS;REEL/FRAME:005736/0748
Effective date: 19870803
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