US5037766A - Method of fabricating a thin film polysilicon thin film transistor or resistor - Google Patents

Method of fabricating a thin film polysilicon thin film transistor or resistor Download PDF

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US5037766A
US5037766A US07/466,583 US46658390A US5037766A US 5037766 A US5037766 A US 5037766A US 46658390 A US46658390 A US 46658390A US 5037766 A US5037766 A US 5037766A
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layer
thin film
polysilicon
fabricating
resistor
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US07/466,583
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Ting S. Wang
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Industrial Technology Research Institute ITRI
Chunghwa Picture Tubes Ltd
Chi Mei Optoelectronics Corp
Hannstar Display Corp
AU Optronics Corp
Quanta Display Inc
TPO Displays Corp
Prime View International Co Ltd
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Assigned to INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, PRIME VIEW INTERNATIONAL CO., LTD., AU OPTRONICS CORP., CHUNGHWA PICTURE TUBES, LTD., TOPPOLY OPTOELECTRONICS CORP., CHI MEI OPTOELECTRONICS CORP., HANNSTAR DISPLAY CORP., QUANTA DISPLAY INC. reassignment INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/136—Resistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/922—Diffusion along grain boundaries
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/98—Utilizing process equivalents or options

Definitions

  • polysilicon thin film transistor has received a great deal of attention for its application for high packing density three-dimension integrated circuit, as described by T. Ohzone, et al in "An 8K ⁇ 8 Bit Static MOS RAM Fabricated by n-MOS/n-well CMOS Technology" in the IEEE Journal of Solid State Circuits, Vol. SC-15. October 1980, pp. 854-861.
  • the size of polysilicon thin film transistor must be scaled down and the threshold voltage must be kept as low as possible.
  • Ohzone cannot be used to scale down the size of polysilicon thin film transistor, because this method increases the threshold voltage of the polysilicon thin film transistor. As a result, additional lithographic processes are needed to mask the transistor region while implanting with oxygen the resistor region on the polysilicon thin film.
  • the object of the present invention is to eliminate the dopant lateral diffusion along the grain boundary from a highly doped region to the undoped intrinsic region. Another object of this invention is to enable the scaling down of the dimensions of thin film polysilicon resistors and transistors. Also an object of the present invention is to decrease the threshold voltage of a thin film field effect transistor. Still another object of the present invention is to fabricate the polysilicon thin film resistor and thin film transistor on the same layer without further lithographic processes.
  • a double layered polysilicon structure is used.
  • One layer is a highly doped layer which is used as an electrodes; the other is an intrinsic layer, used as the resistor layer or the channel layer of a MOS transistor.
  • Oxygen treatment is applied at low temperature after the first highly doped polysilicon electrode is defined, and before the second layer is deposited. The oxygen then diffuses into the surface and grain boundary of the first highly doped polysilicon and blocks the lateral diffusion of the dopant from the first highly doped polysilicon to the second intrinsic polysilicon during subsequent high temperature process. Then, the second polysilicon, free from oxygen, can be used as a high resistivity resistor or a channel layer in a thin film transistor without incurring high threshold voltage.
  • FIG. 1 is the cross section view of the double polysilicon thin film resistor to which this invention applies.
  • FIG. 2 is the cross section view of the double polysilicon thin film transistor to which this invention applies.
  • FIG. 3 is the process flow of a double polysilicon structure and the mechanism of oxygen treatment according to this invention.
  • FIG. 4 is a plot of the resistivity versus the length of the resistor, showing that resistivity of short length resistor is not degraded for long oxygen treatment time.
  • FIG. 5 is the drain current versus gate voltage characteristics of a thin film transistor processed according to the present invention.
  • FIG. 1 the cross section of a double layered polysilicon thin film resistor is shown.
  • a highly doped layer 1 is doped by arsenic (As) or phosphorus (P), and is used as an electrode of a resistor.
  • a second polysilicon layer 2 is of intrinsic type and is used as a highly resistive resistor.
  • a substrate 3 can be any kind of insulator.
  • the highly doped polysilicon 1 is defined before the undoped intrinsic polysilicon layer 2 is deposited.
  • FIG. 2 the cross section of a double layered polysilicon thin film transistor is shown.
  • a highly doped polysilicon layer 11, similar to layer 1 in FIG. 1, is used as a source/drain electrode of a transistor.
  • the channel region is formed by the undoped intrinsic polysilicon layer 12 similar to the resistor 2 layer in FIG. 1.
  • a gate insulator layer 14 is deposited, and a gate electrode 15, which is a conductive layer, is deposited and defined.
  • FIG. 3 The method of scaling down the dimension of the thin film resistor in FIG. 1 and the thin film transistor in FIG. 2 is described in FIG. 3.
  • an oxygen treatment is performed at low temperature (400° C.) for 5 to 10 minutes.
  • the oxygen diffuses into the surface and the grain boundaries, depicted as grids 6 of polysilicon 1, to block the doped atoms from diffusing from the highly doped polysilicon 1 into the intrinsic polysilicon 2 through the grain boundaries 6.
  • the oxygen molecules are lodged along the grain boundaries as depicted by dots in FIG. 3(b).
  • the second polysilicon layer is deposited, the oxygen molecules remain in place as depicted in FIG. 3(c).
  • FIG. 4 The effect of oxygen treatment on resistor resistivity (defined as resistance per unit length) is shown in FIG. 4. It shows the relationship between resistivity and mask length of the resistor with oxygen treatment time as running parameter. Note that the resistivity of short length resistors drops sharply as oxygen treatment time is decreased for short mask length.
  • FIG. 5 is a plot of drain current (I D ) versus gate voltage (V GS ). Note that I D drops off sharply at about 4 volts. This voltage is then the threshold voltage, and is a reasonable value.
  • the oxygen treatment of this invention has overcome the degradation problem of a short channel thin film MOS transistor.

Abstract

A method of fabricating a double layered polisilicon film with oxygen diffusion for scaled down polysilicon thin film transistor/resistor. The double layered polysilicon film structure includes: a first heavily doped polysilicon layer, produced by Low Pressure Chemical Vapor Deposition (LPCVD) system at about 610 degrees Centigrade, is used as electrodes of resistor or source/drain electrodes of a transistor, and a second layer of polysilicon, deposited by LPCVD at the temperature about 560 degrees Centigrade, is used as a resistor layer or a channel layer of a transistor.
Oxygen treatment is applied at low temperature after the first polysilicon layer is defined. The oxygen present at polysilicon grain boundary blocks the dopant diffusing from the first electrode polysilicon to the second polysilicon which is used as resistor region or a channel region of a transistor. Thus, the resistor can maintain high resistivity and the transistor can maintain low threshold voltage even when they are scaled down.

Description

This application is a division of application Ser. No. 07/280,646 filed Dec. 6, 1988, now abandoned.
BACKGROUND OF THE INVENTION
Highly resistive polysilicon is essential for static RAMs with high packing density and low powder dissipation, but the high dopant diffusion coefficient in polysilicon grain boundary limits the minimum length of the polysilicon thin film resistor to be scaled down. In the coventional technique, as depicted by R. Sakto, et al in "A Novel Scaled Down Oxygen Implanted Polysilicon Resistor for Future Static RAMs" published in the 1986 IEEE International Electron Devices Meeting Proceedings, the scaling down of resistors can be realized by using oxygen as an implantation source. When oxygen is implanted into polysilicon layer, the dopant (such as arsenic) diffusing speed in the polysilicon grain boundary drastically decreases after high temperature treatment, as described by T. Ohzone et al in an article entitled, "Ion-Implanted Thin Polycrystalline Silicon High-Value Resistors for High Density Poly-Load Static RAM Applications", in the IEEE Transactions on Electron Device, Vol. ED-32, September 1985, pp. 1749-1755.
Nowadays, polysilicon thin film transistor has received a great deal of attention for its application for high packing density three-dimension integrated circuit, as described by T. Ohzone, et al in "An 8K×8 Bit Static MOS RAM Fabricated by n-MOS/n-well CMOS Technology" in the IEEE Journal of Solid State Circuits, Vol. SC-15. October 1980, pp. 854-861. For high packing density and high speed operation of three-dimension integrated circuits, the size of polysilicon thin film transistor must be scaled down and the threshold voltage must be kept as low as possible. The oxygen implantation method to scale down the size of polysilicon thin film resistor described by T. Ohzone cannot be used to scale down the size of polysilicon thin film transistor, because this method increases the threshold voltage of the polysilicon thin film transistor. As a result, additional lithographic processes are needed to mask the transistor region while implanting with oxygen the resistor region on the polysilicon thin film.
SUMMARY OF THE INVENTION
The object of the present invention is to eliminate the dopant lateral diffusion along the grain boundary from a highly doped region to the undoped intrinsic region. Another object of this invention is to enable the scaling down of the dimensions of thin film polysilicon resistors and transistors. Also an object of the present invention is to decrease the threshold voltage of a thin film field effect transistor. Still another object of the present invention is to fabricate the polysilicon thin film resistor and thin film transistor on the same layer without further lithographic processes.
These objects are achieved in the present invention by treating the highly doped region with oxygen, which blocks the out-diffusion of the dopant from the highly doped region to the undoped region. In the present invention, a double layered polysilicon structure is used. One layer is a highly doped layer which is used as an electrodes; the other is an intrinsic layer, used as the resistor layer or the channel layer of a MOS transistor. Oxygen treatment is applied at low temperature after the first highly doped polysilicon electrode is defined, and before the second layer is deposited. The oxygen then diffuses into the surface and grain boundary of the first highly doped polysilicon and blocks the lateral diffusion of the dopant from the first highly doped polysilicon to the second intrinsic polysilicon during subsequent high temperature process. Then, the second polysilicon, free from oxygen, can be used as a high resistivity resistor or a channel layer in a thin film transistor without incurring high threshold voltage.
The objects and features of the present invention become more apparent with reference to the following description and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is the cross section view of the double polysilicon thin film resistor to which this invention applies.
FIG. 2 is the cross section view of the double polysilicon thin film transistor to which this invention applies.
FIG. 3 is the process flow of a double polysilicon structure and the mechanism of oxygen treatment according to this invention.
a). after first polysilicon deposition and patterning;
b). after oxygen treatment;
c). after second polysilicon deposition.
FIG. 4 is a plot of the resistivity versus the length of the resistor, showing that resistivity of short length resistor is not degraded for long oxygen treatment time.
FIG. 5 is the drain current versus gate voltage characteristics of a thin film transistor processed according to the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
In FIG. 1, the cross section of a double layered polysilicon thin film resistor is shown. A highly doped layer 1 is doped by arsenic (As) or phosphorus (P), and is used as an electrode of a resistor. A second polysilicon layer 2 is of intrinsic type and is used as a highly resistive resistor. A substrate 3 can be any kind of insulator. The highly doped polysilicon 1 is defined before the undoped intrinsic polysilicon layer 2 is deposited.
In FIG. 2, the cross section of a double layered polysilicon thin film transistor is shown. A highly doped polysilicon layer 11, similar to layer 1 in FIG. 1, is used as a source/drain electrode of a transistor. The channel region is formed by the undoped intrinsic polysilicon layer 12 similar to the resistor 2 layer in FIG. 1. Then a gate insulator layer 14 is deposited, and a gate electrode 15, which is a conductive layer, is deposited and defined.
The method of scaling down the dimension of the thin film resistor in FIG. 1 and the thin film transistor in FIG. 2 is described in FIG. 3. Referring to FIG. 1, after the highly doped polysilicon 1 is defined, an oxygen treatment is performed at low temperature (400° C.) for 5 to 10 minutes. The oxygen diffuses into the surface and the grain boundaries, depicted as grids 6 of polysilicon 1, to block the doped atoms from diffusing from the highly doped polysilicon 1 into the intrinsic polysilicon 2 through the grain boundaries 6. The oxygen molecules are lodged along the grain boundaries as depicted by dots in FIG. 3(b). Afterwards, when the second polysilicon layer is deposited, the oxygen molecules remain in place as depicted in FIG. 3(c). The effect of oxygen treatment on resistor resistivity (defined as resistance per unit length) is shown in FIG. 4. It shows the relationship between resistivity and mask length of the resistor with oxygen treatment time as running parameter. Note that the resistivity of short length resistors drops sharply as oxygen treatment time is decreased for short mask length.
In the transistor application shown in FIG. 2, oxygen treatment only affects the doped polysilicon layer 11, while the undoped intrinsic polysilicon 12 is kept intact. The characteristics of a thin film transistor fabricated according to this invention is shown in FIG. 5. The transistor has a width of 50 micrometers, a length of 2 micrometers, and a channel layer thickness of 80 nanometers. The gate insulator has two layers; 350 Angstroms of silicon dioxide (SiO2) underneath and 300 Angstroms of silicon nitride (Si3 N4) on top. FIG. 5 is a plot of drain current (ID) versus gate voltage (VGS). Note that ID drops off sharply at about 4 volts. This voltage is then the threshold voltage, and is a reasonable value. If there were no oxygen treatment, the threshold voltage would be degraded to a very high value due to encroachment of the dopant from the drain and source into the channel region. Thus, the oxygen treatment of this invention has overcome the degradation problem of a short channel thin film MOS transistor.
While the foregoing description is based on oxygen treatment to create a diffusion blocking region, it is conceivable that other means, such as nitrogen treatment, may also achieve the same result. This invention is by no means limited to an oxygen treatment.

Claims (9)

What is claimed is:
1. A method of fabricating a semiconductor thin film structure having polycrystalline semiconductor first and second layers, comprising the steps of: depositing said first layer on an insulating substrate; heavily doping said first layer; selectively removing said first layer except electrode regions of said structure; subjecting said first layer to a gas treatment, said gas capable of reacting with grain boundary surfaces of said first layer to form a diffusion blocking region in said first layer and to retard out-diffusion of dopant from said first layer; depositing said second layer, undoped and not subjecting to said gas treatment; and heating said structure for making electrical contact between the two said layers.
2. A method of fabricating a semiconductor thin film structure as described in claim 1, wherein said gas is oxygen.
3. A method of fabricating a semiconductor thin film structure as described in claim 2, wherein said oxygen is applied after said first layer has been doped.
4. A method of fabricating a semiconductor thin film structure as described in claim 2, wherein said oxygen treatment is obtained with dilute oxygen at temperatures ranging from 400° C. to 500° C.
5. A method of fabricating a semiconductor thin film structure as described in claim 1, wherein said gas is nitrogen.
6. A method of fabricating semiconductor thin film structure as described in claim 1, wherein said second layer has a high resistivity resistance, and said electrode regions serve as contact electrodes.
7. A method of fabricating a semiconductor thin film structure as described in claim 1, wherein said semiconductor is silicon.
8. A method of fabricating a semiconductor thin film structure as described in claim 1, wherein said dopant for said first layer is arsenic, phosphorus or boron.
9. A method of fabricating a semiconductor thin film structure as described in claim 1, wherein said second layer serves as a channel of a thin film field effect transistor, said channel having an insulated gate as control electrode, and said electrode regions serve as source and drain of said transistor.
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