US4831285A - Self precharging static programmable logic array - Google Patents
Self precharging static programmable logic array Download PDFInfo
- Publication number
- US4831285A US4831285A US07/145,018 US14501888A US4831285A US 4831285 A US4831285 A US 4831285A US 14501888 A US14501888 A US 14501888A US 4831285 A US4831285 A US 4831285A
- Authority
- US
- United States
- Prior art keywords
- precharge
- plane
- output
- input
- programmable logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
- H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
- H03K5/1534—Transition or edge detectors
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- Logic Circuits (AREA)
Abstract
Description
Claims (10)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/145,018 US4831285A (en) | 1988-01-19 | 1988-01-19 | Self precharging static programmable logic array |
EP89100609A EP0325180A3 (en) | 1988-01-19 | 1989-01-14 | Self precharging static programmable logic array |
CA000588488A CA1299681C (en) | 1988-01-19 | 1989-01-18 | Self precharging static programmable logic array |
JP1008735A JPH01284019A (en) | 1988-01-19 | 1989-01-19 | Self-precharge type static programmable logic array |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/145,018 US4831285A (en) | 1988-01-19 | 1988-01-19 | Self precharging static programmable logic array |
Publications (1)
Publication Number | Publication Date |
---|---|
US4831285A true US4831285A (en) | 1989-05-16 |
Family
ID=22511236
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US07/145,018 Expired - Lifetime US4831285A (en) | 1988-01-19 | 1988-01-19 | Self precharging static programmable logic array |
Country Status (4)
Country | Link |
---|---|
US (1) | US4831285A (en) |
EP (1) | EP0325180A3 (en) |
JP (1) | JPH01284019A (en) |
CA (1) | CA1299681C (en) |
Cited By (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4893033A (en) * | 1987-10-06 | 1990-01-09 | Fujitsu Ltd | Programmable logic array having input transition detection for generating precharge |
US4894564A (en) * | 1987-10-23 | 1990-01-16 | Mitsubishi Denki Kabushiki Kaisha | Programmable logic array with reduced product term line voltage swing to speed operation |
US4924118A (en) * | 1988-02-29 | 1990-05-08 | Nec Corporation | Programmable logic array with interfacial plane |
US4972130A (en) * | 1988-11-16 | 1990-11-20 | Sgs-Thomson Microelectronics, S.R.L. | Multipurpose, internally configurable integrated circuit for driving in a switching mode external inductive loads according to a selectable connection scheme |
US4990801A (en) * | 1988-06-28 | 1991-02-05 | Deutsche Itt Industries Gmbh | Internal timing circuit for a CMOS programmable logic array |
US5022010A (en) * | 1989-10-30 | 1991-06-04 | International Business Machines Corporation | Word decoder for a memory array |
US5033017A (en) * | 1988-04-11 | 1991-07-16 | Fujitsu Limited | Programmable logic array with reduced power consumption |
US5057712A (en) * | 1989-09-29 | 1991-10-15 | Advanced Micro Device, Inc. | Address transition detector for programmable logic array |
US5058068A (en) * | 1989-11-24 | 1991-10-15 | Sgs-Thomson Microelectronics | Redundancy circuit with memorization of output contact pad position |
US5117133A (en) * | 1990-12-18 | 1992-05-26 | Hewlett-Packard Co. | Hashing output exclusive-OR driver with precharge |
US5121005A (en) * | 1991-04-01 | 1992-06-09 | Motorola, Inc. | Programmable logic array with delayed active pull-ups on the column conductors |
US5189320A (en) * | 1991-09-23 | 1993-02-23 | Atmel Corporation | Programmable logic device with multiple shared logic arrays |
US5311079A (en) * | 1992-12-17 | 1994-05-10 | Ditlow Gary S | Low power, high performance PLA |
US5317541A (en) * | 1989-10-30 | 1994-05-31 | International Business Machines Corporation | Bit decoder for generating select and restore signals simultaneously |
US5457404A (en) * | 1993-09-08 | 1995-10-10 | Advanced Micro Devices, Inc. | Zero-power OR gate |
US5532625A (en) * | 1995-03-01 | 1996-07-02 | Sun Microsystems, Inc. | Wave propagation logic |
US5541536A (en) * | 1995-03-01 | 1996-07-30 | Sun Microsystems, Inc. | Rubberband logic |
USRE35806E (en) * | 1988-11-16 | 1998-05-26 | Sgs-Thomson Microelectronics S.R.L. | Multipurpose, internally configurable integrated circuit for driving a switching mode external inductive loads according to a selectable connection scheme |
US5867038A (en) * | 1996-12-20 | 1999-02-02 | International Business Machines Corporation | Self-timed low power ratio-logic system having an input sensing circuit |
WO2001022590A1 (en) * | 1999-09-23 | 2001-03-29 | Chameleon Systems | Reconfigurable programmable sum of products generator |
US6222383B1 (en) * | 1996-12-26 | 2001-04-24 | Micro Magic, Inc. | Controlled PMOS load on a CMOS PLA |
US6349346B1 (en) * | 1999-09-23 | 2002-02-19 | Chameleon Systems, Inc. | Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit |
US20050024092A1 (en) * | 2002-08-27 | 2005-02-03 | Micron Technology, Inc. | Pseudo CMOS dynamic logic with delayed clocks |
US8438522B1 (en) | 2008-09-24 | 2013-05-07 | Iowa State University Research Foundation, Inc. | Logic element architecture for generic logic chains in programmable devices |
US8661394B1 (en) | 2008-09-24 | 2014-02-25 | Iowa State University Research Foundation, Inc. | Depth-optimal mapping of logic chains in reconfigurable fabrics |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2544027B2 (en) * | 1990-05-24 | 1996-10-16 | 株式会社東芝 | Low power consumption programmable logic array and information processing apparatus using the same |
EP0738044A1 (en) * | 1995-04-11 | 1996-10-16 | International Business Machines Corporation | Reduced power PLA |
US5719505A (en) * | 1995-04-11 | 1998-02-17 | International Business Machines Corporation | Reduced power PLA |
US5712790A (en) * | 1995-04-11 | 1998-01-27 | International Business Machines Corporation | Method of power reduction in pla's |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4233667A (en) * | 1978-10-23 | 1980-11-11 | International Business Machines Corporation | Demand powered programmable logic array |
US4563599A (en) * | 1983-03-28 | 1986-01-07 | Motorola, Inc. | Circuit for address transition detection |
US4611133A (en) * | 1983-05-12 | 1986-09-09 | Codex Corporation | High speed fully precharged programmable logic array |
US4697105A (en) * | 1986-07-23 | 1987-09-29 | American Telephone And Telegraph Company, At&T Bell Laboratories | CMOS programmable logic array |
US4728820A (en) * | 1986-08-28 | 1988-03-01 | Harris Corporation | Logic state transition detection circuit for CMOS devices |
US4728827A (en) * | 1986-12-03 | 1988-03-01 | Advanced Micro Devices, Inc. | Static PLA or ROM circuit with self-generated precharge |
US4764691A (en) * | 1985-10-15 | 1988-08-16 | American Microsystems, Inc. | CMOS programmable logic array using NOR gates for clocking |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0178437A1 (en) * | 1984-09-19 | 1986-04-23 | Siemens Aktiengesellschaft | Dynamic programmable CMOS circuit |
CA1257343A (en) * | 1986-07-02 | 1989-07-11 | Robert C. Rose | Self-timed programmable logic array with pre-charge circuit |
JPH0193927A (en) * | 1987-10-06 | 1989-04-12 | Fujitsu Ltd | Programmable logic circuit |
-
1988
- 1988-01-19 US US07/145,018 patent/US4831285A/en not_active Expired - Lifetime
-
1989
- 1989-01-14 EP EP89100609A patent/EP0325180A3/en not_active Withdrawn
- 1989-01-18 CA CA000588488A patent/CA1299681C/en not_active Expired - Lifetime
- 1989-01-19 JP JP1008735A patent/JPH01284019A/en active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4233667A (en) * | 1978-10-23 | 1980-11-11 | International Business Machines Corporation | Demand powered programmable logic array |
US4563599A (en) * | 1983-03-28 | 1986-01-07 | Motorola, Inc. | Circuit for address transition detection |
US4611133A (en) * | 1983-05-12 | 1986-09-09 | Codex Corporation | High speed fully precharged programmable logic array |
US4764691A (en) * | 1985-10-15 | 1988-08-16 | American Microsystems, Inc. | CMOS programmable logic array using NOR gates for clocking |
US4697105A (en) * | 1986-07-23 | 1987-09-29 | American Telephone And Telegraph Company, At&T Bell Laboratories | CMOS programmable logic array |
US4728820A (en) * | 1986-08-28 | 1988-03-01 | Harris Corporation | Logic state transition detection circuit for CMOS devices |
US4728827A (en) * | 1986-12-03 | 1988-03-01 | Advanced Micro Devices, Inc. | Static PLA or ROM circuit with self-generated precharge |
Cited By (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4893033A (en) * | 1987-10-06 | 1990-01-09 | Fujitsu Ltd | Programmable logic array having input transition detection for generating precharge |
US4894564A (en) * | 1987-10-23 | 1990-01-16 | Mitsubishi Denki Kabushiki Kaisha | Programmable logic array with reduced product term line voltage swing to speed operation |
US4924118A (en) * | 1988-02-29 | 1990-05-08 | Nec Corporation | Programmable logic array with interfacial plane |
US5033017A (en) * | 1988-04-11 | 1991-07-16 | Fujitsu Limited | Programmable logic array with reduced power consumption |
US4990801A (en) * | 1988-06-28 | 1991-02-05 | Deutsche Itt Industries Gmbh | Internal timing circuit for a CMOS programmable logic array |
US4972130A (en) * | 1988-11-16 | 1990-11-20 | Sgs-Thomson Microelectronics, S.R.L. | Multipurpose, internally configurable integrated circuit for driving in a switching mode external inductive loads according to a selectable connection scheme |
USRE35806E (en) * | 1988-11-16 | 1998-05-26 | Sgs-Thomson Microelectronics S.R.L. | Multipurpose, internally configurable integrated circuit for driving a switching mode external inductive loads according to a selectable connection scheme |
US5057712A (en) * | 1989-09-29 | 1991-10-15 | Advanced Micro Device, Inc. | Address transition detector for programmable logic array |
US5022010A (en) * | 1989-10-30 | 1991-06-04 | International Business Machines Corporation | Word decoder for a memory array |
US5317541A (en) * | 1989-10-30 | 1994-05-31 | International Business Machines Corporation | Bit decoder for generating select and restore signals simultaneously |
US5058068A (en) * | 1989-11-24 | 1991-10-15 | Sgs-Thomson Microelectronics | Redundancy circuit with memorization of output contact pad position |
US5117133A (en) * | 1990-12-18 | 1992-05-26 | Hewlett-Packard Co. | Hashing output exclusive-OR driver with precharge |
US5121005A (en) * | 1991-04-01 | 1992-06-09 | Motorola, Inc. | Programmable logic array with delayed active pull-ups on the column conductors |
US5189320A (en) * | 1991-09-23 | 1993-02-23 | Atmel Corporation | Programmable logic device with multiple shared logic arrays |
US5311079A (en) * | 1992-12-17 | 1994-05-10 | Ditlow Gary S | Low power, high performance PLA |
US5457404A (en) * | 1993-09-08 | 1995-10-10 | Advanced Micro Devices, Inc. | Zero-power OR gate |
US5532625A (en) * | 1995-03-01 | 1996-07-02 | Sun Microsystems, Inc. | Wave propagation logic |
US5541536A (en) * | 1995-03-01 | 1996-07-30 | Sun Microsystems, Inc. | Rubberband logic |
US5867038A (en) * | 1996-12-20 | 1999-02-02 | International Business Machines Corporation | Self-timed low power ratio-logic system having an input sensing circuit |
US6222383B1 (en) * | 1996-12-26 | 2001-04-24 | Micro Magic, Inc. | Controlled PMOS load on a CMOS PLA |
US6349346B1 (en) * | 1999-09-23 | 2002-02-19 | Chameleon Systems, Inc. | Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit |
US6311200B1 (en) * | 1999-09-23 | 2001-10-30 | Chameleon Systems, Inc. | Reconfigurable program sum of products generator |
WO2001022590A1 (en) * | 1999-09-23 | 2001-03-29 | Chameleon Systems | Reconfigurable programmable sum of products generator |
US20050024092A1 (en) * | 2002-08-27 | 2005-02-03 | Micron Technology, Inc. | Pseudo CMOS dynamic logic with delayed clocks |
US6972599B2 (en) | 2002-08-27 | 2005-12-06 | Micron Technology Inc. | Pseudo CMOS dynamic logic with delayed clocks |
US20050280445A1 (en) * | 2002-08-27 | 2005-12-22 | Micron Technology, Inc. | Pseudo CMOS dynamic logic with delayed clocks |
US6980033B2 (en) | 2002-08-27 | 2005-12-27 | Micron Technology, Inc. | Pseudo CMOS dynamic logic with delayed clocks |
US7250789B2 (en) | 2002-08-27 | 2007-07-31 | Micron Technology, Inc. | Pseudo-CMOS dynamic logic with delayed clocks |
US8438522B1 (en) | 2008-09-24 | 2013-05-07 | Iowa State University Research Foundation, Inc. | Logic element architecture for generic logic chains in programmable devices |
US8661394B1 (en) | 2008-09-24 | 2014-02-25 | Iowa State University Research Foundation, Inc. | Depth-optimal mapping of logic chains in reconfigurable fabrics |
Also Published As
Publication number | Publication date |
---|---|
EP0325180A3 (en) | 1990-03-28 |
CA1299681C (en) | 1992-04-28 |
EP0325180A2 (en) | 1989-07-26 |
JPH01284019A (en) | 1989-11-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: FAIRCHILD SEMICONDUCTOR CORPORATION, 10400 RIDGEVI Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:GAISER, THOMAS A.;REEL/FRAME:004822/0367 Effective date: 19880104 Owner name: FAIRCHILD SEMICONDUCTOR CORPORATION, A DE CORP.,CA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GAISER, THOMAS A.;REEL/FRAME:004822/0367 Effective date: 19880104 |
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Owner name: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, ARIZONA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FAIRCHILD SEMICONDUCTOR CORPORATION;REEL/FRAME:057694/0374 Effective date: 20210722 |