|Publication number||US4792943 A|
|Application number||US 07/029,768|
|Publication date||20 Dec 1988|
|Filing date||24 Mar 1987|
|Priority date||26 Mar 1986|
|Also published as||DE3610195A1, DE3610195C2, EP0274474A1, EP0274474B1, WO1987006075A1|
|Publication number||029768, 07029768, US 4792943 A, US 4792943A, US-A-4792943, US4792943 A, US4792943A|
|Inventors||Heinz G/o/ ckler|
|Original Assignee||Ant Nachrichtentechnik Gmbh|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Referenced by (19), Classifications (9), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
P(μ, υ)=s.sub.μ (kM-υM)·h(μ+υM),
v(kM, q)·ejπnq/L (=1 for n=0).
s0r (2k)=vr (0)+vr (2)+vr (3),
s0i (2k)=vi (0)+vi (2)+vi (3),
s1r (2k)=vr (0)-vr (2)+vi (3),
s1i (2k)=vi (0)-vi (2)-vr (3),
s2r (2k)=vr (0)+vr (2)-vr (3),
s2i (2k)=vi (0)+vi (2)-vi (3),
s3r (2k)=vr (0)-vr (2)-vi (3), and
s3i (2k)=vi (0)-vi (2)+vr (3).
s0r (2k)=vr (0)+vr (1)+vr (2),
s0i (2k)=vi (0)+vi (1)+vi (2),
s1r (2k)=vr (0)-vi (1)-vr (2),
s1i (2k)=vi (0)+vr (1)-vr (2),
s2r (2k)=vr (0)-vr (1)+vr (2),
s2i (2k)=vi (0)-vi (1)+vi (2),
s3r (2k)+vr (0)+vi (1)-vr (2), and
s3i (2k)=vi (0)-vr (1)-vi (2).
The present invention relates to a digital filter bank for frequency multiplex signals. Such digital filter banks are used to demultiplex and multiplex digitalized frequency multiplex signals. They are disclosed, for example, in an article of F. M. Gardner "On-Board Processing For Mobile Satellite Communications", published in Final Report: ESTEC Contract 5889/84, Palo Alto, Calif., Gardner Research Company, May 2, 1985, and in an article, entitled "Comprehensive Survey of Digital Transmultiplexing Methods," by Helmut Scheuermann and Heinz G/o/ ckler, in Proceedings of the IEEE 69 of November, 1981, at pages 1419-1450.
Among the drawbacks of known digital filter banks are that FFT (fast Fourier transformation) algorithms which are adapted for processing complex signals cannot be used to their best advantage.
It is therefore an object of the present invention to provide a digital filter bank of the above-mentioned type which permits optimum utilization of FFT algorithms.
The above and other objects are achieved, according to the present invention, by a circuit including a digital filter bank for effecting conversion between a frequency multiplex signal having a sampling rate fA and L product sums corresponding to the sampled values of the frequency multiplex signal, the pulse response of the filter bank being of finite length, and a discrete Fourier transformation device for effecting conversion between the product sums and L individual complex signals. The sampling rate is reduced by the factor M≦L in the transformation device so that only every Mth value of the product sums is processed therein. In the filter bank, the frequency multiplex signal is a complex signal; the real portion and the imaginary portion of this signal are delayed in respective delay member chains associated with partial sequences of individual signal values which are sampled at a rate of fA /M. These signal values for the real portion and for the imaginary portion are each multiplied by the coefficients of the pulse response and the latter are each multiplied by complex coefficients and the respective ith complex signals are summed to form the L product sums.
Filter banks according to the invention make possible optimum use of FFT algorithms and are very efficient, i.e. they require few adders and multipliers with respect to the intended purpose and demands for steepness, transmission and blocking ripple, etc.
The invention will now be described with reference to the drawing figures.
FIG. 1 is a block circuit diagram of a circuit portion including a digital filter bank according to the invention.
FIG. 2 is a circuit diagram of a filter circuit including the digital filter bank of FIG. 1.
FIG. 3 is a diagram of a circuit arrangement of part of the digital filter bank of FIG. 2.
FIGS. 4a-h are diagrams of several frequency spectra generated during signal processing by the digital filter bank.
FIGS. 5, 6 and 7 are circuit diagrams of particularly favorable realizations corresponding to FIG. 3 of the digital filter bank.
FIG. 8 is a digram of a hierarchical multistage tree structure employing a plurality of digital filter banks.
FIG. 9 is a circuit diagram of a particularly favorable optimum circuit arrangement for a digital filter bank.
FIG. 10 represents a spectral description of the hierarchical multistage tree structure of FIG. 8.
The block in the center of FIG. 2 represents a digital filter bank Difiba. It is fed by a complex frequency multiplex signal s(kT) which, as shown by the example of FIG. 2, is generated by oversampling at a rate 2fA from a frequency multiplex signal FDM and subsequent filtering by means of a digital anti-aliasing filter DAF, followed by normal sampling at a rate fA =1/T. The term k represents a time factor, = . . . -2, -1, 0, +1, +2 . . . , representative of the moment of each signal element.
The digital filter bank generates L complex signals which are then again processed, by means of a DFT (discrete Fourier transformation) or FFT processor, into L complex signals which are each demodulated on an individual channel by means of a respective demodulator Dem.
FIG. 1 is a block circuit diagram showing the digital filter bank composed of a block for the real portion and a block for the imaginary portion of the complex frequency multiplex signal. By processing at a low sampling rate, indicated by a perpendicularly downwardly oriented arrow, with a reduction factor M≦L, these blocks generate product sums vr (0) . . . vr (L) from the real portion of signal s and vi (0) . . . vi (L) from the imaginary portion of signal s to serve as the L complex input signals for the subsequent discrete or fast Fourier transformation. This applies for channel center frequencies fl =l·B, where l is the consecutive channel number and B the channel bandwidth.
For channel center frequencies fl =l·B+B/2, the complex output signals of the two filter blocks must still be multiplied by the complex factor ejπq/L, q=0 . . . L-1, before they are fed to the Fourier transformer, as shown in FIG. 1, where the L input signals to the Fourier Transformer (DFT) are distinguished by the index q and its L output signals by index l.
FIG. 3 shows a processing block of the digital filter bank of FIG. 1 composed of a chain of N-1=9 delay members each producing a time delay of T. The real portion sr (kT) of the complex input signal, or the imaginary portion si (kT), enters into one end of this chain. The N=10 sampling values of the signal sequence are sampled at a sampling rate 1/(MT) and are each multiplied by a coefficient h(0) . . . h(N-1) of the pulse response of the complex filter. Since 1/T represents the input sampling rate of the system and 1/(MT) its output sampling rate, M is the decimation ratio of the system. In essence, it can be set to an arbitrary integer with M≦L.
Then the products of h(0), h(M) . . . and the products of h(1), h(1+M) . . . etc. are added in selected combinations to form L=4 product sums vr(kM, 0), . . . vr(kM, 3).
The filter coefficients h(0), h(1), . . . , h(N-1) are obtained with standard programs for filter synthesis, such as that described by J. H. McClellan et al.: "A computer program for designing optimum FIR linear phase digital filters", IEEE Trans. Audio Electroacoust. AU-21 (1973) 12, pp. 506-526.
The arrangement described above for the real portion is also used for the imaginary portion from which the product sums vi(kM, 0), . . . vi(kM, 3) are produced.
FIGS. 4a-h show the frequency spectra for a digital filter bank having L=16 channels of which only l=3 to 13 are being used. The channel grid is designed for center frequencies fl =l·B+B/2.
FIG. 4a shows the frequency spectrum sr of the frequency multiplex signals as a result of analog bandwidth limitation and oversampling at a sampling rate 2fA. Channels 3 to 13 are shown in the normal position in the frequency range 0 to fA and in the inverted position in the frequency range fA to 2fA.
FIG. 4b shows the frequency characteristic of the DAF filter of FIG. 2. It has a transmission behavior of |HDAF (ej2πf/f.sbsp.A)| with complex coefficients and, as shown, is provided with a transmission range that is symmetrical to fA /2, thus making it most economical.
FIG. 4c shows the frequency spectrum s(ej2πf/f.sbsp.A) of the complex signal s(kT) after periodic sampling at fA =1/T, will all channels 3 to 13 being generated in the normal position in two frequency ranges.
FIG. 4d shows the transfer function |Hprot (ej2πf/f.sbsp.A)| with a transmission range of -B/2 to +B/2 and filter transition regions each having a width B. This transmission characteristic is repeated at the multiples of sampling rate fA.
In FIG. 4e the transfer function is shifted by fm=l·B=7B as a result of complex modulation with ej2πfm/f.sbsp.A =ej2πlB/f.sbsp.A =ej2πl/L.
The transfer function |Hprot (ej2πf/f.sbsp.A)| is the transfer function of a prototype filter, as defined in FIG. 4d, from which all other slot transfer functions of the filter bank are derivable.
FIG. 4f shows the result of filtering by means of a filter having the characteristic shown in FIG. 4e. It shows channel 7 in the normal position with vestiges of adjacent channels located at both sides due to the transition regions.
FIGS. 4g and 4h show the frequency positions of channels having an odd number s7 (ej2πLf/2FA) and an even number s8 (ej2πLf/2fA) after the sampling frequency has been reduced by the factor M=L/2.
FIG. 5 shows a polyphase embodiment of the digital filter bank for the special case of M=L and for channel center frequencies fl =l·B or fl =lB+B/2. Shown, in representative form is the processing of the real portion of the complex input signal. By means of a demultiplexer, represented by a rotating switch switching from one terminal to the next at the rate fA, this succession of input signals s.sub.(r) (kT) is distributed at the sampling rate of fA =1/T to M=L branches of delay members each delay member having a delay of M·T. In each one of these M branches, every Mth value of the partial sequences is multiplied by the coefficient h(i) where i=μ+kM (for μ=0, 1, . . . M-1 and k=0, 1, 2, . . . N/M) and is then summed to form the individual product sums v.sub.(r) (kM, μ).
The decisive advantage of this arrangement is that, except for the input demultiplexer switch, all operations including storage and delay of the data is effected at the reduced output rate fA /M.
FIG. 6 shows a modified polyphase network where the filter bank according to the invention is realized by M branches, where M=L/K, and for channel center frequencies fl =l·B or fl =lB+B/2.
K is an integer number such that the division of the integer L by K results in an integer M.
The processing unit for the real portion vr (kT) of the complex input signal is again shown by way of example, an identical arrangement being required for the imaginary portion. The input demultiplexer switch distributes the input signal sequence at the sampling rate fA=1/T to the μ branches each having a chain of N/M-1 delay members. In each chain, all Kth values of the partial sequence are combined by means of k summing members to form the signals v.sub.(r) (kM, μ) to v.sub.(r) (kM, μ+L/K) for μ=0, 1, . . . , M-1.
FIG. 7 shows a modified polyphase embodiment of part of the digital filter bank for the case of L=4, M=3, N=9 and for channel center frequencies fl =l·B or fl =l·B+B/2. The processing unit for the real portion of the complex input signal is shown by way of example. The input sequence is distributed by means of a demultiplexer switch to branches μ=0, 1, 2, each including two delay members, with each delay member producing a delay of 3T. The individual values of the partial sequences are multiplied, by means of coefficients h(i) of the pulse response of the filter, with i=0, 1, . . . to N-1=8 and the resulting products are added by means of L=4 summing members to form the product sums
The terms h0, h1, h2, . . . , h8 are product terms. In compliance with FIG. 7 we have, for instance
vo=sr (0·T)h(0)+sr (4T)h(4)+sr (8T)h(8).
Exemplary set of coefficients h(0), . . . , h(8): h(0)=h(8)=0; h(1)=h(7)=-0.111 206 7; h(2)=h(6)=0; h(3)=h(5)=0.525 138 3; h(4)=0.615 571 8.
FIG. 8 shows a tree structure embodiment in which the complex input signal SD (kT) is divided into complex individual signals in stages, each stage composed of filters H1 and H0 having complex coefficients, in each stage in sampling rate being half that in the preceding stage.
The blocks of FIG. 8 termed H0 /H1 with =I, II, III, IV, V are given by FIG. 1 with L=4 where only two output signals of each block are exploited. H0 represents the transfer function of a complex lowpass filter and H1 that of a complex bandpass filter, as defined by FIG. 10c. All these filters have complex coefficients, indicated by underlining of the respective quantities. Further more, FIG. 10a shows again the frequency response of the prototype filter Hprot, from which the transfer function HDAF of the DAF (FIG. 10b) and those of the subsequent stages ≠0 (FIG. 10c) are derived (cf. FIGS. 1, 2). All terms beginning with capital S represent spectra at the input or output ports of a stage filter cell H0 /H1, which are all depicted in FIG. 10.
The input sampling rate of the overall filter bank is given by fsi =1/T.
FIG. 9 shows a particularly economical arrangement of a digital filter bank which additionally results in a particularly economical configuration for the subsequent DFT processor. The arrangement results for L=4, M=2, N=15 (where N=8μ-1, μ being an integer number as desired) and for channel center frequencies fl =l·B+B/2.
Both a real portion and an imaginary portion are shown, both having identical structures. In the real portion as well as in the imaginary portion, the complex input signal s(kT) is distributed, at the timing of the sampling frequency fA=1/T, to two chains of delay members. The first chain is composed of (N-1)/2=7 delay members each having a delay of 2T and the second chain is composed of a delay member having a delay of T(N-3)/2=6T. Since the coefficients h(i) for i=1, 3, 5, 9, 11, 13 are zero, only the output of this delay member 6T is multiplied by h7=1/2. The sampled values obtained at the first delay chain are multiplied by h0·√2, h2·√2, -h4·√2, -h6·√2 and, since the pulse response in this example is symmetrical, by h8·√2=h6·√2, h10·√2=h4·√2, -h12·√2=-h2·√ 2 and -h14·√2=-h0·√2. Then, all M=2nd products are summed to
vr (0)=√2·(h0·sr (k)-h4·sr (k-4)+h6·sr (k-8)-h2·sr (k-12)),
vi (0)=√2·(h0·sr (k)-h4·sr (k-4)+h6·sr (k-8)-h2·sr (k-12)),
-vr (2)=√2[h2·si (k-2)-h6·si (k-6)+h4·si (k-10)-h0·si (k-14)],
vi (2)=√2[h2·sr (k-2)-h6·sr (k-6)+h4·sr (k-10)-h0·sr (k-14)] as well as
vr (3)=[sr (7T)-si (7T)]·h7 and
vi (3)=[sr (7T)+si (7T)]·h7.
The quantities h0, h2, h4, h6 and h7 are the coefficients of the prototype filter Hprot, the frequency response of which is defined in FIG. 10a. (Filter synthesis as aforementioned).
Exemplary set of coefficients: h0=0, h2=0.018 454, h4=0.090328, h6=0.426 544, h7=0.5.
Since v(1) is identical to 0, these three complex signals v(0), v(2) and v(3) form the complex input signals for the subsequent DFT processor which needs to perform merely a few summations and subtractions:
s1r (2k)=vr (0)-vr (2)+vi (3),
s0r (2k)=vr (0)+vr (2)+vr (3),
s2r (2k)=vr (0)+vr (2)-vi (3),
s3r (2k)=vr (0)-vr (2)-vi (3),
s0i (2k)=vi (0)+vi (2)+vi (3),
s1i (2k)=vi (0)-vi (2)-vr (3),
s2i (2k)=vi (0)+vi (2)-vi (3), and
s3i (2k)=vi (0)-vi (2)+vr (3).
In contrast to FIG. 9, if v(3)=0, μ being an integer number disappears for N=8μ+3; instead v(1)≠0. Otherwise the same relationships result.
Now follows a mathematical description of the digital filter bank for complex input and output signals.
The object is to filter out the complex input signal s(kT)=s(k) from the input spectrum of the frequency multiplex signal by means of the filter Hl (ej2πf/fA), having complex coefficients.
Hl (ej2πf/fA) represents the transfer function of the digital filter bank for channel l.
The pulse response (complex terms are underlined)
hl (i)=h(i)ej2πil/L, i=0, 1, . . . , N-1 (1)
of the complex filter, derived by means of frequency shifting from the real prototype filter h(i)=Hprot (ej2πf/fA), the (complex) output signal results as a product of folding: ##EQU1##
The desired signal, which is related to the sampling frequency fA/M reduced by the factor M≦L, then results as follows: ##EQU2##
Blocks of a length L are now formed for suitable processing where
i=Lp+q, with p=-∞ . . . ∞, q=0, 1, . . . L-1 (4)
Entered into (3), this results in ##EQU3##
The exponential term can here be simplified (p, l, LεN) to
ej2π(Lp+q)l/L =ej2πpl ej2πql/L =ej2πql/L (6)
By abbreviating the values v(kM,q) which are identical for all channels l, there then results: ##EQU4##
This is applicable for channel center frequencies fl=1·B.
The realization of Equations (7) is shown essentially in FIGS. 1 and 3. First it is necessary to perform processing (Equation 7a) with the sampling frequency reduced by the factor M to arrive at the complex values v(kM,q); see FIG. 3; here, the parts for calculation of the real portion are identical to those for the calculation of the imaginary portion.
The complex values v(kM,q), l=0, . . . , L-1 must be subjected, as a block, to a DFT of a length L. This optimally utilizes the efficiency of the DFT algorithm (or any desired FFT algorithm) since complex signals are required as input as well as output values.
It is also possible to shift the channel grid by onehalf a channel bandwidth or as desired by n/m (n, mεN; n<m) with respect to FIG. 4, where n and m are integer numbers and n<m.
Then, instead of (1), the following applies: ##EQU5##
Then Equation (5) reads as follows: ##EQU6## and the exponential term (6) n, mε/N, n<m, becomes ##EQU7##
Thus, Equations (7) become ##EQU8##
This also applies generally for channel center frequencies fl =l·B+B·n/m.
The complex coefficients ##EQU9## take the place of the originally real coefficients h(pL+q), which, for the calculation of the values n(kM,q), corresponds to doubling the original number of multiplications and additions.
For m=2 and m=4, there also exists the possibility of calculating v(kM,q) by way of ##EQU10## where m=2 is ##EQU11## and m=4 is ##EQU12##
Thus the effort required to calculate v[?](kM,q) of Equation (12a) and v(kM,q) of equation (7a) is identical. Finally, this results in ##EQU13## which generally requires an additional four multiplications and two additions for each q=0, 1, . . . , L-1, if n≠0. Compared with the effort for Equation (11), the effort for Equation (12) is always less if
which is frequently the case.
Another possibility for m=2 and m=4 is to combine the factors ##EQU14## (Equation 12d) with the DFT to obtain an odd (0DFT), which results in a further reduction of effort.
It is known that any desired digital signal processing network can be converted to a dual function network by transposition. For example, a digital filter bank for the frequency separation of frequency multiplex signals can be converted, by means of the transposition method, into a filter bank for the frequency combination of individual signals into a frequency multiplex signal. For the above described structures, this means that all signal flow directions are reversed (i.e. exchange of input and output, adder becomes branching member, branching member becomes adder, DFT becomes inverse DFT). The method of transposing digital networds is described in the article entitled, "On The Transposition Of Linear Time-Varying Discrete-Time Networks And Its Application To Multirate Digital Systems", Philips J. Res., Volume 33, 1978, pages 78-102.
The invention now being fully described, it will be apparent to one of ordinary skill in the art that many changes and modifications can be made thereto without departing from the spirit or scope of the invention as set forth herein.
The present disclosure relates to the subject matter disclosed in German Application P 36 10 195.8 of March 26, 1986, the entire specification of which is incorporated herein by reference.
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|U.S. Classification||370/210, 370/484|
|Cooperative Classification||H03H17/0266, H03H17/0213, H03H17/0292|
|European Classification||H03H17/02C1, H03H17/02F8A, H03H17/02G3|
|24 Mar 1987||AS||Assignment|
Owner name: ANT NACHRICHTENTECHNIK GMBH, GERBERSTRASSE 33, D-7
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:GOCKLER, HEINZ;REEL/FRAME:004682/0804
Effective date: 19870311
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