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Publication numberUS4792943 A
Publication typeGrant
Application numberUS 07/029,768
Publication date20 Dec 1988
Filing date24 Mar 1987
Priority date26 Mar 1986
Fee statusPaid
Also published asDE3610195A1, DE3610195C2, EP0274474A1, EP0274474B1, WO1987006075A1
Publication number029768, 07029768, US 4792943 A, US 4792943A, US-A-4792943, US4792943 A, US4792943A
InventorsHeinz G/o/ ckler
Original AssigneeAnt Nachrichtentechnik Gmbh
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Digital filter bank
US 4792943 A
Abstract
A circuit including a digital filter bank for effecting conversion between a frequency multiplex signal having a sampling rate fA and L product sums corresponding to the sampled values of the frequency multiplex signal, the pulse response of the filter bank being of finite length, and a discrete Fourier transformation device for effecting conversion between the product sums and L individual complex signals. The sampling rate is reduced by the factor M≦L in the transformation device so that only every Mth value of the product sums is processed therein. In the filter bank, the frequency multiplex signal is a complex signal; the real portion and the imaginary portion of this signal are delayed in respective delay member chains associated with partial sequences of individual signal values which are sampled at a rate of fA /M. These signal values for the real portion and for the imaginary portion are each multiplied by the coefficients of the pulse response and the latter are each multiplied by complex coefficients and the respective ith complex signals are summed to form the L product sums.
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Claims(11)
What is claimed is:
1. In a frequency multiplex circuit including a digital filter bank for effecting conversion between a frequency multiplexed signal and a plurality of weighted filter signals, and discrete Fourier transformation means connected to said filter bank for effecting a discrete Fourier transformation between the weighted filter signals and L individual complex signals appearing on separate lines, wherein:
the frequency multiplexed signal contains component signals each associated with a respective individual complex signal and having a bandwidth B;
the weighted filter signals have the form ##EQU15## where i=pL+q
q=0, 1, 2, . . . L-1, and
i, p, q=(0, 1, 2, 3, . . . )
the frequency multiplexed signal is s(k) and has a sampling rate of fA;
h(i) is a coefficient representing a pulse response of a finite length for i=0, 1, 2, . . . N-1;
the discrete Fourier transformation has the form ##EQU16## where sl (kM) represents the individual complex signals and DFT { } is the discrete Fourier transformation, M is a sampling rate reduction factor, M≦L, and the discrete Fourier transformation involves sampling with respect to every Mth value of the weighted filter signals;
each component signal of the frequency multiplexed signal is associated with a respective channel having a channel number, l, and a center channel frequency fl =lB and l=1, 2, . . . L-1, the improvement wherein:
the frequency multiplexed signal is a complex signal, s(kT)=sr (kT)+jsi (kT) with a real portion Re=sr (kT) and an imaginary portion Im=si (kT), and k is a time factor= . . . , -1, 0, +1 . . . ; and
said filter bank comprises:
two chains of N-1 delay members each having a delay of T and each processing a respective portion of the complex signal, where N is the number of frequency multiplexed signal values associated with each set of weighted filter signal values and T=1/fA ; sampling means for sampling the signals associated with each delay member at a rate corresponding to the sampling rate of the frequency multiplexed signal reduced by M; first processing means for effecting conversion between each sample signal associated with a given delay member and an associated weighted sample signal; and second processing means for effecting conversion between selected weighted filter signals and selected weighted sample signals.
2. In a frequency multiplex circuit including a digital filter bank for effecting conversion between a frequency multiplexed signal and a plurality of weighted filter signals, and discrete Fourier transformation means connected to said filter bank for effecting a discrete Fourier transformation between the weighted filter signal and L individual complex signals appearing on separate lines, wherein:
the frequency multiplexed signal contains component signals each associated with a respective individual complex signal and having a bandwidth B;
the weighted filter signals are complex signals having the form ##EQU17## where n<m,
n=0, 1, 2, . . . ,
m=1, 2, . . . ,
i=pL+q
q=0, 1, 2, . . . L-1, and
i, p, q=(0, 1, 2, 3, . . . )
the frequency multiplexed signal is s(k) and has a sampling rate of fA ;
h(i) is a coefficient representing a pulse response of a finite length for i=0, 1, 2, . . . N-1, which pulse response has a complex rotation factor;
the discrete Fourier transformation has the form ##EQU18## where sl (kM) represents the individual complex signals and DFT { } is the discrete Fourier transformation, M is a sampling rate reduction factor, M≦L, and the discrete Fourier transformation involves sampling with respect to every Mth value of the weighted filter signals;
each component signal of the frequency multiplexed signal is associated with a respective channel having a channel number, l, and a center channel frequency fl =lB+Bn/m and l=0, 1, 2, . . . L-1, the improvement wherein:
the frequency multiplexed signal is a complex signal, s(kT)=sr (kT)+jsi (kT) with a real portion Re=sr (kT) and an imaginary portion Im=si (kT), and k is a time factor= . . . , -1, 0, +1 . . . ; and
said filter bank comprises:
two chains of N-1 delay members each having a delay of T and each processing a respective portion of the complex signal, where N is the number of frequency multiplexed signal values associated with each set of weighted filter signal values and T=1/fA ; sampling means for sampling the signals associated with each delay member at a rate corresponding to the sampling rate of the frequency multiplexed signal reduced by M; first processing means for effecting conversion between each sample signal associated with a given delay member and an associated weighted sample signal, wherein each weighted sample signal corresponds to a sample signal multiplied by a complex coefficient h(i)=hr (i)+jhi (i), where hr (i)=h(i)cos (2πin/Lm) and hi (i)=h(i)sin (2πi.n/Lm); and second processing means for effecting conversion between selected weighted complex filter signals v(kM,q) and respective ith weighted sample signals.
3. In a frequency multiplex circuit including a digital filter bank for effecting conversion between a frequency multiplexed signal and a plurality of weighted filter signals, and discrete Fourier transformation means connected to said filter bank for effecting a discrete Fourier transformation between the weighted filter signal and L individual complex signals appearing on separate lines, wherein:
the frequency multiplexed signal contains component signals each associated with a respective individual complex signal and having a bandwidth B;
the weighted filter signals are complex signals having the form ##EQU19## where
i=pL+q
q=0, 1, 2, . . . L-1, and
i, p, q=(0, 1, 2, 3, . . . )
the frequency multiplexed signal is s(k) and has a sampling rate of fA ;
h(i) is a coefficient representing a pulse response of a finite length for i=0, 1, 2 . . . N-1, which pulse response has a complex rotation factor;
the discrete Fourier transformation has the form ##EQU20## where sp (kM) represents the individual complex signals and DFT { } is the discrete Fourier transformation, M is a sampling rate reduction factor, M≦L, and the discrete Fourier transformation involves sampling with respect to every Mth value of the weighted filter signals;
each component signal of the frequency multiplexed signal is associated with a respective channel having a channel number, l, and a center channel frequency fl =lB+B/2 and l=0, 1, 2, . . . L-1, the improvement wherein:
the frequency multiplexed signal is a complex signal, s(kT)=sr (kT)+jsi (kT) with a real portion Re=sr (kT) and an imaginary portion Im=si (kT), and k is a time factor= . . . , -1, 0, +1 . . . ; and
said filter bank comprises:
two chains of N-1 delay members each having a delay of T and each processing a respective portion of the complex signal, where N is the number of frequency multiplexed signal values associated with each set of weighted filter signal values and T=1/fA ; sampling means for sampling the signals associated with each delay member at a rate corresponding to the sampling rate of the frequency multiplexed signal reduced by M; first processing means for effecting conversion between each sample signal associated with a given delay member and an associated weighted sample signal; second processing means for effecting conversion between selected weighted filter signals and selected weighted sample signals; and third processing means for effecting conversion between complex selected weighted filter signals and those signals multiplied by ej2πq/L.
4. In a frequency multiplex circuit including a digital filter bank for effecting conversion between a frequency multiplexed signal and a plurality of weighted filter signals, and discrete Fourier transformation means connected to said filter bank for effecting a discrete Fourier transformation between the weighted filter signals and L individual complex signals appearing on separate lines, wherein:
the frequency multiplexed signal contains component signals each associated with a respective individual complex signal and having a bandwidth B;
the weighted filter signals have the form ##EQU21## where n=0, or n=1 and m=2,
i=pL+q,
q=0, 1, 2, . . . L-1, and
i, p, q=(0, 1, 2, 3, . . . )
the frequency multiplexed signal is s(k) and has a sampling rate of fA ;
h(i) is a coefficient representing a pulse response of a finite length for i=0, 1, 2, . . . N-1, which pulse response has a complex rotation factor;
the discrete Fourier transformation has the form ##EQU22## where sl (kM) represents the individual complex signals and DFT { } is the discrete Fourier transformation, M is a sampling rate reduction factor, M≦L, and the discrete Fourier transformation involves sampling with respect to every Mth value of the weighted filter signals;
each component signal of the frequency multiplexed signal is associated with a respective channel having a channel number, l, and a center channel frequency fl =lB+Bn/m and l=0, 1, 2, . . . L-1, the improvement wherein:
the frequency multiplexed signal is a complex signal, s(kT)=sr (kT)+jsi (kT) with a real portion Re=sr (kT) and an imaginary portion Im=si (kT), and k is a time factor= . . . , -1, 0, +1 . . . ; and
said filter bank comprises two identical signal processing systems, each associated with a respective complex signal portion and each comprising:
multiposition switch means having a contact switchable between M terminals and M chains of delay members, each chain being connected to a respective terminal of said switch means and containing a number of delay members equal to the largest integer which is not greater than N/M, and each delay member producing a delay of MT, with the associated portion of the frequency multiplexed signal being present at said switch means contact, said switch means being operative to connect said contact cylically to each terminal in turn at the sampling rate of fA from terminal to terminal so that said contact is cyclically connected to each terminal at a rate of fA /M; and
first processing means connected to said delay members for affecting conversion between each sample signal associated with a given delay member and an associated weighted product signal according to the relation
P(μ, υ)=s.sub.μ (kM-υM)h(μ+υM),
where
P is the weighted product signal,
μ is the associated chain=0, 1 . . . M-1,
s.sub.μ is the sample signal at the associated terminal,
υ is the associated delay member=0, 1, 2 . . . , and
h is the weighting coefficient; and
said filter bank further comprises:
second processing means connected to said first processing means of each said signal processing system for effecting conversion between the weighted product signals and L intermediate complex signals v(kM, q), each portion of each intermediate complex signal being the sum of selected weighted product signals for which μ=pM+pλ+q-αM, where α=(pM+pλ+q)/M and λ=L-M; and
third processing means connected to said second processing means for effecting conversion between each intermediate complex signal and an associated weighted filter signal, such that each weighted filter signal is
v(kM, q)ejπnq/L (=1 for n=0).
5. A frequency multiplex circuit as defined in claim 4 wherein for M=L/R, R≦L, and R=1, 2, 3 . . . , said second processing means comprises R summing members for each delay member chain, for forming R sum signals, each said summing member being connected to sum the weighted product signals P(μ, υ) for which υ=bR+c, where b=0, 1, 2 . . . , and c represents the given summing member and=1, 2 . . . R.
6. A frequency multiplex circuit as defined in claim 4 wherein, for M=L, said second processing means are operative, for each chain, for summing all weighted product signals P(μ, υ)=P(q) to form L intermediate signals for each of the real and imaginary portions of v(kM, q).
7. A frequency multiplex circuit as defined in claim 1 wherein there are a plurality of said digital banks connected to one another in successive stages in an outwardly branching tree structure such that, starting with the first stage, the frequency multiplexed signal is separated into L.sub.υ individual signals at the υth stage, where υ=1, 2 . . . , and the sampling rate is reduced at the υth stage by M.sub.υ ≦L.sub.υ.
8. A frequency multiplex circuit as defined in claim 1 further comprising a filter having complex coefficients for sampling an initial frequency multiplexed signal at a sampling rate of 2fA to form the signal s(k).
9. In a frequency multiplex circuit including a digital filter bank for effecting conversion between a frequency multiplexed signal and a plurality of weighted filter signals, and discrete Fourier transformation means connected to said filter bank for effecting a discrete Fourier transformation between the weighted filter signals and 4 individual complex signals appearing on separate lines, wherein:
the frequency multiplexed signal contains component signals each associated with a respective individual complex signal and having a bandwidth B;
the weighted filter signals are complex signals having the form ##EQU23##
i=4p+q
q=0, 1, 2, 3, and
i, p, q=(0, 1, 2, 3, . . . )
the frequency multiplexed signal is s(k) and has a sampling rate of fA ;
h(i) is a coefficient representing a pulse response of a finite length for i=0, 1, 2 . . . N-1, which pulse response has a complex rotation factor, where N=8μ-1 and μ=1, 2, 3 . . . )
the discrete Fourier transformation has the form ##EQU24## where sl (kM) represents the individual complex signals and DFT { } is the discrete Fourier transformation, M=2 and the discrete Fourier transformation involves sampling with respect to every 2nd value of the weighted filter signals;
each component signal of the frequency multiplexed signal is associated with a respective channel having a channel number, l, and a center channel frequency fl =lB+B/2 and l=0, 1, 2, 3, the improvement wherein:
the frequency multiplexed signal is a complex signal, s(kT)=sr (kT)+jsi (kT) with a real portion Re=sr (kT) and an imaginary portion Im=si (kT), and k is a time factor= . . . , -1, 0, +1 . . . ; and
said filter bank comprises, for each portion of the frequency multiplex signal;
first delay means consisting of a chain of (N-1)/2 delay members each having a delay of 2T=2fA, second delay means consisting of one delay member having a delay of T(N-3)/2; and switch means for deriving samples of the associated complex signal portion at the sampling rate of fA and supplying successive samples to alternate ones of said delay means; said first delay means having (N+1)/2 successively numbered output points, the first output point being at the input of the first delay member in said chain, connected to said switch means, and each succeeding output point being at the output of each succeeding delay member of said chain, starting with the first delay member;
first multiplying means connected for multiplying the signals at the odd numbered output points by the √2 scaled coefficients h(4a), where a=0, 1, 2 . . . , and combining the multiplied signals to form a product sum vr (0) for the real portion or vi (0) for the imaginary portion;
second multiplying means connected for multiplying the signals at the even numbered output points by the √2 scaled coefficients h(4a+2), and combining the multiplied signals to form a product sum -vr (2) for the real portion or vi (2) for the imaginary portion;
wherein said first and second multiplying means are operative for causing the multiplied signals associated with each alternate pair of successive output points, starting with the first output point, to be evaluated as positive and for causing the multiplied signals associated with the intervening pairs of successive output points to be evaluated as negative; and
third multiplying means connected for multiplying the output of one delay member of said second delay means by 1/2; and
said filter bank further comprises arithmetic means connected to said third multiplying means for each portion of the frequency multiplexed signal for forming a signal vi (3) representing the sum of the signals produced by the two said third multiplying means and a signal vr (3) representing the signals produced said third multiplying means associated with the real portion less the signal produced by said third multiplying means associated with the imaginary portion; and
said discrete Fourier transformation means are connected to receive the signals vr (0), v1 (0), -vr (2), vi (2), vr (3) and v1 (3) as complex signals and to form four complex signals so (2k) . . . s3 (2k) having the following relationships:
s0r (2k)=vr (0)+vr (2)+vr (3),
s0i (2k)=vi (0)+vi (2)+vi (3),
s1r (2k)=vr (0)-vr (2)+vi (3),
s1i (2k)=vi (0)-vi (2)-vr (3),
s2r (2k)=vr (0)+vr (2)-vr (3),
s2i (2k)=vi (0)+vi (2)-vi (3),
s3r (2k)=vr (0)-vr (2)-vi (3), and
s3i (2k)=vi (0)-vi (2)+vr (3).
10. In a frequency multiplex circuit including a digital filter bank for effecting conversion between a frequency multiplexed signal and a plurality of weighted filter signals, and discrete Fourier transformation means connected to said filter bank for effecting a discrete Fourier transformation between the weighted filter signals and 4 individual complex signals appearing on separate lines, wherein:
the frequency multiplexed signal contains component signals each associated with a respective individual complex signal and having a bandwidth B;
the weighted filter signals are complex signals having the form ##EQU25##
i=4p+q
q=0, 1, 2, 3, and
i, p, q=(0, 1, 2, 3, . . . )
the frequency multiplexed signal is s(k) and has a sampling rate of fA ;
h(i) is a coefficient representing a pulse response of a finite length for i=0, 1, 2 . . . N-1, which pulse response has a complex rotation factor, where N=8μ+3 and μ=1, 2, 3 . . . )
the discrete Fourier transformation has the form ##EQU26## where sl (kM) represents the individual complex signals and DFT { } is the discrete Fourier transformation, M=2 and the discrete Fourier transformation involves sampling with respect to every 2nd value of the weighted filter signals;
each component signal of the frequency multiplexed signal is associated with a respective channel having a channel number, l, and a center channel frequency fl =lB+B/2 and l=0, 1, 2, 3, the improvement wherein:
the frequency multiplexed signal is a complex signal, s(kT)=sr (kT)+jsi (kT) with a real portion Re=sr (kT) and an imaginary portion Im=si (kT), and k is a time factor= . . . , -1, 0, +1 . . . ; and
said filter bank comprises, for each portion of the frequency multiplex signal:
first delay means consisting of a chain of (N-1)/2 delay members each having a delay of 2T=2fA, second delay means consisting of one delay member having a delay of T(N-3)/2; and switch means for deriving samples of the associated complex signal portion at the sampling rate of fA and supplying successive samples to alternate ones of said delay means; said first delay means having (N+1)/2 successively numbered output points, the first output point being at the input of the first delay member in said chain, connected to said switch means, and each succeeding output point being at the output of each succeeding delay member of said chain, starting with the first delay member;
first multiplying means connected for multiplying the signals at the odd numbered output points by the √2 scaled coefficients h(4a), where a=0, 1, 2 . . . , and combining the multiplied signals to form a product sum vr (0) for the real portion or vi (0) for the imaginary portion;
second multiplying means connected for multiplying the signals at the even numbered output points by the √2 scaled coefficients h(4a+2), and combining the multiplied signals to form a product sum -vr (2) for the real portion or vi (2) for the imaginary portion;
wherein said first and second multiplying means are operative for causing the multiplied signals associated with each alternate pair of successive output points, starting with the first output point, to be evaluated as positive and for causing the multiplied signals associated with the intervening pairs of successive output points to be evaluated as negative; and
third multiplying means connected for multiplying the output of one delay member of said second delay means by 1/2; and
said filter bank further comprises arithmetic means connected to said third multiplying means for each portion of the frequency multiplexed signal for forming a signal vi (1) representing the sum of the signals produced by the two said third multiplying means and a signal vr (1) representing the signals produced said third multiplying means associated with the real portion less the signal produced by said third multiplying means associated with the imaginary portion; and
said discrete Fourier transformation means are connected to receive the signals vr (0), v1 (0), -vr (1), -vi (1), -vr (2) and v1 (2) as complex signals and to form four complex signals so (2k) . . . s3 (2k) having the following relationships:
s0r (2k)=vr (0)+vr (1)+vr (2),
s0i (2k)=vi (0)+vi (1)+vi (2),
s1r (2k)=vr (0)-vi (1)-vr (2),
s1i (2k)=vi (0)+vr (1)-vr (2),
s2r (2k)=vr (0)-vr (1)+vr (2),
s2i (2k)=vi (0)-vi (1)+vi (2),
s3r (2k)+vr (0)+vi (1)-vr (2), and
s3i (2k)=vi (0)-vr (1)-vi (2).
11. A frequency multiplex circuit as defined in claim 1 for combining the L individual complex signals to form the frequency multiplexed signal, wherein, said discrete Fourier transformation means is an inverse discrete Fourier transformation device operative for sampling each individual complex signal at a sampling rate of fA /M, and said Fourier transformation device is connected for supplying signals corresponding to the indiviual complex signals to said filter bank.
Description
BACKGROUND OF THE INVENTION

The present invention relates to a digital filter bank for frequency multiplex signals. Such digital filter banks are used to demultiplex and multiplex digitalized frequency multiplex signals. They are disclosed, for example, in an article of F. M. Gardner "On-Board Processing For Mobile Satellite Communications", published in Final Report: ESTEC Contract 5889/84, Palo Alto, Calif., Gardner Research Company, May 2, 1985, and in an article, entitled "Comprehensive Survey of Digital Transmultiplexing Methods," by Helmut Scheuermann and Heinz G/o/ ckler, in Proceedings of the IEEE 69 of November, 1981, at pages 1419-1450.

Among the drawbacks of known digital filter banks are that FFT (fast Fourier transformation) algorithms which are adapted for processing complex signals cannot be used to their best advantage.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a digital filter bank of the above-mentioned type which permits optimum utilization of FFT algorithms.

The above and other objects are achieved, according to the present invention, by a circuit including a digital filter bank for effecting conversion between a frequency multiplex signal having a sampling rate fA and L product sums corresponding to the sampled values of the frequency multiplex signal, the pulse response of the filter bank being of finite length, and a discrete Fourier transformation device for effecting conversion between the product sums and L individual complex signals. The sampling rate is reduced by the factor M≦L in the transformation device so that only every Mth value of the product sums is processed therein. In the filter bank, the frequency multiplex signal is a complex signal; the real portion and the imaginary portion of this signal are delayed in respective delay member chains associated with partial sequences of individual signal values which are sampled at a rate of fA /M. These signal values for the real portion and for the imaginary portion are each multiplied by the coefficients of the pulse response and the latter are each multiplied by complex coefficients and the respective ith complex signals are summed to form the L product sums.

Filter banks according to the invention make possible optimum use of FFT algorithms and are very efficient, i.e. they require few adders and multipliers with respect to the intended purpose and demands for steepness, transmission and blocking ripple, etc.

The invention will now be described with reference to the drawing figures.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a block circuit diagram of a circuit portion including a digital filter bank according to the invention.

FIG. 2 is a circuit diagram of a filter circuit including the digital filter bank of FIG. 1.

FIG. 3 is a diagram of a circuit arrangement of part of the digital filter bank of FIG. 2.

FIGS. 4a-h are diagrams of several frequency spectra generated during signal processing by the digital filter bank.

FIGS. 5, 6 and 7 are circuit diagrams of particularly favorable realizations corresponding to FIG. 3 of the digital filter bank.

FIG. 8 is a digram of a hierarchical multistage tree structure employing a plurality of digital filter banks.

FIG. 9 is a circuit diagram of a particularly favorable optimum circuit arrangement for a digital filter bank.

FIG. 10 represents a spectral description of the hierarchical multistage tree structure of FIG. 8.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The block in the center of FIG. 2 represents a digital filter bank Difiba. It is fed by a complex frequency multiplex signal s(kT) which, as shown by the example of FIG. 2, is generated by oversampling at a rate 2fA from a frequency multiplex signal FDM and subsequent filtering by means of a digital anti-aliasing filter DAF, followed by normal sampling at a rate fA =1/T. The term k represents a time factor, = . . . -2, -1, 0, +1, +2 . . . , representative of the moment of each signal element.

The digital filter bank generates L complex signals which are then again processed, by means of a DFT (discrete Fourier transformation) or FFT processor, into L complex signals which are each demodulated on an individual channel by means of a respective demodulator Dem.

FIG. 1 is a block circuit diagram showing the digital filter bank composed of a block for the real portion and a block for the imaginary portion of the complex frequency multiplex signal. By processing at a low sampling rate, indicated by a perpendicularly downwardly oriented arrow, with a reduction factor M≦L, these blocks generate product sums vr (0) . . . vr (L) from the real portion of signal s and vi (0) . . . vi (L) from the imaginary portion of signal s to serve as the L complex input signals for the subsequent discrete or fast Fourier transformation. This applies for channel center frequencies fl =lB, where l is the consecutive channel number and B the channel bandwidth.

For channel center frequencies fl =lB+B/2, the complex output signals of the two filter blocks must still be multiplied by the complex factor ejπq/L, q=0 . . . L-1, before they are fed to the Fourier transformer, as shown in FIG. 1, where the L input signals to the Fourier Transformer (DFT) are distinguished by the index q and its L output signals by index l.

FIG. 3 shows a processing block of the digital filter bank of FIG. 1 composed of a chain of N-1=9 delay members each producing a time delay of T. The real portion sr (kT) of the complex input signal, or the imaginary portion si (kT), enters into one end of this chain. The N=10 sampling values of the signal sequence are sampled at a sampling rate 1/(MT) and are each multiplied by a coefficient h(0) . . . h(N-1) of the pulse response of the complex filter. Since 1/T represents the input sampling rate of the system and 1/(MT) its output sampling rate, M is the decimation ratio of the system. In essence, it can be set to an arbitrary integer with M≦L.

Then the products of h(0), h(M) . . . and the products of h(1), h(1+M) . . . etc. are added in selected combinations to form L=4 product sums vr(kM, 0), . . . vr(kM, 3).

The filter coefficients h(0), h(1), . . . , h(N-1) are obtained with standard programs for filter synthesis, such as that described by J. H. McClellan et al.: "A computer program for designing optimum FIR linear phase digital filters", IEEE Trans. Audio Electroacoust. AU-21 (1973) 12, pp. 506-526.

The arrangement described above for the real portion is also used for the imaginary portion from which the product sums vi(kM, 0), . . . vi(kM, 3) are produced.

FIGS. 4a-h show the frequency spectra for a digital filter bank having L=16 channels of which only l=3 to 13 are being used. The channel grid is designed for center frequencies fl =lB+B/2.

FIG. 4a shows the frequency spectrum sr of the frequency multiplex signals as a result of analog bandwidth limitation and oversampling at a sampling rate 2fA. Channels 3 to 13 are shown in the normal position in the frequency range 0 to fA and in the inverted position in the frequency range fA to 2fA.

FIG. 4b shows the frequency characteristic of the DAF filter of FIG. 2. It has a transmission behavior of |HDAF (ej2πf/f.sbsp.A)| with complex coefficients and, as shown, is provided with a transmission range that is symmetrical to fA /2, thus making it most economical.

FIG. 4c shows the frequency spectrum s(ej2πf/f.sbsp.A) of the complex signal s(kT) after periodic sampling at fA =1/T, will all channels 3 to 13 being generated in the normal position in two frequency ranges.

FIG. 4d shows the transfer function |Hprot (ej2πf/f.sbsp.A)| with a transmission range of -B/2 to +B/2 and filter transition regions each having a width B. This transmission characteristic is repeated at the multiples of sampling rate fA.

In FIG. 4e the transfer function is shifted by fm=lB=7B as a result of complex modulation with ej2πfm/f.sbsp.A =ej2πlB/f.sbsp.A =ej2πl/L.

The transfer function |Hprot (ej2πf/f.sbsp.A)| is the transfer function of a prototype filter, as defined in FIG. 4d, from which all other slot transfer functions of the filter bank are derivable.

FIG. 4f shows the result of filtering by means of a filter having the characteristic shown in FIG. 4e. It shows channel 7 in the normal position with vestiges of adjacent channels located at both sides due to the transition regions.

FIGS. 4g and 4h show the frequency positions of channels having an odd number s7 (ej2πLf/2FA) and an even number s8 (ej2πLf/2fA) after the sampling frequency has been reduced by the factor M=L/2.

FIG. 5 shows a polyphase embodiment of the digital filter bank for the special case of M=L and for channel center frequencies fl =lB or fl =lB+B/2. Shown, in representative form is the processing of the real portion of the complex input signal. By means of a demultiplexer, represented by a rotating switch switching from one terminal to the next at the rate fA, this succession of input signals s.sub.(r) (kT) is distributed at the sampling rate of fA =1/T to M=L branches of delay members each delay member having a delay of MT. In each one of these M branches, every Mth value of the partial sequences is multiplied by the coefficient h(i) where i=μ+kM (for μ=0, 1, . . . M-1 and k=0, 1, 2, . . . N/M) and is then summed to form the individual product sums v.sub.(r) (kM, μ).

The decisive advantage of this arrangement is that, except for the input demultiplexer switch, all operations including storage and delay of the data is effected at the reduced output rate fA /M.

FIG. 6 shows a modified polyphase network where the filter bank according to the invention is realized by M branches, where M=L/K, and for channel center frequencies fl =lB or fl =lB+B/2.

K is an integer number such that the division of the integer L by K results in an integer M.

The processing unit for the real portion vr (kT) of the complex input signal is again shown by way of example, an identical arrangement being required for the imaginary portion. The input demultiplexer switch distributes the input signal sequence at the sampling rate fA=1/T to the μ branches each having a chain of N/M-1 delay members. In each chain, all Kth values of the partial sequence are combined by means of k summing members to form the signals v.sub.(r) (kM, μ) to v.sub.(r) (kM, μ+L/K) for μ=0, 1, . . . , M-1.

FIG. 7 shows a modified polyphase embodiment of part of the digital filter bank for the case of L=4, M=3, N=9 and for channel center frequencies fl =lB or fl =lB+B/2. The processing unit for the real portion of the complex input signal is shown by way of example. The input sequence is distributed by means of a demultiplexer switch to branches μ=0, 1, 2, each including two delay members, with each delay member producing a delay of 3T. The individual values of the partial sequences are multiplied, by means of coefficients h(i) of the pulse response of the filter, with i=0, 1, . . . to N-1=8 and the resulting products are added by means of L=4 summing members to form the product sums

v0=h0+h4+h8,

v1=h1+h5,

v2=h2+h6, and

v3=h3+h7.

The terms h0, h1, h2, . . . , h8 are product terms. In compliance with FIG. 7 we have, for instance

h0=sr (0T)h(0)

h4=sr (4T)h(4)

h8=sr (8T)h(8)

or

vo=sr (0T)h(0)+sr (4T)h(4)+sr (8T)h(8).

Exemplary set of coefficients h(0), . . . , h(8): h(0)=h(8)=0; h(1)=h(7)=-0.111 206 7; h(2)=h(6)=0; h(3)=h(5)=0.525 138 3; h(4)=0.615 571 8.

FIG. 8 shows a tree structure embodiment in which the complex input signal SD (kT) is divided into complex individual signals in stages, each stage composed of filters H1 and H0 having complex coefficients, in each stage in sampling rate being half that in the preceding stage.

The blocks of FIG. 8 termed H0 /H1 with =I, II, III, IV, V are given by FIG. 1 with L=4 where only two output signals of each block are exploited. H0 represents the transfer function of a complex lowpass filter and H1 that of a complex bandpass filter, as defined by FIG. 10c. All these filters have complex coefficients, indicated by underlining of the respective quantities. Further more, FIG. 10a shows again the frequency response of the prototype filter Hprot, from which the transfer function HDAF of the DAF (FIG. 10b) and those of the subsequent stages ≠0 (FIG. 10c) are derived (cf. FIGS. 1, 2). All terms beginning with capital S represent spectra at the input or output ports of a stage filter cell H0 /H1, which are all depicted in FIG. 10.

The input sampling rate of the overall filter bank is given by fsi =1/T.

FIG. 9 shows a particularly economical arrangement of a digital filter bank which additionally results in a particularly economical configuration for the subsequent DFT processor. The arrangement results for L=4, M=2, N=15 (where N=8μ-1, μ being an integer number as desired) and for channel center frequencies fl =lB+B/2.

Both a real portion and an imaginary portion are shown, both having identical structures. In the real portion as well as in the imaginary portion, the complex input signal s(kT) is distributed, at the timing of the sampling frequency fA=1/T, to two chains of delay members. The first chain is composed of (N-1)/2=7 delay members each having a delay of 2T and the second chain is composed of a delay member having a delay of T(N-3)/2=6T. Since the coefficients h(i) for i=1, 3, 5, 9, 11, 13 are zero, only the output of this delay member 6T is multiplied by h7=1/2. The sampled values obtained at the first delay chain are multiplied by h0√2, h2√2, -h4√2, -h6√2 and, since the pulse response in this example is symmetrical, by h8√2=h6√2, h10√2=h4√2, -h12√2=-h2√ 2 and -h14√2=-h0√2. Then, all M=2nd products are summed to

vr (0)=√2(h0sr (k)-h4sr (k-4)+h6sr (k-8)-h2sr (k-12)),

vi (0)=√2(h0sr (k)-h4sr (k-4)+h6sr (k-8)-h2sr (k-12)),

-vr (2)=√2[h2si (k-2)-h6si (k-6)+h4si (k-10)-h0si (k-14)],

vi (2)=√2[h2sr (k-2)-h6sr (k-6)+h4sr (k-10)-h0sr (k-14)] as well as

vr (3)=[sr (7T)-si (7T)]h7 and

vi (3)=[sr (7T)+si (7T)]h7.

The quantities h0, h2, h4, h6 and h7 are the coefficients of the prototype filter Hprot, the frequency response of which is defined in FIG. 10a. (Filter synthesis as aforementioned).

Exemplary set of coefficients: h0=0, h2=0.018 454, h4=0.090328, h6=0.426 544, h7=0.5.

Since v(1) is identical to 0, these three complex signals v(0), v(2) and v(3) form the complex input signals for the subsequent DFT processor which needs to perform merely a few summations and subtractions:

s1r (2k)=vr (0)-vr (2)+vi (3),

s0r (2k)=vr (0)+vr (2)+vr (3),

s2r (2k)=vr (0)+vr (2)-vi (3),

s3r (2k)=vr (0)-vr (2)-vi (3),

s0i (2k)=vi (0)+vi (2)+vi (3),

s1i (2k)=vi (0)-vi (2)-vr (3),

s2i (2k)=vi (0)+vi (2)-vi (3), and

s3i (2k)=vi (0)-vi (2)+vr (3).

In contrast to FIG. 9, if v(3)=0, μ being an integer number disappears for N=8μ+3; instead v(1)≠0. Otherwise the same relationships result.

Now follows a mathematical description of the digital filter bank for complex input and output signals.

The object is to filter out the complex input signal s(kT)=s(k) from the input spectrum of the frequency multiplex signal by means of the filter Hl (ej2πf/fA), having complex coefficients.

Hl (ej2πf/fA) represents the transfer function of the digital filter bank for channel l.

The pulse response (complex terms are underlined)

hl (i)=h(i)ej2πil/L, i=0, 1, . . . , N-1      (1)

of the complex filter, derived by means of frequency shifting from the real prototype filter h(i)=Hprot (ej2πf/fA), the (complex) output signal results as a product of folding: ##EQU1##

The desired signal, which is related to the sampling frequency fA/M reduced by the factor M≦L, then results as follows: ##EQU2##

Blocks of a length L are now formed for suitable processing where

i=Lp+q, with p=-∞ . . . ∞, q=0, 1, . . . L-1   (4)

Entered into (3), this results in ##EQU3##

The exponential term can here be simplified (p, l, LεN) to

ej2π(Lp+q)l/L =ej2πpl ej2πql/L =ej2πql/L (6)

By abbreviating the values v(kM,q) which are identical for all channels l, there then results: ##EQU4##

This is applicable for channel center frequencies fl=1B.

The realization of Equations (7) is shown essentially in FIGS. 1 and 3. First it is necessary to perform processing (Equation 7a) with the sampling frequency reduced by the factor M to arrive at the complex values v(kM,q); see FIG. 3; here, the parts for calculation of the real portion are identical to those for the calculation of the imaginary portion.

The complex values v(kM,q), l=0, . . . , L-1 must be subjected, as a block, to a DFT of a length L. This optimally utilizes the efficiency of the DFT algorithm (or any desired FFT algorithm) since complex signals are required as input as well as output values.

It is also possible to shift the channel grid by onehalf a channel bandwidth or as desired by n/m (n, mεN; n<m) with respect to FIG. 4, where n and m are integer numbers and n<m.

Then, instead of (1), the following applies: ##EQU5##

Then Equation (5) reads as follows: ##EQU6## and the exponential term (6) n, mε/N, n<m, becomes ##EQU7##

Thus, Equations (7) become ##EQU8##

This also applies generally for channel center frequencies fl =lB+Bn/m.

The complex coefficients ##EQU9## take the place of the originally real coefficients h(pL+q), which, for the calculation of the values n(kM,q), corresponds to doubling the original number of multiplications and additions.

For m=2 and m=4, there also exists the possibility of calculating v(kM,q) by way of ##EQU10## where m=2 is ##EQU11## and m=4 is ##EQU12##

Thus the effort required to calculate v[?](kM,q) of Equation (12a) and v(kM,q) of equation (7a) is identical. Finally, this results in ##EQU13## which generally requires an additional four multiplications and two additions for each q=0, 1, . . . , L-1, if n≠0. Compared with the effort for Equation (11), the effort for Equation (12) is always less if

4L<2N                                                      (13)

which is frequently the case.

Another possibility for m=2 and m=4 is to combine the factors ##EQU14## (Equation 12d) with the DFT to obtain an odd (0DFT), which results in a further reduction of effort.

It is known that any desired digital signal processing network can be converted to a dual function network by transposition. For example, a digital filter bank for the frequency separation of frequency multiplex signals can be converted, by means of the transposition method, into a filter bank for the frequency combination of individual signals into a frequency multiplex signal. For the above described structures, this means that all signal flow directions are reversed (i.e. exchange of input and output, adder becomes branching member, branching member becomes adder, DFT becomes inverse DFT). The method of transposing digital networds is described in the article entitled, "On The Transposition Of Linear Time-Varying Discrete-Time Networks And Its Application To Multirate Digital Systems", Philips J. Res., Volume 33, 1978, pages 78-102.

The invention now being fully described, it will be apparent to one of ordinary skill in the art that many changes and modifications can be made thereto without departing from the spirit or scope of the invention as set forth herein.

The present disclosure relates to the subject matter disclosed in German Application P 36 10 195.8 of March 26, 1986, the entire specification of which is incorporated herein by reference.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4237551 *22 Dec 19782 Dec 1980Granger AssociatesTransmultiplexer
US4241443 *10 Apr 197923 Dec 1980Kokusai Denshin Denwa Co., Ltd.Apparatus for reducing a sampling frequency
US4393456 *19 Mar 198112 Jul 1983Bell Telephone Laboratories, IncorporatedDigital filter bank
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4881222 *4 Mar 198814 Nov 1989Ant Nachrichtentechnik GmbhMulticarrier demodulator
US5247515 *28 Jan 199121 Sep 1993Rockwell International CorporationApparatus for extracting one from many multiplexed signals
US5293382 *1 Mar 19938 Mar 1994Motorola, Inc.Method for FDMA signal multiplexing and demultiplexing
US5535240 *29 Oct 19939 Jul 1996Airnet Communications CorporationTransceiver apparatus employing wideband FFT channelizer and inverse FFT combiner for multichannel communication network
US5587939 *29 Feb 199624 Dec 1996Spar Aerospace LimitedHalf-band filter for a cellular group demultiplexer
US5606575 *1 Feb 199625 Feb 1997Airnet Communications CorporationFFT-based channelizer and combiner employing residue-adder-implemented phase advance
US5867479 *27 Jun 19972 Feb 1999Lockheed Martin CorporationDigital multi-channel demultiplexer/multiplex (MCD/M architecture)
US5926783 *2 Jul 199720 Jul 1999Robert Bosch GmbhSwitchable dividing network
US5946293 *24 Mar 199731 Aug 1999Delco Electronics CorporationMemory efficient channel decoding circuitry
US6091704 *1 Feb 199918 Jul 2000Lockheed Martin CorporationDigital multi-channel demultiplexer/multiplexer (MCD/M) architecture
US635145125 Jul 200026 Feb 2002Bae Systems Information And Electronic Systems Integration, Inc.Digital multi-channel demultiplexer/multiplexer (MCD/M) architecture
US6907083 *1 Feb 200114 Jun 2005R F Engines LimitedFrequency analysis
US699006012 Feb 200124 Jan 2006Bae SystemsPolyphase-discrete fourier transform (DFT) sub-band definition filtering architecture
US709578124 Nov 199922 Aug 2006Northrop Grumman CorporationPolyphase filter with stack shift capability
US7099396 *30 Jun 199829 Aug 2006France TelecomMulticarrier modulation using weighted prototype functions
EP0402742A2 *5 Jun 199019 Dec 1990Victor Company Of Japan, LimitedNoise shaping requantization circuit
WO1992011696A1 *13 Dec 199120 Jun 1992Johan HellgrenA method to reduce the power consumation of a digital filter bank by reducing the number of multiplications
Classifications
U.S. Classification370/210, 370/484
International ClassificationH03H17/02
Cooperative ClassificationH03H17/0266, H03H17/0213, H03H17/0292
European ClassificationH03H17/02C1, H03H17/02F8A, H03H17/02G3
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