|Publication number||US3818245 A|
|Publication date||18 Jun 1974|
|Filing date||5 Jan 1973|
|Priority date||5 Jan 1973|
|Publication number||US 3818245 A, US 3818245A, US-A-3818245, US3818245 A, US3818245A|
|Inventors||Hirasawa M, Suzuki Y|
|Original Assignee||Tokyo Shibaura Electric Co|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Referenced by (20), Classifications (12)|
|External Links: USPTO, USPTO Assignment, Espacenet|
States Patent [191 Suzuki et al.
DRIVING CIRCUIT FOR AN INDICATING DEVICE USING INSULATED-GATE FIELD EFFECT TRANSISTORS Inventors: Yasoji Suzuki, Kawasaki; Masataka Hirasawa, Yokohama, both of Japan Assignee: Tokyo Shibaura Electric Company,
Limited, Tokyo, Japan Filed: Jan. 5, 1973 Appl. No: 321,341
U.S. Cl 307/251, 307/270, 307/304 Int. Cl. H03k 17/00 Field of Search 307/270, 304, 279, 251;
References Cited UNITED STATES PATENTS 7/1966 Theriault 330/35 4/1969 Crawford 330/35 6/1970 White A 307/313 6/l970 French 307/251 LOGIC CIRCUIT June 18, 1974 3,569,737 3/l97l Bauer 307/279 3,675,144 7/1972 Zuk 3,723,749 3/1973 Shapiro 340/336 x Primary ExaminerRudolph V. Rolinec Assistant Examiner-D. P. Davis Attorney, Agent, or Firm-Oblon, Fisher, Spivak, Mc- Clelland & Maier [5 7 ABSTRACT 7 Claims, 4 Drawing Figures INDICATING PATENTEDJUH 18 I974 AVALANCHE BREAKDOWN VOLTAGE VB(VOLT) EXPERIMENTAL DATA FIGl P(HANNEL o N CHANNEL 0 THEORETICAL DATA 10 PCHANNEL CHANNEL 0 l llllllll l llllllll I llllllll l llllllll V IMPURITY(0NCENTRATION NCI Na(Cm 00 V55 /B i wg/g me 4 f Fm I7 12 V A A LOGIC CIRCUIT 4 F 2 DD v v ss IND/(ATING TUBE Ila Ilb 1 I3 v INDICATING I7 55 TUBE A 3/ LOGIC H CIRCUIT 17 LOGIC, I2\ CIRCUIT .l l
DRIVING CIRCUIT FOR AN INDICATING DEVICE USING INSULATED-GATE FIELD EFFECT TRANSISTORS BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates generally to a driving circuit for an indicating device, and more particularly to a circuit which uses insulated-gate field effect transistors to operate as a high voltage driver.
2. Description of the Prior Art Recently Digitron (TM)and Nixy (TM) tubes, for example, have been widely used as indicating devices in electronic desk top calculators. The Digitron tube is particularly popular at present but its driving voltage is very high in general. For example, the driving voltage is usually in the range from about 50V to 60V. Today, however it is desirable that elements such as insulatedgate field effect transistors (hereinafter called IGFET or simply FET or Transistor) for driving Digitron tubes be fabricated in chips of semiconductor materials forming integrated circuits (IC or LSI). It is therefore desirable to design FET circuits which could be used for driving Digitrons and the like, but is generally impossible to use the FET for such circuits because of the inherent properties of the FET. Namely, before the walkout phenomenon, that is, the avalanche break-down voltage changes to a high value due to charging of the gate oxide layer of an FET as a result of electrons and positive holes in avalanche flying into the gate oxide layer, the avalanche break-down voltage of the PET is very low. For example, if an impurity concentration Nd of a semiconductor substrate of a PET is 9 X 10 cm, and the thickness of the gate oxide layer of the FET is 2,000A, the avalanche break-down voltage of the FET is as low as about 45V before the walk-out phenomenon. Therefore the FET whose avalanche break-down voltage is about 45V could not drive the Digitron tube whose driving source must be from 50V to 60V. For better understanding of this problem, FIG. 1 shows theoretical and experimental data of the characteristic relations between avalanche break-down voltage V (before the walk-out phenomenon) and the impurity concentrations of a semiconductor substrate, Nd and Na of P and N channel conductivity type FETs in the case where the thickness of gate oxide layer d 2,000A and the gate voltage Vg is zero volts. In the calculation of the theoretical data, B was set at 1.43 (determined by the thickness of the gate oxide layer and the dielectric constant of the silicon substrate) and the thickness of the gate oxide layer do= 0.36 pm (P channel type) while do= 0.28 pm (N channel type). It is apparent that the avalanche break-down voltage of a PET which has been fabricated using integrated circuit manufacturing techniques is distributed near approximately 45V.
If it is desired to fabricate an IC or L8] including a driving circuit for an indicating tube using one or more FETs, however, it is necessary in the manufacturing steps to evelate the avalanche break-down voltage. For example, one counter-measure is that of increasing the thickness of the gate oxide layer, so than an IC or LSI indicating tube driving circuit including a PET can be manufactured. However, the above described countermeasure will have a bad influence on other circuit elements fabricated in the same semiconductor chip with the driving cirucit, since the threshold voltage of these elements will undesirably become a high voltage. Thus, if the driving circuit and another logic circuit are fabricated together in the same chip using the above described countermeasure, the other logic circuit may lose its properties because the threshold voltage becomes too high. A manufacturing method wherein the thickness of the gate oxide layer is increased only for the PET in the driving circuit was considered, but this method requires two manufacturing steps for forming oxide layers, one of which is for the driving circuit and the other of which is for the other logic circuit. Thus, this method is not practical, since it requires additional complex manufacturing steps.
SUMMARY OF THE INVENTION Accordingly, one object of this invention is to provide a novel driving circuit for an indicating device which uses an insulated-gate field effect transistor whose avalanche break-down voltage is elevated in the usual manufacturing steps.
Another object of this invention is to provide a novel FET driving circuit which can drive a high voltage indicating device.
Another object of this invention is to provide a novel integrated circuit which comprises a driving circuit and another logic circuit.
Another object of this invention is to provide a novel driving circuit, the driving voltage of which can be easily controlled.
Another object of this invention is to provide a novel integrated circuit including insulated-gate field effect transistors wherein a high voltage driving circuit is provided without undesirably influencing another circuit fabricated in the same integrated circuit.
Briefly, according to the present invention these and other objects are achieved by providing a driving circuit for an indicating device using insulated-gate field effect transistors comprising a first insulated-gate field effect transistor of one channel conductivity type whose gate is supplied with a bias potential to operate in the saturation area. A second insulated-gate field effect transistor of the same channel conductivity type is also provided whose gate is supplied with a driving signal as an input signal. A series connection is provided between the first and second transistors including a first connection between one terminal and the first transistor providing an output signal to drive an indicating device. A second common connection is provided between the first transistor and the second transistor, and a third connection is provided between the second transistor and another terminal. Both transistors are coupled in series across a driving source.
BRIEF DESCRIPTION OF THE DRAWINGS A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
FIG. 1 is a graphical diagram illustrating the characteristic curves of the FET used in the present invention and showing the relationships between avalanche break-down voltage and impurity concentration in channels of P and N conductivity type;
FIG. 2 is a schematic diagram of one embodiment of the circuit of this invention illustrating a driving circuit including two FETs and a load resistor; FIG. 3 is a schematic diagram of another embodiment of the circuit of the present invention, showing a driving circuit connected in series with an indicating device; and
FIG. 4 is a schematic diagram of yet another embodiment of the circuit of the present invention, showing a driving circuit for a high voltage driving source using a plurality of FETs operable in the saturation area.
DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, and more particularly to FIG. 2 thereof, the basic driving circuit of this invention is shown.
A resistor and FETs 11 and 12 are shown connected in series between two terminals V and the earth or negative potential of a driving source. The driving source is called the high voltage source, hereinafter, because while IGFETs in integrated circuits usually require only several volts as a driving source, this invention uses 50V to 100V as a driving source for an indicating tube. An indicating tube 13 such as a Digitron tube, for example, is connected to a node 16 of the load resistor 15 and the FET 11 as an output. Instead of the indicating tube, a plasma display device may be used, when devices of this type are required as indicating devices. The FET 11 is supplied at its gate with a predetermined bias voltage V (negative voltage) and the other FET 12 is supplied at its gate with a driving signal, such as an input from a logic circuit 14. The logical information used as an input signal controls the application of power from the high voltage source V,,,, to the indicating tube 13 to drive it in accordance with ON and OFF switching of the FET 12 determined by the logical information. The drain of the FET 11 is connected through the load resistor 15 to the driving source V The node 16 of the resistor 15 and the drain of the FET 1 l is connected as a first output to the indicating tube 13. The source electrode of the FET 11 is also connected to the drain of the FET 12, forming a second output. Furthermore, the source of the FET 12 is connected to earth potential and the substrate of the FETs 11 and 12 is also connected to the earth potential respectively. It is noted that the source, drain, gate and substrate electrodes of the FETs l1 and 12 are simply described above as the source, drain, gate and substrate.
In this configuration, since the source voltages used herein are related such that I V I I V I in general, the FET 11 is ON when the FET 12 is OFF, so that:
I DD I I SS Ihl1I I V. V I for saturation operation of the FET 11.
As a result, there is no problem of over supplying the gate oxide layer of the FET 12 with a voltage greater than the avalanche break-down voltage, since the voltage supplied at the drain of the FET 12 is I V V I and there exists the relation I V I I V I Even if V V and V is the avalance break-down voltage, there is no risk that the drain voltage of FET 12 may be the attenuated threshold voltage V of the FET l1. Especially if the bias potential V approaches that of the driving source V a more favorable result will occur because of the increasing absolute value of the threshold voltage V For example, when it is assumed that the impurity concentration of the substrate Nd 6 X 10, the thickness of the gate oxide layer a 2,000A, the bias potential V 24V and the driving source V 6OV, the threshold voltage of the FET 11, V becomes about 7V, and then the drain of the FET 12 is supplied with l7V. On the other hand the voltage between the source and the drain of the FET 11 is:
oull mrzz I I VDD ss lhll) TM I outl out2i The supplied voltage of the FET 11 is 43\/, which is less than the avalanche break-down voltage (about 45V) of the usual FET. This explanation assumes that the FET 12 is OFF, but when the FET 12 is ON, it is apparent that there is no problem about the avalanche break-down voltage.
In the above described embodiment, the drain of the FET 11 is connected through the load resistor 15 to the driving source V and the node 16 of the drain and the resistor 15 is connected to the indicating tube 13. However without limitation of this embodiment, another embodiment of the invention is illustrated in FIG. 3 wherein the drain of the FET 11 is connected through the indicating device 13 to the driving source V Furthermore, if the driving source used is desired to be more than that of the first embodiment in absolute value, a preferred embodiment for such purpose is illustrated in FIG. 4. FETs 11a and 11b, which operate always in the saturation area, are connected in series to be able to endure a backward voltage across the PN junction of the FET 12. It is easily understood that further FETs operable in saturation area may be connected in series with the FETs 11a and 11b for constructing even higher voltage driving sources.
It is pointed out that, although all of the illustrated embodiments use P channel conductivity FETs, the invention has the same advantages when N channel conductivity type FETs are used instead of P channel FETs.
Furthermore, all of the above embodiments are described as drivers for indicating tubes such as Digitrons. However, this invention is not limited to use with indicating tubes. For example, MOS integrated circuits including the driving circuit of this invention may be advantageously used as high voltage drivers for virtually any purpose.
Obviously, numerous additional modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.
What is claimed as new and desired to secure by letters patent of the United States is:
l. A driving circuit for an indicating device using insulated-gate field effect transistors comprising:
a first insulated-gate field effect transistor of one channel conductivity type whose gate is supplied with a bias potential;
a second insulated-gate field effect transistor of said one channel conductivity type whose gate is supplied with an input logic driving signal;
a series connection of said first and second transistors including a first connection between an output terminal and said first transistor providing an output signal to drive an indicating device, a second common connection between said first transistor and said second transistor, and a third connection between said second transistor and a second terminal; and
a power source having a voltage magnitude greater than avalanche breakdown of said first-and second transistors connected across said first and second transistors wherein said bias potential is of a magnitude which maintains said first transistor in saturation when said second transistor is in an off condition whereby avalanche breakdown in each of said transistors is prevented.
2. A driving circuit for an indicating device using insulated-gate field effect transistors as in claim 1, further comprising:
a load resistor coupled between said power source and said output terminal.
3. A driving circuit for an indicating device using insulated-gate field effect transistors as in claim 2, wherein:
said indicating device is coupled to said load resistor and to said first transistor.
4. A driving circuit for an indicating device using insulated-gate field effect transistors as in claim 1, wherem:
said indicating device is coupled in series between said power source and said first transistor.
5. A driving circuit for an indicating device using insulated-gate field effect transistors as in claim 1, further comprising:
a third transistor coupled to said first transistor and through said common connection to said second transistor.
6. A driving circuit for an indicating device using insulated-gate field effect transistors as in claim 5, further comprising:
a load resistor coupled between said power source and said output terminal.
7. A driving circuit for an indicating device using insulated-gate field effect transistors as in claim 5, wherein:
said indicating device is coupled in series between said power source and said first transistor.
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|U.S. Classification||326/80, 326/83, 327/546|
|International Classification||H03K17/18, H03K19/0944, H03K19/003|
|Cooperative Classification||H03K17/18, H03K19/09441, H03K19/00315|
|European Classification||H03K19/003C, H03K19/0944B, H03K17/18|