US 3751718 A
An electric locking system including an electrically operated door latch wherein the latch is energized by a signal derived from logic circuitry. The system is provided with a switch and a timing light; the initial closure of the switch activates the timing light for successive periods of time. During each of the successive periods of time, a memory register is enabled and activation of the switch during one of these periods of time will result in the storage of a binary one in the memory register. When the timing light has been energized and the memory register enabled a predetermined number of times, a logic gate is enabled and the contents of the memory register are applied to the gate; if the contents of the memory register coincide with a preselected binary code, an unlocked signal causes the energization of the electrical latch mechanism to thereby unlock the door.
Description (OCR text may contain errors)
United States Patent [1 1 Hanchett, Jr.
[ Aug.7, 1973 I PROGRAMMABLE ELECTRIC LOCKING  ABSTRACT SYSTEM An electric locking system including an electrically op- [7 l lflvenlori Leland J- J 3 erated door latch wherein the latch is energized by a l p fl Ariz. 85028 signal derived from-logic circuitry. The system is pro- Izzl med N0 M 1972 vided with a switch and a timing light; the initial closure of the switch activates the timing light for successive l PP NOJ 307,120 periods of time. During each of the successive periods I of time, a memory register is enabled and activation of  U d 317/134 70/278 307/ AT the switch during one of these periods of time will re- 340/164 sult in the storage of a binary one in the memory regis- [511 Im Cl Eosb 49/00 ter. When the, timing light has been energized and the  Field 307/10 memory register enabled a predetermined number of R A 164 times, a logic gate is enabled and the contents of the memory register are applied to the gate; if the contents [561 References Cited of the memory register coincide with a preselected binary code, an unlocked signal causes the energization v D. STATES PATENTS of the electrical latch mechanism to thereby unlock the 3,600,637 8/l97l Bergkvist 340/164 A do Y 3,463,9ll 8/ l969 Dupray et al. 340/149 R 3,57l,800 3/1971 Taylor et al 340/164 R 7 Claims, 2 Drawing Figures Primary Examiner-L D. Miller Assistant Examiner-Harry E. Moose, .lr. Attorney-William c. Cahill et al.
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The present invention pertains to locking systems, and more particularly, to an electrically actuated lock that is activated upon the receipt of a predetermined code.
Many schemes have been suggested in the prior art for electrically activating a door latch, including several schemes wherein a predetermined code must be entered into the system by an operator before the latch mechanism becomes energized. These prior art systems usually incorporate a relatively complex keying or switching system calling for the manipulation of numerous switches or dials. The complexity of these priorart systems usually militates against their use for residential environments; further, the shortcomings of these systems has also effectively precluded their use in vehicular applications.
The use of a predetermined code for electrical operation of a door lock presents significant benefits in addition to the obvious ones concerning the loss of keys from ordinary locks or the possible interchangeability of keys or the existence of master keys. These unexpected advantages, particularly in vehicular applications, results from the availability of a parameter other than a code as a requirementfor the energization of the locking system of the present invention. This additional parameter, namely time, presents a certain requirementof co-ordination and a skill on the part of the operator to effectuate a door unlocking. The complexity or difficulty of this time requirement may easily be adjusted and the vehicular applications may be set to preclude entry to the vehicle to. even the owner thereof if his condition is such that he is incapable of sufficient co-ordination to safely drive the vehicle. This latter feature may be of substantial significance in preventing persons under the influence of alcohol or drugs from gaining access to their vehicles during such periods of influence; the system also insures that the door is locked upon each closure.
- It is therefore an object of the present invention to provide aninexpensive and rugged electric locking system requiring. the use of a code for unlocking.
It is another object of the ,present invention to provide an inexpensive and rugged electric locking system requiring the use of a code for unlocking, and wherein the code is entered serially into the system by the operator. i
It is still another object of the present invention to :provide a programmable electric locking system wherein the codemust be entered in a prescribed timed sequence.
It is a further object of the present invention to provide a programmable eletric locking system wherein the code for unlocking may -be changed.
These and other advantages of the present invention will become apparent to those skilled in the art as the description thereof proceeds.
Thepresent invention may be-described by reference to the accompanying drawings, in which:
FIG. I is a schematic illustration, partially broken away, showing the placement of the system in a vehicular door.
FIG. 2 is a schematic diagram of the locking system of the present invention,
Referring now to FIG. 1, a vehicle is schematically illustrated at 16 and includes a door 11 having a conventional door handle 12. The door may include the usual mechanical latch operated by the handle 12. An electrically operated latch 13 is shown schematically and is operated in a conventional solenoid manner through the use of a solenoid coil 14. A switch 15 in the form of a pushbutton is provided while the switch 15 is also illuminated; the light (not shown) for backlighting the switch 15 serves as the timing light, as will be explained more fully hereinafter.
Referring now to FIG. 2, the system of the present invention incorporates a timer 20 including a potentiometer 22 that may be used for varying the frequency of the timing signals generated by the timer 20. The timer may be constructed by any of several well known techniques or circuits and is simply a free running oscillator having an adjustable oscillation frequency. A typical timer that can be used is manufactured and sold by Sig netics and is designated as their 555 timer.
The timing signals generated by the timer 20 are applied to a cycle counter 24 which receives and counts the timing signals and generates a cycle signal in response to each successive predetermined number of timing signals. Circuits that may be used in the cycle counter are numerous and may take the form of a standard circuit chip known as a 7493 chip. Theresulting cycle signals are of a duration and frequency depending on the adjustment to potentiometer 22 and thus-the frequency of oscillation of the timer 20. In the embodiment chosen for illustration, it has been found that a cycle signal duration of two seconds with a two-second interval between cycle signals is appropriate. A cycle signal from thecounter 24 is applied to a memory register 26 and enables each of the ten memory cells 1 10. As the cycle counter counts from 1 to 10, the memory register 26 is therefore enabled for ten cycle periods; during each of these enabling times, succeeding memory cells 1 10 are made available for the storage of a binary one or a binary zero.
A switch 30, when closed, applies a binary one to'the memory register through gates 31, 32, and 33 con-' nected to form a latch. Initial closure of the switch 30 applies a signal through gates 34 and 35 connected as a monostable multivibrator to the cycle counter 24 to initiate the counting cycle; upon completion of counting to eleven, the cycle counter is automatically reset through the application of the signal CCI] from the cycle counter through the gate 38 and back to the cycle counter 24. The initial-closure of the switch 30 therefore starts the cycle counter and, as explained previously, enables the memory register for successive periods. Subsequent closure of the switch 30 during any one of these timing periods will result in the insertion of a binary one in a memory cell of the memory register. If the switch 30 is left in its open position during one of the cycle times, a binary zero is stored in the memory cell. The memory register is a typical shift register memory circuit readily available in a variety of forms; atypical register suitable for use as a memory register 26 is known as Signetics 8273, serial in, parallel out, 10 bit register.
The cycle signals from the cycle counter 24 are also applied to a timing light 40 which may take the form of a simple neon lamp positioned within the switch 30 to backlight the pushbutton 15 (FIG. 1) forming the switch. However, an alternate timing light arrangement has been chosen for illustration in FIG. 2. The timing light 40 comprises a seven segment numerical :display 41 connected to receive appropriate display signals from a display decoder and driver 42. The decoder 42 and display 41 are commonly packaged as a unit and are available from numerous manufacturers. With the timing light 40 of the type shown in the embodiment in FIG. 2, the light will not only provide a visual indication to the operator when the memory register has been enabled and the switch 30 is to be closed if a binary one is to be inserted in the register, but will also provide an indication to the operator of the code digit position which is presently being entered in the memory register.
Upon completion of ten cycle signal counts, a count completion signal CC 10 is generated by thecycle counter and is applied to gates 45 and 46. The contents of each of the memory cells 1 10 are applied to inverters 51 60. The outputs of the respective inverters are bypassed and the inverted contents of each of the memory cells 1 10 as well as the uninverted contents thereof are presented .to switches 61 70. These switches may be positioned to connect either the contents of the respective memory cells or the inverted contents of the respective memory cells to logic gate 75. Thus, the embodiment shown, if the contents of the m emory cells 1 10 correspond tothe binary number 1111100011, an output from the gate 75 will be generated. This output is inverted in inverter 76 and applied to the gate 45 while the uninverted output is applied to the gate 46. Each of the gates 45 and 46 has been enabled by the cycle counter signal CC10.
In the embodiment chosen for illustration, a signal from the 'gate 75. indicating that the binary contents of the memory cells 1 l correspond with that selected in the switches 61 70 will result in an unlocking signal from the gate 45 applied to the terminal 77. If desired, a logic level or signal from the logic gate 75 indicating a code in the memory register not corresponding to the setting of the switches 71 70 will result in the generation of an alarm signal from the gate 46 to the terminal The inverters and logic gates shown in FIG. 2 may take the form of any of several well known and comterminal 77 which will result in energization of the solenoid winding 14 and retraction of the latch 13 (FIG. 1) and 14 (FIG. 1). lf the contents of the memory cells 1 do not correspond to the setting of the switches 61 70 at the cycle counter signal CC10, then an alarm signal is provided at terminal 78. A cycle counter then counts to eleven and generates the signal CCl 1, which then resets the cycle counter and the system is available to repeat the operation.
The signals available at terminals 77 and 78 may be utilized in any conventional manner to operate the door latch or door alarm. As used herein, the term latch includes other structure that is sometimes used to accomplish the function of the latch, such as a break-open cavity or recess used in connection with a fixed latch. The alarm signal may be connected to sound the vehicle horn or, in residential applications, the alarm may simply be the door bell. Since the signals available at terminals 77 and 78 are basically logic levor the alarm.
bined into a single timing means if the free running oscillator comprising the timer is chosen so that the fre quency of the signals produced thereby is low enough to permit the switch 30 to be operated in the normal reaction time of the operator. In the event that'the cycle counter is eliminated by using such a timing means", the signals CC10 and CCll can be dispensed with and the equivalent logic signals derived directly from the memory register 26. The timing light can then' derivea timing signal either from the timing means or directly from the memory register as the latter is cycled'by the timingsignal.
The utilization of a timing means, coupled with the timing light, to indicate to the operator when toactivate the switch 30 provides a serial in, parallel out, logic system for entering a code to unlock a door; fur- .ther, the superimposition of the timing requirements on mercially available logic circuits or-circuit chips. For
example, logic gates31, 32, 34, 35, 38, 45, 46, and 75 are of the well known 7400 series commercially avail-' able from numerous manufacturers, including Texas Instruments. I v I Y I The operation of the system of the present invention may now be described. The operatorwhodesires to open the door 11 of the vehicle shown in FIG. 1 at 16 initially depresses'the backlighted switch 15 which corresponds to the switch 30 in FIG. '2. This initial closure of the-switch 30 results in theinitiation of a countdown by the cycle counter 24 and results in the illumination of the timing .light 40. Thetimirig light thereafter successively is energized and de-energized, remaining energized for a predetermined period such as 2 seconds. During this two-second period of energization of the timing light, the memory register 26 has been enabled and subsequent closure of the switch 30 during this enabling time period will result in the insertion ofa binary one in the corresponding memory'cell in the memory register 26. When the cycle counter has completed acount of ten, the cycle counter signal CC10 will enable gates 45 and 46. lf'the contents of the memory cells 1 10 correspond to the setting of the switches 61 70,
the code to be entered into the system requires a predetermined minimum co-ordination on the part of the operator. I
1. A programmable electric locking system including nals for storing a binary one or a binary zero during each succeeding timing signal; means connecting said switch to said memory register forentering binary ones or binary zeros during each timing signal; means connecting said timing signal to said timing light for energizing said light to indicate to an operator when said switch may be operated to enter binary onesor binary zeros in said memory register; a decoding circuit connected to said memory register and responsive to a predetermined combination of binary ones or binary zeros stored'in said memory register'for generating an un locking signal for energizing said electrically operated door-latch.
2. A programmable electric locking system including an electrically operated .door latch comprising: a
The cycle counter 24 and the timer 20 may be com-.-
switch; timing means for generating timing signals; a cycle counter connected to receive said timing signals and to generate a cycle signal in response to each successive predetermined number of timing signals; a memory register connected to receive said cycle signals for storing a binary one or a binary zero during each succeeding cycle signal; means connecting said switch to said memory register for entering binary ones or binary zeros during each cycle signal; means connecting said cycle signal to said timing light for energizing said light to indicate to an operator when said switch may be operated to enter binary ones or binary zeros in said memory register; a decoding circuit connected to said memory register and responsive to a predetermined combination of binary ones and binary zeros stored in said memory register for generating an unlocking signal for energizing said electrically operated door latch.
3. The combination set forth in claim 2, wherein said memory register includes a plurality of memory cells, each for storing, when enabled, a binary one or a binary zero and wherein each succeeding cycle signal received by said memory register enables said memory cells.
4. The combination set forth in claim 3, wherein said memory register is a serial in, parallel out, binary register for serially receiving binary information for storage therein and for providing said stored binary informa tion in parallel.
5. The combination set forth in claim 3, wherein said timing light'includes an indicator for numerically indicating the code digit position then being encoded by said switch.
6. A programmable electric locking system including an electrically operated door latch, comprising: a switch; a timing light visible to an operator of said switch; a free running oscillator having an adjustable frequency of oscillation for generating timing signals; a cycle counter connected to receive said timing signals and to generate a cycle signal in response to each successive predetermined number of timing signals, said cycle counter connected to said switch and responsive to an initial closure of said switch to initiate counting of said timing signals and generation of said cycle signals by said cycle counter; a memory register connected to receive said cycle signals and having a plurality of memory cells, each for storing, when enabled, a binary one or a binary zero, each succeeding cycle signal received by said memory register enabling said memory cells; means connecting said switch to said memory register for entering binary ones or binary zeros in said memory cells when said cells are enabled; means connecting said cycle counter to said timing light for energizing said light when said counter generates cycle signals to indicate to an operator when said memory cells are being enabled; a decoding circuit connected to said memory register and responsive to a predetermined combination of binary ones and binary zeros stored in said memory cells for generating an unlocking signal.
7. The combination set forth in claim 6, wherein said decoding circuit includes an inverter connected to each of said memory cells for inverting the binary contents thereof and wherein said decoding circuit includes a plurality of switches, each corresponding to a different one of said memory cells, each of said switches positionable to connect the contents of the corresponding memory cell or the inverse of the contents of the corresponding memory cell to a logic gate.