Publication number | US3711692 A |

Publication type | Grant |

Publication date | 16 Jan 1973 |

Filing date | 15 Mar 1971 |

Priority date | 15 Mar 1971 |

Publication number | US 3711692 A, US 3711692A, US-A-3711692, US3711692 A, US3711692A |

Inventors | Batcher K |

Original Assignee | Goodyear Aerospace Corp |

Export Citation | BiBTeX, EndNote, RefMan |

Patent Citations (3), Referenced by (179), Classifications (8), Legal Events (1) | |

External Links: USPTO, USPTO Assignment, Espacenet | |

US 3711692 A

Abstract

An arrangement for counting the number of a given data such as ones in a data field. The system employs full adders which count the number of ones in basic three element subsets of the data field. Additional full adders total the results of the first series of full adders and also count any additional ones of the data field.

Claims available in

Description (OCR text may contain errors)

United States Patent Batcher [451 Jan. 16, 1973 [54] DETERMINATION OF NUMBER OF 3.466.433 9/969 Dudact al .235/l75 3,603,776 9/!97] Wcinherger ..235/l75 ONES IN A DATA FIELD BY ADDITION [75] Inventor: Kenneth E. Batcher, Stow, Ohio [73] Assignee: Goodyear Aerospace Corporation,

Akron, Ohio [22] Filed: March 15, 1971 [2]] Appl. No.: l24,08 9

[52] US. Cl ..235/l75 [51] Int. Cl ..G06f 7/50 [58] Field of Search ..235/l75, 92, 92 CP, 92 SA [56] References Cited UNITED STATES PATENTS 3,535,502 l0/l970 Clapper ..235/l75 X Primary Examiner-Eugene G. Botz Assistant ExaminerDavid H. Malzahn Att0rney.l. G. Pere and L. A. Germain [57] ABSTRACT An arrangement for counting the number of a given data such as ones in a data field. The system employs full adders which count the number of ones in basic three element subsets of the data field. Additional full adders total the results of the first series of full adders and also count any additional ones of the data field.

5 Claims, 3 Drawing Figures OUTPUT PATENTEDJAN 1 6 I973 SHEET 2 0F 2 mmE INVENTOR KENNETH E. BATCHER WWW,

ATTORNEYS DETERMINATION OF NUMBER OF ONES IN A DATA FIELD BY ADDITION It is the primary object of the present invention to provide means for counting the number of occurrences ofa given value in a data field.

It is also an object of the invention to provide means for counting the number of occurrences of a given value in a data field which provides for the fast counting of the selected value occurrences.

The above and other objects of the invention which will become apparent in the following detailed description are achieved by providing a counting arrangement in which a first series of full adders count the number of occurrences of a selected value simultaneously in three element subsets of the data field, and includes an additional series of full adders for combining the totals produced by each of the adders of the first series.

For a more complete understanding of the invention and the objects and advantages thereof reference should be had to the following detailed descriptionand the accompanying drawings wherein there is shown a preferred embodiment of the invention.

In the drawing:

FIG. 1 is a schematic showing of the counting arrangement of the present invention for a six element field;

FIG. 2 is a schematic showing of the counting arrangement for a seven element field; and

FIG. 3 is a schematic showing of a counting arrangement for a fifteen element field.

The data fields referred to in the following description may be stored in any suitable data storage means, such as the response store of an associative memory or associative processor. Regardless of the particular storage device involved, the data is stored as individual bits in the usual digital manner each having a O or 1 value.

FIG. 1 shows a six element data field 10 and illustrates the basic concept of the present invention. Each of the elements b of the data field 10 may have either a or. I value. While the elements are shown grouped into two sets of three elements each, this is for illustration only and the data field is not necessarily so arranged physically. In order to count the total number of bits b which are of a particular value, for example which have the value 1, there is provided an arrangement of full adders 12-18. A typical full adder would be a MCl0l9 integrated circuit manufactured by Motorola Semiconductor Products, Inc.. Each of the full adders 12-18 is capable of receiving three binary inputs and adding these inputs to produce the two digit binary sum thereof, with the least significant digit of the sum being produced at the output s and the more significant digit being produced at the output 0. The full adder 12 receives as inputs the values of three of the bits of the data field 10 and the full adder 14 receives as inputs the values of the remaining three data bits. If the data field is expressed in a form other than a binary code, converting means may be provided between the elements of the field and the full adders. Such converting means produces a 0 output if the element is not of the selected value and a 1 output if the element is of the selected value. Thus, the full adders 12 and 14 will simultaneously produce the total count of the 1's in their respective subsets of the data field 10. A third full adder 16 receives as inputs the least significant digit outputs of the first full adders l2 and 14. The output of this full adder 16 represents the sum of the least significant digits of the outputs of the adders I2 and 14. The least significant digit of the output of the adder 16 is thus the least significant digit of the sum of the 1's in the data field 10. This digit is supplied to the output device 20. A fourth full adder 18 receives as inputs the most significant digit output of the full adder l6 and the most significant digit outputs of the full adders I2 and 14. The least significant digit of the addition performed by the full adder 18 is the second significant digit of the total count while the most significant digit of the output is the most significant digit of the full count. Thus, the output of the least significant digit of the full adder l6 and the full output of the adder 18 comprise the full count of the number of ones in the data field 10.

FIG. 2 illustrates the arrangement of full adders employed with a data field 22 having seven elements. A first set of full adders 24 and 26 each count the values of three positions of the data field 22. An additional set of full adders 28 and 30 count, respectively, the single previously uncounted bit value of the data field 22, the least significant digits of the outputs of the counters 24 and 26, and the most significant digit of the output of the counter 28 and the most significant digits of the outputs of the counters 24 and 26. Again, the least significant digit output of the counter 28 is the least significant digit of the total count while the outputs of the full adder 30 provide the second and third significant digits of the total count. These three outputs are supplied to the output device 32 and represent the total count of the number of l s in the data field 22.

The basic counting system described in the above paragraphs may be expanded to count the number of ls in a field of any length. Essentially, this is accomplished by dividing the data field into subsets which may be counted by one of the counting arrangements described above and by adding the totals achieved for each subset by means of additional full adders. Thus, as is shown in FIG. 3, a fifteen element data field 48 may be divided into three subsets: S, which consists ofa single bit of the data field 48, S which consists of the next seven data bits of the field 48; and S which consists of the remaining seven data bits. It should be noted that the order in which the data field 48 is divided into the subsets S S and S is purely arbitrary. The arrangement shown in which the first element is assigned to the subset the next seven elements to the subset S ,-and the remaining seven elements to subset S is chosen for convenience of illustration. However, any other arrangement may be employed so long as the subsets S and 8;, are of equal length and the subset S, contains not more than one element.

The total count of 1's in the subsets S and 8;, may be determined by full counters 50 and 52 which are each equivalent to the full adder arrangement of FIG. 2. The counts produced by the seven position counters 50 and 52 and the count of the least significant bit subset S are added by means of additional full adders 54-58. These full adders 54-58 add, respectively, the least significant digit values, the next most significant digit values and the carry value of the previous adder, and the most significant digit values and the carry value from the previous adder. The outputs of the full adders 54-58 provide the successively higher ranked significant digits of the total count and these outputs are furnished to the output device 60. It should be noted that the maximum time required to achieve the total count of the number of I s in the data field is equal to the delay imposed by a full adder multiplied by the total number of full adders involved in producing one digit of the output or final count. Referring again to the arrangement of FIG. 3 it will be seen that the maximum delay is five times the delay of one full adder. Since the adders 62 and 64 operate simultaneiously these two full adders impose only one time delay in the count. The adder 68, however, receives inputs both from the adder 62 and from the full adder 66. As a result, two additional delays are imposed. Likewise, the full adder 56 receives inputs both from the adder 68 and the adder 54 so that two additional time delays are again imposed. In general, if a field having 11 bit positions can be counted with a maximum delay of P full adders, a field having 2n 1 bit positions can be counted with a maximum delay off 2 full adders. For a field having 2" 1 bit positions, where m is greater than or equal to 2, the maximum delay will be 2m 3 multiplied by the delay of one full adder.

The counting arrangement of the present invention is applicable to date fields of any length. The data field is first divided into three primary subsets S S and S with the subsets S and 8;, being of equal length and the subset S containing at most a single element. The subsets S,, S and 8;, are mutually exclusive and exhaust the elements of the data field. lf the primary subsets S and 8;, each contain more than three elements, they are further divided into secondary subsets S S and S and S S and S respectively. The secondary subsets are also mutually exclusive and exhaustive of the elements of their respective primary subsets. The division of the primary subsets is accomplished in the same manner as the original division of the data field. Thus, the subsets S and S are of equal length and the subset S is either void or contains a single element, depending on whether the primary subset S contains an even or odd number of elements. Division of the multiple element subsets is continued in the same manner until a series of ultimate subsets, none of which contains more than three elements of the data field, is achieved.

A full adder is provided for each of the ultimate subsets which contains more than a single element. The full adders produce the counts of the number of 1's in the multiple element ultimate subsets. The counts of the penultimate subsets are obtained by means of additional full adders, two additional full adders being provided for each penultimate subset with one full adder combining the count of the single element subset, if present, and the least significant digit outputs of the ultimate subset adders and the second full adder combining the most significant digit of the output of the first full adder and the most significant digits of the ultimate subset full adders. By means of additional full adders arranged in the same manner, the counts of the successive subsets of the hierarchical rank of the subsets are obtained. The final series of adders combines the counts of the subsets 5,, S and S to produce the total count for the entire data field.

It will be understood that while only the best known embodiment of the invention has been described in detail, in accordance with the Patent Statutes, the invention is not so limited. Reference should therefore be had to the appended claims in determining the true scope of the invention.

What is claimed is:

1. The method of determining the number of occurrences of a selected value in a data field having at least fifteen elements, which comprises the steps of l. dividing the data field into mutually exclusive, ex-

haustive subsets S S and S where S, and S, are of equal length and 8, includes at most one element of the data field;

2. counting the occurrences of the selected value in each of the subsets S, and S 3. adding, by means ofa full adder, the number of occurrences of the selected value in subset S and the least significant digit of the count of each of the subsets S and S 4. adding, by means of an additional full adder, the most significant digit of the output of the previous full adder and the next significant digit of the count of each of the subsets S and S 5. repeating step (4) until all the digits of the count of each of the subsets S, and 5;, have been exhausted, an additional full adder being employed for each addition; and

6. transmitting to an output device the least significant digit of the output of each full adder and both digits of the output of the last full adder, the least significant digit of the output of the first full adder being the least significant digit of the total count, the least significant digits of the outputs of successive full adders being the successive digits of the full count, and the most significant digit of the output of the final full adder being the most significant digit of the full count.

2. The method according to claim 1 wherein the count of each multiple element subset of the data field is determined by the steps of:

a. dividing .the subset into three mutually exclusive, exhaustive subsets, the first-of which has at most one element, a second and third of which are of equal length;

b. determining if any subset produced in the immediately preceeding division contains more than three elements;

c. dividing all elements produced in the immediately preceeding division which contain more than three elements into three subsets satisfying the conditions of step (a);

. repeating steps (b) and (0) until an ultimate series of subsets no one of which contains more than three elements is obtained;

e. summing, by means of full adders, the number of occurrences of the selected value of each ultimate subset having more than one element; and

f. by means of additional full adders, progressively combining andadding to the sums the number of occurrences of the selected value in those subsets having one element in the reverse order of their creation in steps (a) through (d) until the total count of each multiple element subset has been achieved.

3. Apparatus for counting the number of occurrences of a predetermined value in a data field of at least fifteen elements, comprising:

first and second counting means for counting the number of occurrences in first and second portions, respectively, of the data field, the first and second portions being non-overlapping, of equal length, and including at least all but one element of the data field;

a first full adder receiving as inputs the value of the data field element excluded from the first and second portions and the least significant digits of the output of the first and second counting means;

additional full adders receiving as inputs, respectively, the more significant digit output of the preceeding full adder and the succeedingly more significant digits of the outputs of the first and second counting means; and

an output device receiving the least significant digit outputs of each full adder and the most significant digit output of the final full adder, the output of the first full adder being the least significant digit of the total and the outputs of successive full adders being the successively more significant digits of the total.

4. Apparatus according to claim 3 wherein the first and second counting means each comprise a plurality of full adders.

5. Apparatus according to claim 4 wherein the full adders comprising each counting means are arranged in a plurality of series, the full adders of the first series counting the occurrences in two to three element subsets of the portion, the full adders of successive series combining the totals of the previous series of full adders.

Patent Citations

Cited Patent | Filing date | Publication date | Applicant | Title |
---|---|---|---|---|

US3466433 * | 14 Dec 1965 | 9 Sep 1969 | Ibm | Optical parallel adder |

US3535502 * | 15 Nov 1967 | 20 Oct 1970 | Ibm | Multiple input binary adder |

US3603776 * | 15 Jan 1969 | 7 Sep 1971 | Ibm | Binary batch adder utilizing threshold counters |

Referenced by

Citing Patent | Filing date | Publication date | Applicant | Title |
---|---|---|---|---|

US4336600 * | 10 Apr 1980 | 22 Jun 1982 | Thomson-Csf | Binary word processing method using a high-speed sequential adder |

US4399517 * | 19 Mar 1981 | 16 Aug 1983 | Texas Instruments Incorporated | Multiple-input binary adder |

US4488253 * | 30 Apr 1982 | 11 Dec 1984 | Itt Industries, Inc. | Parallel counter and application to binary adders |

US4713786 * | 15 Feb 1985 | 15 Dec 1987 | Harris Corporation | Digital hardware selection filter |

US5148388 * | 17 May 1991 | 15 Sep 1992 | Advanced Micro Devices, Inc. | 7 to 3 counter circuit |

US5539683 * | 24 Jun 1994 | 23 Jul 1996 | Fujitsu Limited | Method and device for processing, and detecting a state of, binary data |

US5541865 * | 6 Jul 1995 | 30 Jul 1996 | Intel Corporation | Method and apparatus for performing a population count operation |

US5619437 * | 27 Sep 1995 | 8 Apr 1997 | Ando Electric Co., Ltd. | Parallel data counter circuit |

US5642306 * | 15 May 1996 | 24 Jun 1997 | Intel Corporation | Method and apparatus for a single instruction multiple data early-out zero-skip multiplier |

US5666298 * | 22 Aug 1996 | 9 Sep 1997 | Intel Corporation | Method for performing shift operations on packed data |

US5675526 * | 26 Nov 1996 | 7 Oct 1997 | Intel Corporation | Processor performing packed data multiplication |

US5677862 * | 2 Apr 1996 | 14 Oct 1997 | Intel Corporation | Method for multiplying packed data |

US5701508 * | 19 Dec 1995 | 23 Dec 1997 | Intel Corporation | Executing different instructions that cause different data type operations to be performed on single logical register file |

US5721892 * | 6 Nov 1995 | 24 Feb 1998 | Intel Corporation | Method and apparatus for performing multiply-subtract operations on packed data |

US5740392 * | 27 Dec 1995 | 14 Apr 1998 | Intel Corporation | Method and apparatus for fast decoding of 00H and OFH mapped instructions |

US5742529 * | 21 Dec 1995 | 21 Apr 1998 | Intel Corporation | Method and an apparatus for providing the absolute difference of unsigned values |

US5752001 * | 1 Jun 1995 | 12 May 1998 | Intel Corporation | Method and apparatus employing Viterbi scoring using SIMD instructions for data recognition |

US5757432 * | 18 Dec 1995 | 26 May 1998 | Intel Corporation | Manipulating video and audio signals using a processor which supports SIMD instructions |

US5764943 * | 28 Dec 1995 | 9 Jun 1998 | Intel Corporation | Data path circuitry for processor having multiple instruction pipelines |

US5787026 * | 20 Dec 1995 | 28 Jul 1998 | Intel Corporation | Method and apparatus for providing memory access in a processor pipeline |

US5793661 * | 26 Dec 1995 | 11 Aug 1998 | Intel Corporation | Method and apparatus for performing multiply and accumulate operations on packed data |

US5802336 * | 27 Jan 1997 | 1 Sep 1998 | Intel Corporation | Microprocessor capable of unpacking packed data |

US5815421 * | 18 Dec 1995 | 29 Sep 1998 | Intel Corporation | Method for transposing a two-dimensional array |

US5818739 * | 17 Apr 1997 | 6 Oct 1998 | Intel Corporation | Processor for performing shift operations on packed data |

US5819101 * | 21 Jul 1997 | 6 Oct 1998 | Intel Corporation | Method for packing a plurality of packed data elements in response to a pack instruction |

US5822232 * | 1 Mar 1996 | 13 Oct 1998 | Intel Corporation | Method for performing box filter |

US5822459 * | 28 Sep 1995 | 13 Oct 1998 | Intel Corporation | Method for processing wavelet bands |

US5831885 * | 4 Mar 1996 | 3 Nov 1998 | Intel Corporation | Computer implemented method for performing division emulation |

US5835392 * | 28 Dec 1995 | 10 Nov 1998 | Intel Corporation | Method for performing complex fast fourier transforms (FFT's) |

US5835748 * | 19 Dec 1995 | 10 Nov 1998 | Intel Corporation | Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file |

US5835782 * | 4 Mar 1996 | 10 Nov 1998 | Intel Corporation | Packed/add and packed subtract operations |

US5852726 * | 19 Dec 1995 | 22 Dec 1998 | Intel Corporation | Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner |

US5857096 * | 19 Dec 1995 | 5 Jan 1999 | Intel Corporation | Microarchitecture for implementing an instruction to clear the tags of a stack reference register file |

US5859997 * | 20 Aug 1996 | 12 Jan 1999 | Intel Corporation | Method for performing multiply-substrate operations on packed data |

US5862067 * | 29 Dec 1995 | 19 Jan 1999 | Intel Corporation | Method and apparatus for providing high numerical accuracy with packed multiply-add or multiply-subtract operations |

US5880979 * | 21 Dec 1995 | 9 Mar 1999 | Intel Corporation | System for providing the absolute difference of unsigned values |

US5881279 * | 25 Nov 1996 | 9 Mar 1999 | Intel Corporation | Method and apparatus for handling invalid opcode faults via execution of an event-signaling micro-operation |

US5898601 * | 17 Dec 1996 | 27 Apr 1999 | Intel Corporation | Computer implemented method for compressing 24 bit pixels to 16 bit pixels |

US5907842 * | 20 Dec 1995 | 25 May 1999 | Intel Corporation | Method of sorting numbers to obtain maxima/minima values with ordering |

US5935240 * | 15 Dec 1995 | 10 Aug 1999 | Intel Corporation | Computer implemented method for transferring packed data between register files and memory |

US5936872 * | 20 Dec 1995 | 10 Aug 1999 | Intel Corporation | Method and apparatus for storing complex numbers to allow for efficient complex multiplication operations and performing such complex multiplication operations |

US5940859 * | 19 Dec 1995 | 17 Aug 1999 | Intel Corporation | Emptying packed data state during execution of packed data instructions |

US5959636 * | 23 Feb 1996 | 28 Sep 1999 | Intel Corporation | Method and apparatus for performing saturation instructions using saturation limit values |

US5983253 * | 20 Dec 1995 | 9 Nov 1999 | Intel Corporation | Computer system for performing complex digital filters |

US5983256 * | 29 Oct 1997 | 9 Nov 1999 | Intel Corporation | Apparatus for performing multiply-add operations on packed data |

US5983257 * | 26 Dec 1995 | 9 Nov 1999 | Intel Corporation | System for signal processing using multiply-add operations |

US5984515 * | 21 Aug 1997 | 16 Nov 1999 | Intel Corporation | Computer implemented method for providing a two dimensional rotation of packed data |

US6009191 * | 15 Feb 1996 | 28 Dec 1999 | Intel Corporation | Computer implemented method for compressing 48-bit pixels to 16-bit pixels |

US6014684 * | 24 Mar 1997 | 11 Jan 2000 | Intel Corporation | Method and apparatus for performing N bit by 2*N-1 bit signed multiplication |

US6018351 * | 30 Oct 1997 | 25 Jan 2000 | Intel Corporation | Computer system performing a two-dimensional rotation of packed data representing multimedia information |

US6035316 * | 23 Feb 1996 | 7 Mar 2000 | Intel Corporation | Apparatus for performing multiply-add operations on packed data |

US6036350 * | 20 May 1997 | 14 Mar 2000 | Intel Corporation | Method of sorting signed numbers and solving absolute differences using packed instructions |

US6049864 * | 20 Aug 1996 | 11 Apr 2000 | Intel Corporation | Method for scheduling a flag generating instruction and a subsequent instruction by executing the flag generating instruction in a microprocessor |

US6058408 * | 20 Dec 1995 | 2 May 2000 | Intel Corporation | Method and apparatus for multiplying and accumulating complex numbers in a digital filter |

US6067034 * | 7 Apr 1998 | 23 May 2000 | Vocal Technologies Ltd. | Maximal bit packing method |

US6070237 * | 4 Mar 1996 | 30 May 2000 | Intel Corporation | Method for performing population counts on packed data types |

US6081824 * | 5 Mar 1998 | 27 Jun 2000 | Intel Corporation | Method and apparatus for fast unsigned integral division |

US6092184 * | 28 Dec 1995 | 18 Jul 2000 | Intel Corporation | Parallel processing of pipelined instructions having register dependencies |

US6128614 * | 8 Feb 1999 | 3 Oct 2000 | Intel Corporation | Method of sorting numbers to obtain maxima/minima values with ordering |

US6170997 | 22 Jul 1997 | 9 Jan 2001 | Intel Corporation | Method for executing instructions that operate on different data types stored in the same single logical register file |

US6237016 | 31 Jul 1997 | 22 May 2001 | Intel Corporation | Method and apparatus for multiplying and accumulating data samples and complex coefficients |

US6266686 | 4 Mar 1999 | 24 Jul 2001 | Intel Corporation | Emptying packed data state during execution of packed data instructions |

US6275834 | 4 Mar 1996 | 14 Aug 2001 | Intel Corporation | Apparatus for performing packed shift operations |

US6370559 | 13 Jul 1999 | 9 Apr 2002 | Intel Corportion | Method and apparatus for performing N bit by 2*N−1 bit signed multiplications |

US6385634 | 31 Aug 1995 | 7 May 2002 | Intel Corporation | Method for performing multiply-add operations on packed data |

US6418529 | 31 Mar 1998 | 9 Jul 2002 | Intel Corporation | Apparatus and method for performing intra-add operation |

US6430251 * | 24 Oct 2000 | 6 Aug 2002 | Sun Microsystems, Inc. | 4-Bit population count circuit |

US6470370 | 16 Jan 2001 | 22 Oct 2002 | Intel Corporation | Method and apparatus for multiplying and accumulating complex numbers in a digital filter |

US6516406 | 8 Sep 2000 | 4 Feb 2003 | Intel Corporation | Processor executing unpack instruction to interleave data elements from two packed data |

US6631389 | 22 Dec 2000 | 7 Oct 2003 | Intel Corporation | Apparatus for performing packed shift operations |

US6738793 | 14 Jan 2001 | 18 May 2004 | Intel Corporation | Processor capable of executing packed shift operations |

US6751725 | 16 Feb 2001 | 15 Jun 2004 | Intel Corporation | Methods and apparatuses to clear state for operation of a stack |

US6792523 | 27 Jul 1999 | 14 Sep 2004 | Intel Corporation | Processor with instructions that operate on different data types stored in the same single logical register file |

US6823353 | 2 Aug 2002 | 23 Nov 2004 | Intel Corporation | Method and apparatus for multiplying and accumulating complex numbers in a digital filter |

US6901420 | 18 Jul 2003 | 31 May 2005 | Intel Corporation | Method and apparatus for performing packed shift operations |

US6904114 * | 25 Apr 2003 | 7 Jun 2005 | J. Barry Shackleford | Ones counter employing two dimensional cellular array |

US6909767 | 14 Jan 2004 | 21 Jun 2005 | Arithmatica Limited | Logic circuit |

US6961845 | 9 Jul 2002 | 1 Nov 2005 | Intel Corporation | System to perform horizontal additions |

US7047383 | 11 Jul 2002 | 16 May 2006 | Intel Corporation | Byte swap operation for a 64 bit operand |

US7117232 | 27 May 2005 | 3 Oct 2006 | Intel Corporation | Method and apparatus for providing packed shift operations in a processor |

US7149882 | 11 May 2004 | 12 Dec 2006 | Intel Corporation | Processor with instructions that operate on different data types stored in the same single logical register file |

US7155601 | 14 Feb 2001 | 26 Dec 2006 | Intel Corporation | Multi-element operand sub-portion shuffle instruction execution |

US7260595 | 14 Nov 2003 | 21 Aug 2007 | Arithmatica Limited | Logic circuit and method for carry and sum generation and method of designing such a logic circuit |

US7373490 | 19 Mar 2004 | 13 May 2008 | Intel Corporation | Emptying packed data state during execution of packed data instructions |

US7392275 | 30 Jun 2003 | 24 Jun 2008 | Intel Corporation | Method and apparatus for performing efficient transformations with horizontal addition and subtraction |

US7395298 | 30 Jun 2003 | 1 Jul 2008 | Intel Corporation | Method and apparatus for performing multiply-add operations on packed data |

US7395302 | 30 Jun 2003 | 1 Jul 2008 | Intel Corporation | Method and apparatus for performing horizontal addition and subtraction |

US7424505 | 19 Nov 2001 | 9 Sep 2008 | Intel Corporation | Method and apparatus for performing multiply-add operations on packed data |

US7430578 | 30 Jun 2003 | 30 Sep 2008 | Intel Corporation | Method and apparatus for performing multiply-add operations on packed byte data |

US7451169 | 15 Jun 2006 | 11 Nov 2008 | Intel Corporation | Method and apparatus for providing packed shift operations in a processor |

US7461109 | 6 Jun 2007 | 2 Dec 2008 | Intel Corporation | Method and apparatus for providing packed shift operations in a processor |

US7480686 | 14 May 2004 | 20 Jan 2009 | Intel Corporation | Method and apparatus for executing packed shift operations |

US7509367 | 4 Jun 2004 | 24 Mar 2009 | Intel Corporation | Method and apparatus for performing multiply-add operations on packed data |

US7624138 | 30 Dec 2003 | 24 Nov 2009 | Intel Corporation | Method and apparatus for efficient integer transform |

US7631025 | 30 Jun 2003 | 8 Dec 2009 | Intel Corporation | Method and apparatus for rearranging data between multiple registers |

US7685212 | 25 Oct 2002 | 23 Mar 2010 | Intel Corporation | Fast full search motion estimation with SIMD merge instruction |

US7725521 | 10 Oct 2003 | 25 May 2010 | Intel Corporation | Method and apparatus for computing matrix transformations |

US7739319 | 1 Jul 2003 | 15 Jun 2010 | Intel Corporation | Method and apparatus for parallel table lookup using SIMD instructions |

US7818356 | 19 Oct 2010 | Intel Corporation | Bitstream buffer manipulation with a SIMD merge instruction | |

US7966482 | 21 Jun 2011 | Intel Corporation | Interleaving saturated lower half of data elements from two source registers of packed data | |

US8078836 | 13 Dec 2011 | Intel Corporation | Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits | |

US8185571 | 23 Mar 2009 | 22 May 2012 | Intel Corporation | Processor for performing multiply-add operations on packed data |

US8190867 | 29 May 2012 | Intel Corporation | Packing two packed signed data in registers with saturation | |

US8214626 | 3 Jul 2012 | Intel Corporation | Method and apparatus for shuffling data | |

US8225075 | 8 Oct 2010 | 17 Jul 2012 | Intel Corporation | Method and apparatus for shuffling data |

US8346838 | 1 Jan 2013 | Intel Corporation | Method and apparatus for efficient integer transform | |

US8396915 | 12 Mar 2013 | Intel Corporation | Processor for performing multiply-add operations on packed data | |

US8495123 | 1 Oct 2012 | 23 Jul 2013 | Intel Corporation | Processor for performing multiply-add operations on packed data |

US8495346 | 11 Apr 2012 | 23 Jul 2013 | Intel Corporation | Processor executing pack and unpack instructions |

US8510355 | 19 Oct 2010 | 13 Aug 2013 | Intel Corporation | Bitstream buffer manipulation with a SIMD merge instruction |

US8521994 | 22 Dec 2010 | 27 Aug 2013 | Intel Corporation | Interleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation |

US8560586 * | 29 Mar 2010 | 15 Oct 2013 | Meltin Bell | Linear bit counting implementations |

US8601246 | 27 Jun 2002 | 3 Dec 2013 | Intel Corporation | Execution of instruction with element size control bit to interleavingly store half packed data elements of source registers in same size destination register |

US8626814 | 1 Jul 2011 | 7 Jan 2014 | Intel Corporation | Method and apparatus for performing multiply-add operations on packed data |

US8639914 | 29 Dec 2012 | 28 Jan 2014 | Intel Corporation | Packing signed word elements from two source registers to saturated signed byte elements in destination register |

US8688959 | 10 Sep 2012 | 1 Apr 2014 | Intel Corporation | Method and apparatus for shuffling data |

US8725787 | 26 Apr 2012 | 13 May 2014 | Intel Corporation | Processor for performing multiply-add operations on packed data |

US8745119 | 13 Mar 2013 | 3 Jun 2014 | Intel Corporation | Processor for performing multiply-add operations on packed data |

US8745358 | 4 Sep 2012 | 3 Jun 2014 | Intel Corporation | Processor to execute shift right merge instructions |

US8782377 | 22 May 2012 | 15 Jul 2014 | Intel Corporation | Processor to execute shift right merge instructions |

US8793299 | 13 Mar 2013 | 29 Jul 2014 | Intel Corporation | Processor for performing multiply-add operations on packed data |

US8793475 | 29 Dec 2012 | 29 Jul 2014 | Intel Corporation | Method and apparatus for unpacking and moving packed data |

US8838946 | 29 Dec 2012 | 16 Sep 2014 | Intel Corporation | Packing lower half bits of signed data elements in two source registers in a destination register with saturation |

US8914613 | 26 Aug 2011 | 16 Dec 2014 | Intel Corporation | Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits |

US9015453 | 29 Dec 2012 | 21 Apr 2015 | Intel Corporation | Packing odd bytes from two source registers of packed data |

US9116687 | 29 Dec 2012 | 25 Aug 2015 | Intel Corporation | Packing in destination register half of each element with saturation from two source packed data registers |

US9141387 | 29 Dec 2012 | 22 Sep 2015 | Intel Corporation | Processor executing unpack and pack instructions specifying two source packed data operands and saturation |

US9152420 | 29 Jan 2013 | 6 Oct 2015 | Intel Corporation | Bitstream buffer manipulation with a SIMD merge instruction |

US9170814 | 5 Nov 2012 | 27 Oct 2015 | Intel Corporation | Bitstream buffer manipulation with a SIMD merge instruction |

US9170815 | 29 Jan 2013 | 27 Oct 2015 | Intel Corporation | Bitstream buffer manipulation with a SIMD merge instruction |

US9182983 | 29 Dec 2012 | 10 Nov 2015 | Intel Corporation | Executing unpack instruction and pack instruction with saturation on packed data elements from two source operand registers |

US9182985 | 5 Nov 2012 | 10 Nov 2015 | Intel Corporation | Bitstream buffer manipulation with a SIMD merge instruction |

US9182987 | 29 Jan 2013 | 10 Nov 2015 | Intel Corporation | Bitstream buffer manipulation with a SIMD merge instruction |

US9182988 | 7 Mar 2013 | 10 Nov 2015 | Intel Corporation | Bitstream buffer manipulation with a SIMD merge instruction |

US9189237 | 27 Dec 2012 | 17 Nov 2015 | Intel Corporation | Bitstream buffer manipulation with a SIMD merge instruction |

US9189238 | 29 Jan 2013 | 17 Nov 2015 | Intel Corporation | Bitstream buffer manipulation with a SIMD merge instruction |

US9218184 | 15 Mar 2013 | 22 Dec 2015 | Intel Corporation | Processor to execute shift right merge instructions |

US9223572 | 29 Dec 2012 | 29 Dec 2015 | Intel Corporation | Interleaving half of packed data elements of size specified in instruction and stored in two source registers |

US9229718 | 30 Dec 2014 | 5 Jan 2016 | Intel Corporation | Method and apparatus for shuffling data |

US9229719 | 30 Dec 2014 | 5 Jan 2016 | Intel Corporation | Method and apparatus for shuffling data |

US9361100 | 29 Dec 2012 | 7 Jun 2016 | Intel Corporation | Packing saturated lower 8-bit elements from two source registers of packed 16-bit elements |

US9389858 | 29 Dec 2012 | 12 Jul 2016 | Intel Corporation | Orderly storing of corresponding packed bytes from first and second source registers in result register |

US20020059355 * | 19 Nov 2001 | 16 May 2002 | Intel Corporation | Method and apparatus for performing multiply-add operations on packed data |

US20020112147 * | 14 Feb 2001 | 15 Aug 2002 | Srinivas Chennupaty | Shuffle instructions |

US20030050941 * | 9 Jul 2002 | 13 Mar 2003 | Patrice Roussel | Apparatus and method for performing intra-add operation |

US20030115441 * | 27 Jun 2002 | 19 Jun 2003 | Alexander Peleg | Method and apparatus for packing data |

US20030123748 * | 25 Oct 2002 | 3 Jul 2003 | Intel Corporation | Fast full search motion estimation with SIMD merge instruction |

US20030131219 * | 27 Jun 2002 | 10 Jul 2003 | Alexander Peleg | Method and apparatus for unpacking packed data |

US20040010676 * | 11 Jul 2002 | 15 Jan 2004 | Maciukenas Thomas B. | Byte swap operation for a 64 bit operand |

US20040024800 * | 18 Jul 2003 | 5 Feb 2004 | Lin Derrick Chu | Method and apparatus for performing packed shift operations |

US20040054878 * | 30 Jun 2003 | 18 Mar 2004 | Debes Eric L. | Method and apparatus for rearranging data between multiple registers |

US20040054879 * | 1 Jul 2003 | 18 Mar 2004 | Macy William W. | Method and apparatus for parallel table lookup using SIMD instructions |

US20040059889 * | 30 Jun 2003 | 25 Mar 2004 | Macy William W. | Method and apparatus for performing efficient transformations with horizontal addition and subtraction |

US20040117422 * | 30 Jun 2003 | 17 Jun 2004 | Eric Debes | Method and apparatus for performing multiply-add operations on packed data |

US20040133617 * | 10 Oct 2003 | 8 Jul 2004 | Yen-Kuang Chen | Method and apparatus for computing matrix transformations |

US20040153490 * | 14 Nov 2003 | 5 Aug 2004 | Sunil Talwar | Logic circuit and method for carry and sum generation and method of designing such a logic circuit |

US20040181649 * | 19 Mar 2004 | 16 Sep 2004 | David Bistry | Emptying packed data state during execution of packed data instructions |

US20040201411 * | 14 Jan 2004 | 14 Oct 2004 | White Benjamin Earle | Logic circuit |

US20040210741 * | 11 May 2004 | 21 Oct 2004 | Glew Andrew F. | Processor with instructions that operate on different data types stored in the same single logical register file |

US20040215681 * | 14 May 2004 | 28 Oct 2004 | Lin Derrick Chu | Method and apparatus for executing packed shift operations |

US20040223580 * | 25 Apr 2003 | 11 Nov 2004 | J. Barry Shackleford | Ones counter employing two dimensional cellular array |

US20050038977 * | 13 Sep 2004 | 17 Feb 2005 | Glew Andrew F. | |

US20050108312 * | 1 Jul 2003 | 19 May 2005 | Yen-Kuang Chen | Bitstream buffer manipulation with a SIMD merge instruction |

US20050219897 * | 27 May 2005 | 6 Oct 2005 | Lin Derrick C | Method and apparatus for providing packed shift operations in a processor |

US20060235914 * | 15 Jun 2006 | 19 Oct 2006 | Lin Derrick C | Method and apparatus for providing packed shift operations in a processor |

US20060236076 * | 12 Jun 2006 | 19 Oct 2006 | Alexander Peleg | Method and apparatus for packing data |

US20070239810 * | 6 Jun 2007 | 11 Oct 2007 | Lin Derrick C | Method and apparatus for providing packed shift operations in a processor |

US20090265409 * | 23 Mar 2009 | 22 Oct 2009 | Peleg Alexander D | Processor for performing multiply-add operations on packed data |

US20110029759 * | 8 Oct 2010 | 3 Feb 2011 | Macy Jr William W | Method and apparatus for shuffling data |

US20110035426 * | 10 Feb 2011 | Yen-Kuang Chen | Bitstream Buffer Manipulation with a SIMD Merge Instruction | |

US20110093682 * | 22 Dec 2010 | 21 Apr 2011 | Alexander Peleg | Method and apparatus for packing data |

US20110219214 * | 8 Sep 2011 | Alexander Peleg | Microprocessor having novel operations | |

US20110238717 * | 29 Sep 2011 | Meltin Bell | Linear Bit Counting Implementations | |

USRE45458 | 21 Mar 2002 | 7 Apr 2015 | Intel Corporation | Dual function system and method for shuffling packed data elements |

EP0195284A2 * | 27 Feb 1986 | 24 Sep 1986 | Siemens Aktiengesellschaft | Device for counting the number of 1/0 bits contained in an n-bits binary word |

EP0388506A2 * | 19 Jun 1989 | 26 Sep 1990 | Digital Equipment Corporation | Normalizer |

WO1996017289A1 * | 1 Dec 1995 | 6 Jun 1996 | Intel Corporation | A novel processor having shift operations |

WO2004064254A2 * | 14 Jan 2004 | 29 Jul 2004 | Arithmatica Limited | A logic circuit |

WO2004064254A3 * | 14 Jan 2004 | 10 Sep 2004 | Arithmatica Ltd | A logic circuit |

Classifications

U.S. Classification | 708/210 |

International Classification | G11C15/00, G11C15/04, G06F7/60 |

Cooperative Classification | G06F7/607, G11C15/04 |

European Classification | G06F7/60P, G11C15/04 |

Legal Events

Date | Code | Event | Description |
---|---|---|---|

22 Feb 1988 | AS | Assignment | Owner name: LORAL CORPORATION, 600 THIRD AVENUE, NEW YORK, NEW Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:GOODYEAR AEROSPACE CORPORATION;REEL/FRAME:004869/0167 Effective date: 19871218 Owner name: LORAL CORPORATION,NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GOODYEAR AEROSPACE CORPORATION;REEL/FRAME:004869/0167 |

Rotate