US3688278A

US3688278A - Data processing apparatus

Info

Publication number: US3688278A
Application number: US860849A
Authority: US
Inventors: Jacques Louis Sauvan; Jacques Berthelemy
Original assignee: Individual
Current assignee: Individual
Priority date: 1968-09-19
Filing date: 1969-09-19
Publication date: 1972-08-29
Anticipated expiration: 1989-08-29
Also published as: NL6914155A; DE1947384A1; IL33006A0; CA951824A; BE739022A; GB1284421A; IL33006A; FR1586705A; CH531217A

Abstract

Data processing apparatus arranged to perform a method for the search, simultaneously in several networks, for a set of optimum component trajectories respecting constraints of inter-dependence of these networks, these trajectories connecting in each network a starting point node and a target point node ; this method is carried out by performing a series of retrograde investigations from a final situation to an initial situation and thus determining step by step the desired set of optimum component trajectories ; the apparatus may include : centers for simulating each network, centers of association of nodes or links of different networks for simulating the inter-dependence constraints of the networks, posting members for target and starting points nodes, a center of coordination for coordinating the transmission of signals to a number of lines which connect said different centers with the aid of temporary memories.

Description

United States Patent Sauvan et al.

14s] Aug. 29, 1972 [54] DATA PROCESSING APPARATUS 3,411,140 11/1968 Halina et al. ..340/172.5 [72] Inventors; Jacques Louis Sam,ln 43 we 3,440,617 4/1969 Lest] ..340/172.5 Lacepede Paris; q Berthelfi 3,446,950 5/1969 Kmg et al. ..235/197 my, 8 rue de la Gare, 77 Thorigny, both of France Primary Examiner-Paul J. Henon Assistant Examiner-Ronald F. Chapuran Filed: p 19, 1969 Attorney-Flynn & Frishauf 211 App]. No.: 860,849

[ ABSTRACT 30 Foreign Application Priority Data Data processing apparatus arranged to perform a method for the search, s1multaneously 1n several net- Sept. 19, 1968 France ..166844 works, for a Set of optimum component trajectories respecting constraints of inter-dependence of these networks, the traje tories connecting in each net- I k a mi i d d a t i t d 53 Field of Search ..340/172.5, 146.3; 235/180, this method fg out by i j Series of 235/]97 retrograde investigations from a final situation to an initial situation and thus determining step by step the [56] Retenmes C'ted desired set of optimum component trajectories the UNITED STATES PATENTS apparatus may include centers for simulating each network, centers of associatlon of nodes or links of 3,038,660 6/ 1962 Honnell et al. ..235/1 80 diff t networks f Simulating the interdependence 3,191,150 6/1965 Andrews ..340/ 146.3 constraints of the networks, posting members for tap 3,242,466 3/ 1966 DllkS ..340/172.5 get and starting Points nodes, 3 oemer f Coordination 3,278,899 10/1966 Shelton et a1 ..340/ 146.3 for coordinating the transmission of signals to a flapper number of lines which connect said different centers may th th d ft 3,391,392 7/1968 Doyle ..340/172.5 e 0 emporary memoms 3,394,352 7/1968 Wernikoff et a1 ..340/ 172.5 27 Claims, 36 Drawing Figures 2 i" ACT /3 AUT .mRr i FIN 18 as I 015 1m 1 l i i 1 1 l i MIT M7 at: RE? 82 1 "L?. C2! .J

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Claims

1. Apparatus for the extraction of information for use with data processing apparatus which includes matrices having bistable elements, and temporary memories; a coordination center (CC) controlling the bistable matrices and the temporary memories, said apparatus analyzing an external system defined by a plurality of parameters, each capable of taking a finite number of values and to undergo, starting from each said values, a finite number of variations, the data processing machine comprising I. a plurality of basic, functionally nOn-subdividable subassemblies including (a) as many connection centers (FIG. 3: CL; CLX, CLY . . . . ) as there are parameters to be memorized, each connection center (CL) comprising as many connection elements (FIG. 8: EL) as there are possible values for the parameter to be considered, each connection element (EL) comprising a first separate bistable memorization element (BO 1108); b. as many bi-dimensional recording center matrices (FIG. 3: CI; CIX, CIY . . . . ) as there are parameters, each recording center comprising recording elements (FIG. 9: EI) included in the recording center matrices, each recording element comprising a separate second bistable memorization element (B 1201), each state of said second bistable memorization element corresponding to one of the possible variations of one of the values of the parameter of the respective matrix; a first AND gate (1203), the output from the second bistable memorization element (B 1201) forming one input to said first AND gate (1203); c. at least one value-associative matrix (FIG. 3: CAS; CAS XY . . . . ) comprising as many association elements (FIG. 7: EAS) as the number of possible associations, and having third bistable memorization elements (FIG. 7: B 1004), capable of having two values, each one corresponding to a different parameter, and fourth and fifth bistable memorization elements (B1 1007; B2 1012), and a second AND gate (1011), said fourth and fifth bistable elements being connected to said second AND gate (1011); II. extraction apparatus, comprising a. a first group of four types of interconnecting lines, interconnecting the connecting elements (FIG. 8: EL) with respect to a parameter, to the recording elements (FIG. 9: EI) with respect to the same said parameter, said four types of lines including: 1. a first type of said lines (FIGS. 8 and then 9: INT OACI) interconnecting the output from a first OR GATE (1110) of a connecting element (EL) to the first input of said first AND gate (1203) of a row of recording elements (EI) associated with one of said values; 2. second types of lines (FIGS. 9 and then 8: AUT OACI) interconnecting the output of a second OR gate (1206) from a recording element (EI) to the first input of a third AND gate (1111) of a corresponding connecting element (EL), the output of which is connected to an input of a fourth AND gate (1113); 3. third types of lines (FIGS. 8 and then 9: INT EACI) interconnecting the output of a third OR gate (1103) of a connecting element (EL) and corresponding to a particular value of a parameter, to the second inputs of said first AND gates (1203) of the recording elements (EI) so that the variation of a value of the parameter corresponding to the columns in which each recording element (EI) is arranged defines the same extreme value for the array of recording elements (EI) connected to the same line of said third type (INT EACI) and said extreme value is that of said connecting element (EL), the input of said third OR gate (1103) being connected to the outputs of fifth and sixth AND gates (1102, 1104); 4. fourth types of lines (FIGS. 9 and then 8: AUT EACI) interconnecting the outputs of fourth OR gates (1208) of the recording elements (EI) to a first input of a seventh AND gate (1112) of a corresponding connecting element (EL); b. recording lines (SORT ACT) interconnecting eigth AND gates (1207) of the recording elements (FIG. 9: EI) such that each of said recording lines (FIG. 11: SORT ACT) corresponds, for the same column of a recording matrix, to the same variation controlling the actual value of the parameter; c. the extraction apparatus further including said valueassociative elements (FIGS. 3 and 7: EAS) and a second group of three types of interconnecting lines, interconnecting the connecting elements (FIG. 8: EL), each, with respect to a value of a paramEter to at least a row of value-associative elements (EAS) with respect to the same value of a parameter including; 1. fifth types of lines (FIG. 8, then 7: INT CAS; INT CAS X, INT CAS Y) interconnecting the outputs of a buffer OR gate (1113) of a connecting element (EL) to at least one of two inputs (INT CAS X, INT CAS Y, . . . . ) of ninth AND gates (FIG. 7: 1006) of a row of associative elements (EAS), a group of associative elements forming an association center (CAS), the center of association (CAS) formed by said group of elements being associated with a predetermined value with respect to said parameter, the outputs of said ninth AND gates (1006) being connected to one input of said fourth bistable elements (1007), and to the input of an inverter (I 1022); 2. at least two sixth types of lines (RET B1) for each center of association (CAS) associated with a predetermined value (CAS; RET B1X, RET B1Y . . . . ), having at least two fifth and sixth OR gates (1016, 1017), each associated with at least two rows of at least one center of association (CAS) associated with said predetermined value, for each parameter, each row of elements (FIG. 7: EAS) being connected to an input of the ninth AND gate (1106) of the connecting element (FIG. 8: EL) corresponding to the value of the parameter defined by said row; 3. at least two seventh types of lines (RET B2) for each center of association of the same predetermined value (FIG. 7: CAS; RET B2X, RET B2Y . . . . ) having at least two seventh and eighth OR gates (1019, 1020), each associated with at least two rows of at least one center of association (CAS) of said predetermined value, for each parameter, each row of elements (FIG. 7: EAS) being connected to an input of a tenth AND gate (1101) of the connecting element (FIG. 8: EL) corresponding to the value of the parameter defined by said row; d. as many display lines (FIG. 8: MEM B2) of the values for the group of parameters corresponding to the final state of the system to be controlled, as are possible values for each parameter, each said lines being connected to an input of the buffer OR gate (1113) of a connecting element (EL) which corresponds to the same value of the same parameter; e. as many display lines (FIG. 8: MEM B0) of the values for the group of parameters corresponding to the initial state of the system to be controlled as are possible values for each parameter, each said line (MEM B0) being connected to an input of a ninth OR gate (1118) of the connecting element (EL) which corresponds to the same value of the same parameter; f. the coordination center (CC) executing, step by step, the different phases of search, comprising: 1. lines gamma connected to a second input of fourth AND gates (1109) and said sixth AND gates (1104) of the connecting elements (FIG. 8: EL); 2. start lines (A) connected to the inputs of tenth OR gates (1120) of all the connecting elements (FIG. 8: EL); 3. control lines (RAZ B1) connected to all eleventh AND gates (1023) of the value association elements (FIG. 7: EAS); 4. an eighth line (FIG. 11b: AUT SORT ACT) connected to all the first inputs of twelfth AND gates (1408), the other second inputs of which being connected to all of said recording lines (FIG. 9: SORT ACT) of the same column of recording elements (EI) in a recording matrix (CI); 5. ninth lines (BT2) connected to: one input of said fifth AND gates (1102), said third AND gates (1111) and a pair of thirteenth AND gates (1112, 1119) of all the connecting elements (FIG. 8: EL), and one input of fourteenth AND

2. second types of lines (FIGS. 9 and then 8: AUT OACI) interconnecting the output of a second OR gate (1206) from a recording element (EI) to the first input of a third AND gate (1111) of a corresponding connecting element (EL), the output of which is connected to an input of a fourth AND gate (1113);

2. at least two sixth types of lines (RET B1) for each center of association (CAS) associated with a predetermined value (CAS; RET B1X, RET B1Y . . . . ), having at least two fifth and sixth OR gates (1016, 1017), each associated with at least two rows of at least one center of association (CAS) associated with said predetermined value, for each parameter, each row of elements (FIG. 7: EAS) being connected to an input of the ninth AND gate (1106) of the connecting element (FIG. 8: EL) corresponding to the value of the parameter defined by said row;

2. AUT OACI lines (FIGS. 9 and then 8) interconnecting the output from a recording element (EI) to the first input of a 1111 AND gate of a corresponding connecting element (EL), the output of which is connected to a 1113 control gate;

2. start lines (A) connected to the inputs of tenth OR gates (1120) of all the connecting elements (FIG. 8: EL);

2. Apparatus according to claim 1, wherein: I. said machine comprises a fourth sub-assembly, said fourth sub-assembly including at least one matrix (FIG. 3: CAA; CAA XY) formed of elements of variable association of values (FIG. 10: EAA), said elements of variable association of values including six bistable memorization elements (FIG. 10: B 1301), each corresponding to an association of at least two variations of value, each associated with a different parameter; and wherein the extraction apparatus further comprises II. a thirteenth type line (INT CAA) interconnecting the output of a twelfth OR gate (FIG. 9: 1204) with all the recording elements (EI) of a column to one of the inputs of a seventeenth AND gate (1304) of all the elements of variable association of value (FIG. 10: EAA) of a row, of at least one of the matrices (CAA; lines INT CAA X, INT CAA Y, FIG. 10); and fourteenth type lines (FIG. 10: AUT CAA; AUT CAAX, AUT CAAY), connected to the outputs of thirteenth and fourteenth OR gates (1305, 1306), all said fourteenth type lines (AUT CAA) of one row of a center of association (CAA) being connected to an input of an eighteenth AND gate (FIG. 9) of all the recording elements (EI) of a column of the recording matrix (CI), the other input of said eighteenth AND gates (1205) being interconnected to the output of said first AND gate (1203), the output of said first AND gate being connected to one input of said second OR gate (1206).

2. start lines (A) connected to all the connecting elements (FIG. 8: EL);

2. at least two RET B1 lines for each center of association (CAS) controlling and associated with a predetermined value (RET B1X, RET B1Y . . . ), each line being associated with at least two rows of value-associative elements (EAS) of at least one center of association (CAS) associated with said predetermined value, for each parameter, each row of elements (FIG. 7: EAS) being connected to an input of the 1106 AND gate of the connecting element (FIG. 8: EL) corresponding to the value of the parameter defined by said row;

3. at least two RET B2 lines for each center of association (CAS) of the same predetermined value (FIG. 7: RET B2XX, RET B2YY . . . . ), each line being associated with at least two rows of value-associative elements (EAS) of at least one center of association (CAS) of said predetermined value, for each parameter, each row of elements (FIG. 7: EAS) being connected to an input of a 1101 AND gate of the connecting element (FIG. 8: EL) corresponding to the value of the parameter defined by said row; d. as many MEM B2 display lines (FIG. 8) of the values for the group of parameters corresponding to the final state of the system to be controlled, as are possible values for each parameter, each said MEM B2 lines being connected to a connecting element (EL) wich corresponds to the same value of the same parameter; e. as many MEM B0 control lines (FIG. 8) of the values for the group of parameters corresponding to the initial state of the system to be controlled as are possible values for each parameter, each said MEM B0 lines being connected to a connecting element (EL) which corresponds to the same value of the same parameter; f. the coordination center (CC) executing, step by step, the different phases of analysis and comprising:

3. control lines (RAZ B1, RAZ B2, FIN Beta CAS), connected to the value association elements (EAS); and

3. Apparatus according to claim 1, wherein each of the elements of association (FIG. 7: EAS) comprises a fifteenth OR gate (1008) connected to the output of said fifth bistable memory elements (B2 1012) of at least some of the elements of association (EAS) accessible during a single variation of value of the parameters associated with said element; the output from said fifteenth OR gate (1008) being connected across said fourteenth AND gate (1009) to one input of the ninth AND gate (1006).

3. control lines (RAZ B1) connected to all eleventh AND gates (1023) of the value association elements (FIG. 7: EAS);

3. INT EACI lines (FIGS. 8 and then 9) interconnecting the output of a connecting element (EL) representative of and corresponding to a particular value of a parameter, to second inputs of said 1203 AND gates of the recording elements (EI) so that the variation of a value of the parameter corresponding to the columns in which each recording element (EI) is arranged defines the same extreme value for the array of recording elements (EI) connected to the INT EACI line and said extreme value is that of said connecting element (EL);

3. at least two seventh types of lines (RET B2) for each center of association of the same predetermined value (FIG. 7: CAS; RET B2X, RET B2Y . . . . ) having at least two seventh and eighth OR gates (1019, 1020), each associated with at least two rows of at least one center of association (CAS) of said predetermined value, for each parameter, each row of elements (FIG. 7: EAS) being connected to an input of a tenth AND gate (1101) of the connecting element (FIG. 8: EL) corresponding to the value of the parameter defined by said row; d. as many display lines (FIG. 8: MEM B2) of the values for the group of parameters corresponding to the final state of the system to be controlled, as are possible values for each parameter, each said lines being connected to an input of the buffer OR gate (1113) of a connecting element (EL) which corresponds to the same value of the same parameter; e. as many display lines (FIG. 8: MEM B0) of the values for the group of parameters corresponding to the initial state of the system to be controlled as are possible values for each parameter, each said line (MEM B0) being connected to an input of a ninth OR gate (1118) of the connecting element (EL) which corresponds to the same value of the same parameter; f. the coordination center (CC) executing, step by step, the different phases of search, comprising:

3. third types of lines (FIGS. 8 and then 9: INT EACI) interconnecting the output of a third OR gate (1103) of a connecting element (EL) and corresponding to a particular value of a parameter, to the second inputs of said first AND gates (1203) of the recording elements (EI) so that the variation of a value of the parameter corresponding to the columns in which each recording element (EI) is arranged defines the same extreme value for the array of recording elements (EI) connected to the same line of said third type (INT EACI) and said extreme value is that of said connecting element (EL), the input of said third OR gate (1103) being connected to the outputs of fifth and sixth AND gates (1102, 1104);

4. fourth types of lines (FIGS. 9 and then 8: AUT EACI) interconnecting the outputs of fourth OR gates (1208) of the recording elements (EI) to a first input of a seventh AND gate (1112) of a corresponding connecting element (EL); b. recording lines (SORT ACT) interconnecting eigth AND gates (1207) of the recording elements (FIG. 9: EI) such that each of said recording lines (FIG. 11: SORT ACT) corresponds, for the same column of a recording matrix, to the same variation controlling the actual value of the parameter; c. the extraction apparatus further including said value-associative elements (FIGS. 3 and 7: EAS) and a second group of three types of interconnecting lines, interconnecting the connecting elements (FIG. 8: EL), each, with respect to a value of a paramEter to at least a row of value-associative elements (EAS) with respect to the same value of a parameter including;

4. AUT EACI lines (FIGS. 9 and then 8) interconnecting the outputs of the recording elements (EI) to a first input of a 1112 control gate of a corresponding connecting element (EL); b. SORT ACT recording lines interconnecting the recording elements (FIG. 9: EI), each of said SORT ACT recording lines (FIG. 11) corresponding, for the same column of a recording matrix, to the same variation controlling the actual value of the parameter; c. a second group of three types of interconnecting lines, interconnecting the connecting elements (FIG. 8: EL), each, with respect to a value of a parameter to at least a row of value-associative elements (FIGS. 3 and 7: EAS), of the value-associative matrix (CAS), with respect to the same value of a parameter including:

4. an eighth line (FIG. 11b: AUT SORT ACT) connected to all the first inputs of twelfth AND gates (1408), the other second inputs of which being connected to all of said recording lines (FIG. 9: SORT ACT) of the same column of recording elements (EI) in a recording matrix (CI);

4. Apparatus according to claim 1, wherein each of the sixth type lines (RET B1) with respect to the same parameter are connected to the inputs of ninteenth AND gates (1106), to form a line of the connecting elements (EL; FIG.8) of the parameter; and wherein the seventh type lines (RET B2) with respect to the same parameter form the inputs to the tenth AND gates (1101) of a line of the connecting elements (EL) of said parameter; the output from said tenth AND gates (1101) being connected to the other input of sixteenth OR gates (1102) and to the inputs of said sixth AND gates (1104); and wherein the fourteenth type lines (FIG. 10: AUT CAAX, AUT CAAY) are provided, relative to the same parameter, and forming one of the inputs to a twentieth AND gate (FIG. 11: 1401).

4. AUT SORT ACT control lines (FIG. 11b) connected to control energization by said SORT ACT recording lines (FIG. 9), of the same column of recording elements (EI) in a recording matrix (CI);

5. INF BO lines (FIG. 8), and a comparator (FIG. 11a: SAFI) connected to sense a predetermined condition and, upon such sensing, interrupting the extraction step; and

5. Apparatus according to claim 1, wherein the tenth OR gate (1120) of each connecting element (FIG. 8: EL) is excited by the signal from the start line (A) at a clock time ( Beta T2); and the thirteenth AND gate (1119) is validated by the ninth line (BT2), connected to one of the inputs of said thirteenth AND gate (1119), the output being connected to one of the inputs of the first OR gate (1110), energizing the first type line (INT OACI).

5. ninth lines (BT2) connected to: one input of said fifth AND gates (1102), said third AND gates (1111) and a pair of thirteenth AND gates (1112, 1119) of all the connecting elements (FIG. 8: EL), and one input of fourteenth AND gates (1009) of all the association of value elements (FIG. 7: EAS);

6. tenth lines (BT1) connected to one input of all the second AND gates (1011) of all the association of value elements (FIG. 7: EAS);

6. Apparatus according to claim 1, wherein the start line (A) connects the start signal to a twentieth OR gate (FIG. 11b: 1403), the output from said twentieth OR gate (1403) being connected to validate a twenty-first AND gate (1402), the output from said twenty-first AND gate (1402) forming the connection to the line, or column of said thirteenth lines (INT CAA).

6. a clock means providing timing signals (FIG. 15) to said apparatus until said predetermined condition is sensed and the extraction steps interrupted.

7. Apparatus according to claim 1, wherein each of the elements of association (EAS) comprises one of said fourth bistable memorization elements (B1 1007), said bistable elements having a control and reset input, the reset input being connected to said control line (RAZ B1) over said eleventh AND gate (1023), the other input of said eleventh AND gate (1023) being connected to the output of an inverter (I 1022).

7. further control lines (RAZ B2) connected to one input of the fifth bistable memory element (B2 1012) of all the association of value elements (FIG. 7: EAS);

8. eleventh lines (FIG. 7: FIN Beta CAS) connected to the output of an eleventh OR gate (1021), one each being associated with a center of value association (FIG. 7: CAS) and connected, in turn, to the inputs of fifteenth AND gates (FIG. 11a: 1330);

8. Apparatus according to claim 1, wherein each element of association (FIG. 7: EAS) comprises a seventeenth OR gate (1010), the inputs of said seventeenth OR gate (1010) being connected to an output (1013) of said fifth bistable memorization element (B2 1012), the output of the fourteenth AND gate (1009) and a general control line (P), said general control line suppressing the constraint of a validation by the ninth AND gate (1016) or from the output of the fourteenth AND gate (1009) or from the output of the fifth bistable memorization element (B2 1012).

9. Apparatus according to claim 1, wherein each element of association (FIG. 7: EAS) of a column of each association of values matrix (FIG. 3: CAS) comprises a fifteenth line (BOX) forming an input line, said input line (BOX) being common to all elements in a column, and being connected to a twenty-second AND gate (1018) and a sixteenth input line (BOY) common to all the elements in a row being connected to a second input of said twenty-second AND gate (1018); the third input to said twenty-second AND gate being formed by the output from the fourth bistable memorization element (B1 1007), the output from said twenty-second AND gate (1018) forming one of the inputs to the eleventh OR gate (1021), the other inputs of said eleventh OR gate 1021 being formed by the outputs from all the twenty-second AND gates of the respective matrix.

9. twelfth lines (FIG. 8: INF B0), and a comparator (FIG. 11a SAFI) and a sixteenth AND gate (FIN EXT), the twelfth lines being connected to the input of the comparator, the output thereof being connected to said sixteenth AND gate (FIN EXT) and interrupting the extraction step; and

10. a clock means, said clock providing timing signals (FIG. 15), one of said timing signals providing a signal (FIN Beta ) to the output of said fifteenth AND gate (FIG. 11a: 1330) and then, providing further timing signals (FIG. 16), to be followed by said first timing signals (FIG.15) until the signal is derived from said sixteenth AND gate (FIG. 11a: FIN EXT), said signal from said sixteenth AND gate stopping the further generation of clock signals.

10. Apparatus according to claim 1, wherein fifteenth OR gates (1008) are provided, the inputs to said fifteenth OR gates (1008) being formed by the outputs of the fifth bistable memorization elements (FIG. 7: B1 1012) of the elements of association (EAS) adjacent the respective elements.

11. Apparatus according to claim 1, wherein the fourth AND gate (1109) has as a second input the output of the first bistable memorization element (BO 1108), the output from said fourth AND gate (1109) being connected to the second input of the first OR gate (1110).

12. Apparatus according to claim 1, wherein a reset line (RAZ B0) is provided, said reset line (FIG. 8: RAZ B0) being common to the apparatus and forming a second input to the first bistable memorization element (B0 1108).

13. Apparatus according to claim 4, wherein each connecting element (FIG. 8: EL) includes a twenty-third AND gate (1107), a first input of said twenty-third AND gate (1107) being connected to the output of the nineteenth AND gate (1106); and a seventeenth overall authorization line (AUT 1) is provided, forming a second input to said twenty-third AND gate (1107), the output from said twenty-third AND gate (1107) forming a seCond input to the ninth OR gate (1118).

14. Apparatus according to claim 2, wherein each recording element (FIG. 9: EI) includes the eighteenth AND gate (1205), the output of said eighteenth AND gate (1205) forming the inputs to the fourth OR gate (1208) and a seventeenth OR gate (1207).

15. Apparatus according to claim 14, wherein each recording element (FIG. 9: EI) includes said seventeenth OR gate (1207), an additional input thereof being connected to the recording line (SORT ACT) of the column of the matrix of recording elements in which the recording element (EI) is located.

16. Apparatus according to claim 1, wherein each recording element (FIG. 9: EI) has the second input of the fourth OR gate (1208) connected to the output of the fourth type lines (AUT EACI) of the recording elements.

17. Apparatus according to claim 1, wherein each recording element (FIG. 9) comprises an eighteenth line (GEN), to the group of recording elements of one matrix, said common line (GEN) forming an input to an eighteenth OR gate (1202), the output of which forms one of three inputs to the first AND gate (1203).

18. Apparatus according to claim 1, comprising elements of association of variation of values (FIG. 10: EAA), said elements comprising, each, an eighteenth OR gate (1303), having one input formed by the output of the sixth bistable memorization element (B 1301), and a second input formed by an eighteenth line (PROJ) common to all the elements of the matrix, the output from said twentieth OR gates forming a third input to a seventeenth AND gate (1304).

19. Apparatus according to claim 1, wherein, in each element of the variation of association of values (FIG. 10: EAA), a nineteenth reset line (RAZ CAA) is provided, common to the apparatus, said nineteenth reset line forming a second input to a sixth bistable memorization element (B 1301).

20. Apparatus according to claim 1, wherein each recording line (SORT ACT) has a twelfth AND gate (FIG. 11b: 1408) inserted therein which is energized by the eighth type line (FIG. 11a, then FIG. 11b; AUT SORT ACT), the recording lines (SORT ACT) of one recording matrix (CI) being all connected to a multiple input gate (FIG. 11a: PAM 2301), said multiple input gate (PAM 2301) energizing either a twentieth line (SAM) or, if more than one line is to be energized, the recording lines (SORT ACT) of each recording matrix, or a twenty-first line (O) if no single one of the recording lines (SORT ACT) is energized, the twentieth output lines (SAM) from all the gates (PAM 2301) providing to the coordination center (CC) the information from the twenty-first line (O) over a nineteenth OR gate (2401), the other inputs of which being connected to the ZERO outputs of all the multiple gates (PAM), the output from said multiple gates (PAM 2301) further delivering to the coordination center (CC) data of information > 1 over a twenty-first OR gate (2402), the other inputs of which being connected to the inputs > 1 of all the other multiple gates (PAM 2301), the output from said twentieth OR gate (2402) being connected to a twenty-fourth AND gate (2405), the other input of which is connected to a twenty-eighth AND gate (PACN) over an inverter (2406).

21. Apparatus according to claim 1, wherein an inter-parameter hierarchy circuit between the recording matrices is provided (FIG. 23), comprising: a seventh bistable memorization element (BAM 2304) for each recording matrix, connected to a twentieth line (SAM) of corresponding multiple gates (PAM 2301); an eighth bistable memorization element (BH 2309) to indicate that in inter-processing priority has been authorized in the relative, respective recording matrix (CI); and a classification circuit for the recording matrices, connected to the outputs of the seventh memorization elements (BAM 2304) and to thE inputs of the eighth memorization elements (BH 2309) to authorize energization of the specific eighth bistable memorization element (BH 2309) which corresponds to the first matrix, taken in the order of hierarchy between the matrices, and in which the specific seventh element (BAM 2304) contains data in its memory.

22. Apparatus according to claim 21, wherein the matrix classification circuit (FIG. 23) comprises a loop line, having connected thereto as many twenty-fifth AND gates (2305) as matrices are present to arrange in hierarchial order, all said twenty-fifth AND gates (2305) being permanently energized, except that particular one corresponding to the first matrix in the hierarchial arrangement, each of said twenty-fifth AND gates (2305) being additionally connected, over an inverter (I 2307) to the input of a twenty-sixth AND gate (2308), a twenty-first OR gate (2306) being connected to the output of the seventh memorization elements (BAM 2304) and being interposed in the loop line after each of said twenty-fifth AND gates (2305).

23. Apparatus according to claim 21, wherein the inter-data processing priority circuit (FIG. 23) comprises a control element (COM 2201) connected to a first input line (MEP) connected to the output of the eighth bistable memorization element (BH 2309) and to a second input line (MODH), said second input line (MODH) being connected to the output of said eighth memorization element (2309) by means of a twenty-seventh AND gate (2312), energized from the output of said seventh bistable memorization element (BAM 2304); a second loop line (FIG. 22) and as many twenty-seventh AND gates (1404) interconnected in said loop line as possible values of action can be recorded in the matrix, all said twenty-seventh AND gates (1404) being energized by said control element (COM 2201), except that corresponding to the first data processing step to be taken in the hierarchy; and each said thirteenth interrogation lines (FIG. 22: INT CAA) including a twenty-first AND gate (1402), the input of which being connected to the output of the corresponding twenty-seventh AND gate (1404) over an inverter (I 1406), the fourteenth authorization line (AUT CAA) being connected to said loop in advance of the subsequent twenty-seventh AND gate (1404), by means of a twenty-second OR gate (1405).

24. Apparatus according to claim 23, wherein the twenty-first AND gates (1402) have three inputs, the third input being connected across a twenty-third OR gate (1403) to the output of twentieth AND gates (1401), the inputs of which being connected to the fourteenth authorization lines (AUT CAA).

25. Apparatus according to claim 1, wherein the recording lines (FIG. 11a: SORT ACT 0) of all the recording matrices are connected to the inputs of a twenty-eighth AND gate (PACN), the output of which is connected to one of the inputs of a nineteenth OR gate (2401).

26. Apparatus according to claim 1, wherein the outputs (INF B0) of the first memorization elements (FIG. 8: B0 1108) of the connecting elements (EL) corresponding to a matrix are connected to display elements (FIG. 11a: SAFI) associated with the matrices, the outputs of the display elements (SAFI) being connected to the inputs of the sixteenth AND gates (FIN EXT), the output of which controlling the termination of search by the coordination center (CC).

27. Apparatus for the extraction of information for use with data processing apparatus which includes matrices having bistable elements, and temporary memories; a coordination center (CC) controlling the bistable matrices and the temporary matrices, said apparatus analyzing an external system defined by a plurality of parameters, each capable of taking a finite number of values and to undergo, starting from each said values, a finite number of variations, the data processing machine comprising I. a plurality of basiC, functionally non-subdividable sub-assemblies including a. as many connection centers (FIG. 3: CL; CLX, CLY . . . . ) as there are parameters to be memorized, each connection center (CL) comprising as many connection elements (FIG. 8: EL) as there are possible values for the parameter to be considered, each connection element (EL) comprising at least one separate first bistable memorization element (B0 1108); b. as many bi-dimensional recording centers in matrix form (FIG. 3: CI; CIX, CIY . . . . ) as there are parameters in the system, each recording center (CI) comprising recording elements (FIG. 9: EI) included in the recording center matrices, each recording element comprising at least one separate second bistable memorization element (B 1201), each state of said second bistable memorization element corresponding to one of the possible variations of one of the values of the parameter of the respective matrix, and a 1203 AND gate controlled from the output from the second bistable memorization elements (B 1201); (c) at least one value-associative matrix (FIG. 3: CAS; CAS XY . . . . ) comprising as many association elements (FIG. 7: EAS) as the number of possible associations, and having a plurality of third bistable memorization elements (FIG. 7: B 1004, B1 1007, B2 1012), each state of which corresponds to a different parameter, and a 1011 AND gate controlled from one of said third bistable elements; and II. a data extraction and interconnection system comprising a. a first group of four types of interconnecting lines, interconnecting the connecting elements (FIG. 8: EL), with respect to a predetermined parameter, to the recording elements (FIG. 9: EI) with respect to the same said parameter, said four types of lines including: