US20150380391A1

US20150380391A1 - Packaging substrate, method for manufacturing same, and chip packaging structure having same

Info

Publication number: US20150380391A1
Application number: US14/848,504
Authority: US
Inventors: Yong Ha Woo; E-Tung Chou; Wen-Lun Lo
Original assignee: Zhen Ding Technology Co Ltd
Current assignee: Zhen Ding Technology Co Ltd
Priority date: 2012-12-28
Filing date: 2015-09-09
Publication date: 2015-12-31
Also published as: US20140185259A1; CN103904050A; US9173298B2; CN103904050B; TW201436132A

Abstract

A packaging substrate includes a circuit board, a number of first conductive posts, and a number of second conductive posts. The circuit board includes a first base and a first conductive pattern layer formed on a first surface of the first base. The first conductive posts extend from and are electrically connected to the first conductive pattern layer. The second conductive posts extend from and are electrically connected to the first conductive pattern layer. The height of each of the second conductive posts is larger than that of each of the first conductive posts. A manufacturing method thereof is also provided.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This patent application is a divisional application of patent application Ser. No. 14/097,251, filed on Dec. 5, 2013, entitled “PACKAGING SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND CHIP PACKAGING STRUCTURE HAVING SAME”, assigned to the same assignee, which is based on and claims priority from China Patent Application No. 2012-10582244.6, filed in China on Dec. 28, 2012, and disclosures of both related applications are incorporated herein by reference in their entireties.

FIELD

The present disclosure relates to semiconductor packaging technology and, particularly, to a packaging substrate, a method for manufacturing the packaging substrate, and a chip package structure having the packaging substrate.

BACKGROUND

A chip packaging structure includes a packaging substrate, a connecting substrate, and a number of chips. Some of the chips are arranged on and are electrically connected to the packaging substrate, and the other chips are arranged on and are electrically connected to the connecting substrate. The packaging substrate is mechanically and electrically connected to the connecting substrate through a number of solder balls, which are between one surface of the packaging substrate and an opposing surface of the connecting surface. However, the binding force between the packaging substrate and the connecting surface is limited because the contact areas between the solder balls and the surfaces are limited. Thus, the solder balls are easily damaged or dislodged if the chip packaging structure is touched when in transport or in use. This reduces the performance and safety of the chip packaging structure.
Therefore, it is desirable to provide a packaging substrate, a method for manufacturing the packaging substrate, and a chip packaging structure having the packaging substrate, to overcome or at least alleviate the above-mentioned problems.

BRIEF DESCRIPTION OF THE DRAWINGS

Implementations of the present technology will now be described, by way of example only, with reference to the attached figures.

FIG. 1 shows a cross sectional view of a circuit board for a method of manufacturing a packaging substrate according to a first exemplary embodiment.

FIG. 2 shows a cross sectional view of a circuit board in FIG. 1 after forming a metal layer.

FIG. 3 shows a cross sectional view of a circuit board in FIG. 2 after forming a first plating barrier pattern.

FIG. 4 shows a cross sectional view of a circuit board in FIG. 3 after forming a first plating layer.

FIG. 5 shows a cross sectional view of a circuit board in FIG. 4 after forming a second plating barrier pattern on the first plating layer.

FIG. 6 shows a cross section view of a circuit board in FIG. 5 after forming a first etching barrier pattern.

FIG. 7 shows a cross sectional view of a circuit board in FIG. 6 after removing the second plating barrier pattern.

FIG. 8 shows a cross sectional view of a circuit board in FIG. 7 after forming a second plating layer on the first plating layer and the first etching barrier pattern.

FIG. 9 shows a cross sectional view of a circuit board in FIG. 8 after forming a second etching barrier pattern on the second plating layer.

FIG. 10 shows a cross sectional view of a circuit board in FIG. 9 after etching the first plating layer and the second plating layer to form the first conductive posts and the second conductive posts.

FIG. 11 shows a cross sectional view of a circuit board in FIG. 10 after removing the first plating barrier pattern, the first etching barrier pattern, and the second etching barrier pattern.

FIG. 12 is a diagrammatic view of an alternative embodiment of the packaging substrate in FIG. 10 after removing the first etching barrier pattern and the second etching barrier pattern and melting the first etching barrier pattern to form solder caps.

FIG. 13 shows a cross sectional view of a circuit board in FIG. 8 after forming a photoresist layer for a method of manufacturing a package substrate according to a second exemplary embodiment.

FIG. 14 shows a cross sectional view of a circuit board in FIG. 13 after forming a second etching barrier pattern and a protective layer.

FIG. 15 shows a cross sectional view of a circuit board in FIG. 14 after removing the photoresist layer and the first plating barrier pattern and etching the first plating layer and the second plating layer to form the first conductive posts and the second conductive posts.

FIG. 16 is similar to FIG. 12, but showing another embodiment of the packaging substrate.

FIG. 17 is a cross-sectional view of a chip packaging structure, according to a third exemplary embodiment.

DETAILED DESCRIPTION

Referring to FIGS. 1-11, a method for manufacturing a packaging substrate 100 a, according to a first exemplary embodiment, is shown. The method includes the following steps.
Referring to FIG. 1, a circuit board 110 is provided.
The circuit board 110 may be a single-sided circuit board, a double-sided circuit board, or a multilayer circuit board. The circuit board 110 includes a first base 111, a first conductive pattern layer 112, a second conductive pattern layer 113, a first solder mask 114, and a second solder mask 115. In at least one embodiment, the circuit board 110 is a multilayer circuit board, and includes a number of resin layers (not shown) and a number of conductive pattern layers (not shown) alternately stacked on one another.
The first base 111 includes a first surface 1111 and a second surface 1112. The first surface 1111 and the second surface 1112 are positioned at opposite sides of the first base 111, and the first surface 1111 is substantially parallel to the second surface 1112. The first conductive pattern layer 112 is located on the first surface 1111. The second conductive pattern layer 113 is located on the second surface 1112. The first conductive pattern layer 112 is electrically connected to the second conductive pattern layer 113 through via holes (not shown) defined in the first base 111.
The first solder mask 114 covers part of the first surface 1111 which is exposed to the first conductive pattern layer 112, and part of the first conductive pattern layer 112. The first solder mask 114 defines a number of first openings 1141 and a number of second openings 1142. The first openings 1141 are positioned at a central portion of the first solder mask 114 and are arranged in an array. The second openings 1142 surround the first openings 1141. The cross-sectional area of each of the first openings 1141 is less than that of each of the second openings 1142. The first conductive pattern layer 112 is exposed to the first openings 1141 and the second openings 1142.
The second solder mask 115 covers part of the second surface 1112 which is exposed to the second conductive pattern layer 113, and part of the second conductive pattern layer 113. The second solder mask 115 defines a number of third openings 1151. The second conductive pattern layer 113 is exposed to the third openings 1151.
Referring to FIG. 2, a metal layer 120 is formed on the first solder mask 114. The metal layer 120 is copper and serves as a seed layer. In at least one embodiment, the metal layer 120 is formed by a sputtering coating process.
Referring to FIG. 3, a first plating barrier pattern 130 is formed on the second solder mask 115 and on the part of the second conductive pattern layer 113 which is exposed to the second solder mask 115. In at least one embodiment, the first plating barrier pattern 130 is formed by a printing stripping rubber method.
Referring to FIG. 4, a first plating layer 140 is formed on the metal layer 120 and the first conductive pattern layer 112. The first plating layer 140 covers the entire metal layer 120 and the part of the first conductive pattern layer 112 which is exposed to the first openings 1141 and the second openings 1142. In at least one embodiment, the first plating layer 140 is made of copper.
Referring to FIG. 5, a second plating barrier pattern 150 is formed on the first plating layer 140. The second plating barrier pattern 150 defines a number of first through holes 151 corresponding to the first openings 1141. The first through holes 151 are arranged in an array and correspond to pads of a chip to be packaged (not shown). The first through holes 151 may be formed by laser beams.
Referring to FIG. 6, a first etching barrier pattern 160 is formed on the part of the first plating layer 140 which is exposed to the first through holes 151, by a plating method. The first etching barrier pattern 160 corresponds to the first through holes 151. In at least one embodiment, the first etching barrier pattern 160 may be made of tin or nickel. That is, the first etching barrier pattern 160 does not react with an etching agent which can etch away copper. Thus, the part of the first plating layer 140 covered by the first etching barrier pattern 160 can be maintained when the first plating layer 140 is etched by the etching agent. The first etching barrier pattern 160 may be made of other metal which does not react with the etching agent.
Referring to FIGS. 6-7, the second plating barrier pattern 150 is removed by stripping.
Referring to FIG. 8, a second plating layer 170 is formed on the first plating layer 140 and the first etching barrier pattern 160 by plating. In at least one embodiment, the second plating layer 170 is made of copper. The thickness of the second plating layer 170 is larger than that of the first etching barrier pattern 160. That is, the first etching barrier pattern 160 is entirely packaged within the second plating layer 170.
Referring to FIG. 9, a second etching barrier pattern 180 corresponding to the second openings 1142 is formed on the second plating layer 170. A dry film is first attached on the second plating layer 170, and then exposed and developed, thereby the second etching barrier pattern 180 is formed.
Referring to FIG. 10, the first plating layer 140 and the second plating layer 170 are etched to form a number of first conductive posts 191 and a number of second conductive posts 192, using an etching agent. The first conductive post 191 includes the part of the first plating layer 140 which is shielded by the first etching barrier pattern 160. The second conductive post 192 includes the parts of the first and second plating layers 140 and 170 which are shielded by the second etching barrier pattern 180. In at least one embodiment, the etching factor is greater than four, for reducing lateral erosion. The first conductive posts 191 are located in the first openings 1141 and the second conductive posts 192 are located in the second openings 1142. The height of each first conductive post 191 is equal to the thickness of the first plating layer 140. The height of each second conductive post 192 is equal to the sum of the thicknesses of the first plating layer 140 and of the second plating layer 170.
Referring to FIGS. 10-11, the first plating barrier pattern 130, the first etching barrier pattern 160, and the second etching barrier pattern 180 are removed to form the packaging substrate 100 a. In other embodiments, referring to FIG. 10 together with FIG. 12, the first etching barrier pattern 160 does not need to be removed. Instead, the first etching barrier pattern 160 is made molten to form solder caps 193 using an IR-reflow soldering process. The solder caps 193 are configured to protect part of the first conductive pattern layer 112 corresponding to the solder caps 193.
Referring to FIGS. 1-8 and 13-15, a method for manufacturing a packaging substrate 100 b according to a second exemplary embodiment is shown. The first to eighth steps in at least one embodiment are the same as the first to eighth steps in the first embodiment. Thus, the explanation for the method of the second embodiment begins with the ninth step.
Referring to FIG. 13, a photoresist layer 171 with a number of second through holes 172 is formed on the second plating layer 170 and a number of third through holes 131 are defined in the first plating barrier pattern 130. The second through holes 172 correspond to the second openings 1142.
Referring to FIG. 14, a second etching barrier pattern 180 is formed on the part of the second plating layer 170 which is exposed to the second through holes 172 and a protective layer 194 is formed on the part of the second conductive pattern layer 113 which is exposed to the third through holes 131. In at least one embodiment, the second etching barrier pattern 180 and the protective layer 194 are gold plated over nickel and are formed by plating. That is, the second etching barrier pattern 180 serves as a protective layer.
Referring to FIGS. 14-15, the photoresist layer 171 and the first plating barrier pattern 130 are removed. The first plating layer 140 and the second plating layer 170 are etched to form a number of first conductive posts 191 and a number of second conductive posts 192, and thereby the packaging substrate 100 b is formed. The first etching barrier pattern 160 is located on a top end of each of the first conductive posts 191, and the second etching barrier pattern 180 is positioned on a top end of each of the second conductive posts 192. The first etching barrier pattern 160 thus cooperates with the second etching barrier pattern 180 to protect the first conductive pattern layer 112. The protective layer 194 is configured to protect the second conductive pattern layer 113. In other embodiments, referring to FIG. 16 together with FIG. 15, the first etching barrier pattern 160 can be made molten to form solder caps 193 using an IR-reflow soldering process.
Referring to FIG. 12, a packaging substrate 100 a, according to a third exemplary embodiment, is shown. The packaging substrate 100 a includes a circuit board 110, a number of first conductive posts 191, and a number of second conductive posts 192.
The circuit board 110 may be a single-sided circuit board, a double-sided circuit board, or a multilayer circuit board. The circuit board 110 includes a first base 111, a first conductive pattern layer 112, a second conductive pattern layer 113, a first solder mask 114, and a second solder mask 115. In at least one embodiment, the circuit board 110 is a multilayer circuit board, and includes a number of resin layers (not shown) and a number of conductive pattern layers (not shown) alternately stacked on one another.
The first base 111 includes a first surface 1111 and a second surface 1112. The first surface 1111 and the second surface 1112 are positioned at opposite sides of the first base 111, and the first surface 1111 is substantially parallel to the second surface 1112. The first conductive pattern layer 112 is located on the first surface 1111. The second conductive pattern layer 113 is located on the second surface 1112. The first conductive pattern layer 112 is electrically connected to the second conductive pattern layer 113 through via holes (not shown) defined in the first base 111.
The first solder mask 114 covers the part of the first surface 1111 which is exposed to the first conductive pattern layer 112 and part of the first conductive pattern layer 112. The first solder mask 114 defines a number of first openings 1141 and a number of second openings 1142. The first openings 1141 are positioned at a central portion of the first solder mask 114 and are arranged in an array. The second openings 1142 surround the first openings 1141. The cross-sectional area of each first opening 1141 is less than that of each second opening 1142. The first conductive pattern layer 112 is exposed to the first openings 1141 and the second openings 1142.
The second solder mask 115 covers the part of the second surface 1112 which is exposed to the second conductive pattern layer 113 and part of the second conductive pattern layer 113. The second solder mask 115 defines a number of third openings 1151. The second conductive pattern layer 113 is exposed to the third openings 1151.
The first conductive posts 191 correspond to the first openings 1141. The second conductive posts 192 correspond to the second openings 1142. The first conductive posts 191 extend from the first conductive pattern layer 112 in the first openings 1141. The second conductive posts 192 extend from the first conductive patter layer 112 in the second openings 1142. The height of each second conductive post 192 is larger than that of each first conductive post 191. A solder cap 193 is formed on a top end of each first conductive post 191. The solder cap 193 is made of tin or nickel. In other embodiments, a protective layer (not shown) can be formed on a top end of each second conductive post 192, and the protective layer is gold plated over nickel.
Referring to FIG. 17, a chip packaging structure 10, according to a fourth exemplary embodiment, is shown. The chip packaging structure 10 includes a first chip packaging body 11 and a second chip packaging body 12.
The first chip packaging body 11 includes the packaging substrate 100 a of the first embodiment and a first chip 200. The first chip 200 includes a first top surface 201 and a first bottom surface 202. The first top surface 201 and the first bottom surface 202 are positioned at opposite sides of the first chip 200. The first top surface 201 is substantially parallel to the first bottom surface 202. A number of first electrode pads 210 are arranged on the first bottom surface 202 and correspond to the first conductive posts 191. The first chip 200 is supported on the first conductive posts 191. Each first electrode pad 210 contacts a first conductive post 191, and a first solder ball 101 surrounds the entire circumferential surface of a first conductive post 191 and a first electrode pad 210. Thus, the first chip 200 is mechanically and electrically connected to the packaging substrate 100 a. A first packaging glue 102 is infilled into a gap between the first chip 200 and the packaging substrate 100 a to render the connection between the first chip 200 and the packaging substrate 100 a more reliable.
The second chip packaging body 12 includes a connecting substrate 300, a second chip 400, and a third chip 500. The connecting substrate 300 includes a second base 310, a number of first contact pads 320, a number of second contact pads 330, a third solder mask 340, and a fourth solder mask 350.
The second base 310 includes a second top surface 3101 and a second bottom surface 3102. The second top surface 3101 and the second bottom surface 3102 are positioned at opposite sides of the second base 310, and the second top surface 3101 is substantially parallel to the second bottom surface 3102. The second base 310 defines a number of conductive holes 340 corresponding to the second conductive posts 192, the first contact pads 320, and the second contact pads 330. Each of the conductive holes 340 passes through the second top surface 3101 and the second bottom surface 3102.
The first contact pads 320 are formed on the second top surface 3101 and aligned with the conductive holes 340. The second contact pads 330 are formed on the second bottom surface 3102 and aligned with the conductive holes 340. That is, the first contact pads 320 are electrically connected to the second contact pads 330 through the conductive holes 340.
The third solder mask 350 is formed on the second top surface 3101 and defines a number of fourth opening 352 corresponding to the first contact pads 320. Each of the first contact pads 320 is exposed to a fourth opening 352. The fourth solder mask 360 is formed on the second bottom surface 3102 and defines a number of fifth openings 362 corresponding to the second contact pads 330. Each of the second contact pads 330 is exposed to a fifth opening 362.
The second chip 400 is located on the third solder mask 350 by a second packaging glue 600. The third chip 500 is located on the second chip 400 by a dielectric film 700 and is spaced apart from the second chip 400. A number of second electrode pads 410 are formed on the second chip 400 surrounding the second packaging glue 600. A number of third electrode pads 510 are formed on the third chip 500 surrounding the dielectric film 700. The second electrode pads 410 and the third electrode pads 510 are electrically connected to the first contact pads 320 through wires 800. A third packaging glue 105 is formed on the connecting substrate 300 to seal the entire second chip 400, the entire third chip 500, the entire second solder mask 350, and the entirety of wires 800, therefore the connections between the second chip 400, the third chip 500, and the connecting substrate 300 are more reliable.
When the second chip packaging body 12 is packaged on the first chip packaging body 11, the second conductive posts 192 are mechanically and electrically connected to the second contact pads 330 through second solder balls 103. Each second solder ball 103 surrounds the entire circumferential surface of a second conductive post 192 and covers an entire second contact pad 330. In at least one embodiment, a number of third solder balls 106 are formed on the second conductive pattern layer 113 exposed within the third openings 1151. The third solder balls 106 are configured for connecting other electronic elements (not shown). In at least one embodiment, sum of the height of each first conductive post 191 and the thickness of the first chip 200 is equal to the height of each second conductive post 192.
In the chip packaging structure 10, the contact area between the first chip 200 and the first packaging substrate 100 a is increased because the first solder ball 101 surrounds the entire circumferential surface of each first conductive post 191 and each first electrode pad 210. The contact area between the first chip packaging body 11 and the second chip packaging body 12 is increased because each second solder ball 103 surrounds the entire circumferential surface of each second conductive post 192 and covers the entirety of each second contact pad 330. Therefore the first and second solder balls 101 and 103 are more reliable in function and strength even if the chip packaging structure 10 is touched when in transport or in use.
In other embodiments, the packaging substrate 100 b in the second embodiment can be applied in the chip packaging structure 10 instead of applying the packaging substrate 100 a of the first embodiment.
Even though numerous characteristics and advantages of the present embodiments have been set forth in the foregoing description, together with details of the structures and functions of the embodiments, the disclosure is illustrative only, and changes may be made in detail, especially in the matters of shape, size, and arrangement of parts within the principles of the disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.

Claims

What is claimed is:

1. A packaging substrate comprising:

a circuit board comprising a first base and a first conductive pattern layer formed on a first surface of the first base;

a plurality of first conductive posts extending from and electrically connected to the first conductive pattern layer; and

a plurality of second conductive posts extending from and electrically connected to the first conductive pattern layer, the height of each of the second conductive posts being larger than that of each of the first conductive posts.

2. The packaging substrate of claim 1, wherein a solder cap is formed on a top end of each of the first conductive posts.

3. The packaging substrate of claim 1, wherein a protective layer is formed on a top end of each of the second conductive posts, and the protective layer is gold plating over nickel.

4. The packaging substrate of claim 1, wherein the circuit board further comprises a first solder mask covering part of the first surface exposed to the first conductive pattern layer and part of the first conductive pattern layer, the first solder mask defines a plurality of first openings corresponding to the first conductive posts and a plurality of second openings corresponding to the second conductive posts, the first conductive posts are located in the respective first openings, and the second conductive posts are located in the respective second openings.

5. The packaging substrate of claim 4, wherein the circuit board further comprises a second conductive pattern layer formed on an opposing second surface of the first base and a second solder mask, the second solder mask defines a plurality of third openings, part of the second conductive pattern layer is exposed to the third openings.

6. The packaging substrate of claim 5, wherein a protective layer is formed on the part of the second conductive pattern layer exposed to the third openings.

7. The packaging substrate of claim 1, wherein the first conductive posts are located at a central portion of the first conductive pattern layer, and the second conductive posts surround the first conductive posts.

8. A chip packaging structure comprising:

a first chip packaging body comprising a packaging substrate and a first chip, the packaging substrate comprising:

a plurality of second conductive posts extending from and electrically connected to the first conductive pattern layer, the height of each of the second conductive posts being larger than that of each of the first conductive posts;

the first chip comprising a plurality of first electrode pads corresponding to the first conductive posts, the first electrode pads mechanically and electrically connected to the respective first conductive posts through first solder balls; and

a second chip packaging body comprising a connecting substrate and a second chip packaged on the connecting substrate, the connecting substrate comprising a plurality of first contact pads corresponding to the second conductive posts, and the first contact pads mechanically and electrically connected to the respective second conductive posts through second solder balls.

9. The chip packaging structure of claim 8, wherein a sum of the height of each of the first conductive posts and the thickness of the first chip is equal to the height of each of the second conductive posts.

10. The chip packaging structure of claim 9, wherein a solder cap is formed on a top end of each of the first conductive posts.

11. The chip packaging structure of claim 9, wherein a protective layer is formed on a top end of each of the second conductive posts, and the protective layer is gold plating over nickel.

12. The chip packaging structure of claim 9, wherein the circuit board further comprises a first solder mask covering part of the first surface exposed to the first conductive pattern layer and part of the first conductive pattern layer, the first solder mask defines a plurality of first openings corresponding to the first conductive posts and a plurality of second openings corresponding to the second conductive posts, the first conductive posts are located in the respective first openings, and the second conductive posts are located in the respective second openings.

13. The chip packaging structure of claim 12, wherein the circuit board further comprises a second conductive pattern layer formed on an opposing second surface of the first base and a second solder mask, the second solder mask defines a plurality of third openings, part of the second conductive pattern layer is exposed to the third openings.

14. The chip packaging structure of claim 13, wherein a protective layer is formed on the part of the second conductive pattern layer exposed to the third openings.

15. The chip packaging structure of claim 9, wherein the first conductive posts are located at a central portion of the first conductive pattern layer, and the second conductive posts surround the first conductive posts.