US20150206908A1 - Focal plane array and method for manufacturing the same - Google Patents
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Abstract
A method of forming a focal plane array by: preparing a first wafer having sensing material provided on a surface, which is covered by a sacrificial layer; preparing a second wafer including read-out integrated circuit and a contact pad, which is covered by another sacrificial layer into which are formed support legs in contact with the contact pad, the support legs being covered with a further sacrificial layer; bonding the sacrificial layers of the first and second wafers together such that the sensing material is transferred from the first wafer to the second wafer when a sacrificial bulk layer of the first wafer is removed; defining a pixel in the sensing material and forming a conductive via through the pixel for providing a connection between an uppermost surface of the pixel and the supporting legs; and removing the sacrificial layers to release the pixel, with the supporting legs underneath it.
Description
- This application is a continuation of a national stage application No. 13/582,103 filed Oct. 4, 2012, under 35 U.S.C. §371, of International Application No. PCT/EP2011/053049, filed Mar. 1, 2011, which claims priority to European Application No. 10155250.3, filed Mar. 2, 2010, with above-identified applications incorporated by reference herein in their entireties.
- The present invention relates to the manufacture of focal plane arrays and, in particular, the manufacture of a focal plane array for use in a thermal imaging device, using transfer bonding of sensing material.
- The resolution of an imaging device is very much dependent on the number of pixels provided in its focal plane array. The number of pixels is, in turn, limited by the dimensions of the focal plane array.
- In existing focal plane arrays, pixels are generally supported by legs that extend from opposing sides. However, legs arranged in this way occupy valuable space within the focal plane array, which limits the amount of sensing material available and hence limits the performance of the imaging device.
- Accordingly, an aim of the present invention is to provide a focal plane array in which the active sensing area is maximised.
- According to the present invention there is provided a method of forming a focal plane array comprising one or more pixels, the focal plane array being fabricated by: preparing a first wafer having sensing material provided on a surface, which is covered by a first sacrificial layer; preparing a second wafer including read-out integrated circuit (ROIC) and a contact pad, which is covered by a second sacrificial layer into which are formed one or more support legs in contact with the contact pad, the support legs being covered with a further sacrificial layer; bonding the sacrificial layers of the first and second wafers together such that the sensing material is transferred from the first wafer to the second wafer when a sacrificial bulk layer of the first wafer is removed; defining a pixel in the sensing material above each of the one or more support legs and forming a conductive via through each pixel defined for providing a connection between an uppermost surface of the pixel and its support legs; and removing the sacrificial layers to release the one or more pixel, each of the one or more pixels being defined such that its support legs are arranged to be completely beneath the sensing material of the pixel.
- The support legs are free-standing and act as mechanical support to separate the pixel from the ROIC substrate while ensuring that the active sensing area is maximised, due to the legs being arranged to be completely beneath the sensing material of each pixel in the focal plane array. The legs also provide an electrical connection for each pixel to the ROTC lying beneath the focal plane array.
- As the pixel legs do not take up any space to the sides of the pixels, the total area of active sensing material can be maximised in an array when compared to the area available in an array having conventional pixels with legs at their sides.
- Furthermore, focal plane arrays manufactured according to the method of the present invention are two level-structures, which are realised by use of wafer bonding. In addition to maximising the active sensing area available, the present invention also provides a manufacturing method which enables a plurality of vacuum encapsulated focal plane arrays to be formed simultaneously at wafer level on a single ROIC substrate, which can subsequently be diced to provide individual focal plane arrays.
- The wafer-level transfer of the sensing material onto the ROIC allows the utilisation of high performance crystalline materials, which could not previously be used due to the layer-wise construction of the pixels required.
- According to the method of the present invention, a high performance focal plane array having peak responsivity in the 7 to 14 μm wavelength region can be achieved. The array resolution is typically in the range of quarter VGA to full VGA, but is not limited to this range. Pixel pitch for this wavelength is typically in the
range 13 to 40 μm. - An example of the present invention will now be described with reference to the accompanying figures, in which:
-
FIG. 1 is a plan view of a focal plane array (FPA) according to an example of the present invention; -
FIG. 2 is a schematic representation of a pixel of the focal plane array ofFIG. 1 , taken through section A-A; -
FIG. 3 is a representation of a sectional view through a pixel sealed within the focal plane array ofFIG. 1 , taken through section B-B; -
FIGS. 4A , 4B, 4C, 4D, 4E, and 4F show the steps for preparing a pre-processed read-out integrated circuit (ROIC) for transfer bonding; -
FIGS. 5A , 5B, and 5C show the steps for forming an infra-red (IR) wafer prior to transfer bonding of the thermistor material; -
FIG. 6 is a sectional view of a pixel structure after the IR wafer has been bonded to the ROIC wafer; -
FIG. 7 is a sectional view through the pixel structure after the thermistor material has been transferred to the ROIC wafer; -
FIGS. 8A , 8B, 8C, 8D, 8E, 8F, 8G, and 8H show the process steps for defining a pixel and forming a conductive contact plug through it; -
FIGS. 9A , 9B, 9C, 9D, and 9E show the process steps for forming a bonding frame on the ROIC wafer; -
FIG. 10 is a sectional view of a released pixel ready for cap wafer sealing; and -
FIGS. 11A , 11B, 11C, 11D, 11E, and 11F show the steps for forming a cap wafer for sealing the focal plane array. -
FIG. 1 shows a plan view of a focal plane array (FPA) 1, according to the present invention, before sealing, the FPA comprising a plurality ofpixels 2 arranged in an array. The focal plane array 1 of this example is suitable for a thermal imaging device and hence eachpixel 2 is a bolometer pixel comprisingsensing material 3, which in this example consists of a thermistor built as a layer stack of for example, Si and SiGe with contacting and buffer layers, as will be described in detail below. - The material for the
thermistor 3 is chosen on the basis that it has a strong temperature dependent resistivity. Energy absorbed in the layers generates heat, resulting in a measurable change in thethermistor 3 resistance. Absorption of the infra-red (IR) waves 6 is enhanced by the introduction of an absorber layer 4 positioned on an upper surface of thethermistor 3 at a wavelength optimised distance from areflector layer 5 that is deposited on the reverse side of thethermistor 3, as can be seen inFIG. 2 . - Once the FPA 1 has been formed, as will be described below, a
cap wafer 10 is sealed, in a vacuum, over the FPA 1 and thus heat transfer from thepixels 2 to the surroundings is low. A bondingframe 11 is provided around the FPA 1 for thecap wafer 10 to be sealed onto. - The
pixels 2 arranged around the outer edge of the FPA 1 are thermally-shorted or “blind”, reference pixels. In addition, the FPA may also contain temperature sensors and vacuum level sensors. The analogue signals from thepixels 2 are converted to digital format by read-out integrated circuitry (ROIC) provided on aROIC wafer 9 and this information is used to present an image. -
FIG. 2 shows a schematic representation of a section (A-A) of the FPA inFIG. 1 showing the basic structure of atypical pixel 2 formed by the method of the present invention. In particular it can be seen how eachpixel 2 is spaced apart from the ROICwafer 9 by free-standing supportinglegs 7 that are provided underneath thepixel 2. Theselegs 7 provide the dual function of acting as mechanical supports for thepixel 2, as well as providing an electrical connection between thepixel 2 and the ROIC lying beneath it on theROIC wafer 9. Both the material and design of thepixel legs 7 are selected to ensure that heat transfer from thepixel 2 to the surroundings is minimised. -
FIG. 3 is a schematic representation of a section (B-B) of the FPA inFIG. 1 showing aresulting pixel 2 formed by the method of the present invention. In all of the following figures, thepixels 2 are represented according to section B-B ofFIG. 1 , although it should be understood that thepixels 2 are actually defined as two halves, as shown in the representation ofFIG. 2 . The pixels are mirrored across atrench 16 that is etched into theIR wafer 8, as will be described below. - It can be seen from
FIG. 3 that a bondingframe 11 structure for supporting thecap wafer 10 is provided to the side of thepixel 2. The capped FPA 1 starts out as three separate wafers: an ROIC wafer 9, anIR wafer 12 including thethermistor material 3, and acap wafer 10. TheIR wafer 12 andROIC wafer 9 are joined by transfer bonding of thethermistor material 3 to form thepixels 2, which are then sealed by thecap wafer 10 using a suitable bonding method, such as Cu—Sn bonding, to bond it to the bondingframe 11. - The ROIC
wafer 9 is pre-fabricated using standard CMOS processing technology, which is well known and hence not further described here. However, irregularities are shown on thetop surface 13 of theROIC wafer 9 to illustrate a typical top surface topography that might result from standard CMOS processing. - The
IR wafer 8, in this example, is created by using a standard silicon-on-insulator (SOI) wafer 12 having a BOX layer 14, and a device layer having a thickness appropriate for being a first, highly doped p+ Si layer in a layer stack that forms thesensing material 3. Of course, any suitable carrier may be used in place of the SOI wafer. The rest of the layers, including the required doping layer, are built by epitaxial growth of single crystalline Si and SiGe to create quantum well layers on top of the un-patterned SOI wafer. These quantum well layers thereby provide an IRsensitive thermistor material 3. Single or multiple quantum well layers may be used depending on performance requirements. - The
thermistor material 3 used in theIR wafer 12 is, preferably, based on a material concept described in U.S. Pat. No. 6,292,089 and consists of single crystal Si and SiGe quantum well layers. Thisthermistor 3 material has a high temperature coefficient of resistance as well as low noise characteristics, and is fully compatible with standard CMOS processes. Highly doped p+ Si layers (around 1019 cm.sup.-3) are used on both sides of the quantum well layers structure to provide ohmic contacts to thethermistor 3. Furthermore, an undoped Si barrier layer must exist between the highly doped p+ Si layers and the quantum well layers. SOI wafers and their formation are well known in the art. In this example of the present invention, the total thickness of all layers provided above a BOX layer 14 of theSOI wafer 12 should be wavelength optimised, which for the present invention will be, ideally, around 0.5 to 0.7 μm. - The manufacturing process of the present invention will now be described in detail with reference to a
single pixel 2, although it will be understood that a plurality of pixels can be formed in an array, simultaneously, using this method. -
FIGS. 4A through 4F show the steps for preparing the pre-fabricated ROIC wafer 9 (as shown inFIG. 4A ) for bonding, including forming the supportinglegs 7. First, athin insulator layer 16 of, for example, Al2O3 is deposited (as shown inFIG. 4B ), preferably by atomic layer deposition (ALD) on the surface of theROIC wafer 9. Thisinsulator layer 16 will serve as an etch barrier against vapor HF used at a later stage to release thepixels 2. However, thisinsulator layer 16 needs to be removed from themetal ROIC pads 17 of theROIC wafer 9 and hence it is also patterned by lithography and etched (also as shown inFIG. 4B ). The etching should stop at the underlyingmetal ROIC pads 17, but selectivity is typically not critical at this step (commonly used pad materials are AlSi, AlCu or AlSiCu). - Following the above process steps, a low
temperature oxide layer 18 is deposited (as shown inFIG. 4C ) on theROIC wafer 9 using, for example, plasma-enhanced chemical vapor deposition (PECVD), and then polished to planarize it. Contactwindows 19 to themetal ROIC pads 17 are then opened by etching through the oxide layer 27 (as shown inFIG. 4D ). Next, athin film material 7 is deposited and patterned (as shown inFIG. 4E ) to form legs for thepixel 2. The flatness of thelegs 7 relies on the level of planarity ensured by the first oxide deposition (as shown inFIG. 4C ) and the subsequent polishing. A further layer oflow temperature oxide 18 is then deposited (as shown inFIG. 4F ) and polished to planarize it. At this point, theROIC wafer 9 is ready for bonding to theIR wafer 8. - An alternative procedure is to first planarize the
ROIC wafer 9 surface by depositing a low temperature oxide having a thickness greater than the topography of thewafer surface 13 using, for example PECVD. This oxide layer is then polished to planarize it and then contact holes are etched through it, down to theROTC metal pads 17, Following this, a metal layer can be deposited and patterned to act as the ROTC contact pads and the above described steps shown inFIGS. 4B to 4F are then followed. In this alternative, theinsulator layer 26 is deposited on a planarized surface instead of a surface withirregularities 13. - A further alternative process is to reorder the steps of the process such that the patterning of the insulator layer in the step shown in
FIG. 4B is instead combined with the step shown inFIG. 4D , after the step shown inFIG. 4C , as a double etch process, such that the patterning of the ALD layer can be performed after the contact windows are opened. - As discussed above, the material for the
legs 7 must be selected to provide them with mechanical strength to support thepixel 2, ensure a good electrical connection, whilst preventing heat conduction, between thepixel 2 and the ROIC on theROIC wafer 9 via thelegs 7. This material must also withstand the subsequent etching of the sacrificial oxide layers to release thepixels 2. An example of a suitable material for thelegs 7 is amorphous TiAl. -
FIGS. 5A through 5C show the steps for processing theIR wafer 8. First, an IR wafer is provided (as shown inFIG. 5A ), as described above. A thinfilm metal layer 5, for example AlSi or TiAl, is deposited (as shown inFIG. 5B ) to act as areflector layer 5, which is also used for ohmic contact. Following the metal layer deposition, alow temperature oxide 19 is deposited (as shown inFIG. 5C ) by, for example, plasma-enhanced chemical vapor deposition (PECVD) and then polished to planarize it. At this point theIR wafer 8 is ready to be bonded to theROIC wafer 9. -
FIG. 6 shows theIR wafer 8 and theROIC wafer 9 joined together by using a transfer bonding process, during which the twowafers sensitive thermistor layer 3 and thereflector layer 5 are transferred to theROIC wafer 9. The wafer bonding process uses oxide-oxide bonding between theoxide layer 19 on theIR wafer 8 and theoxide layer 18 on theROIC wafer 9, performed at temperatures less than 400° C., to form a bondedoxide layer 20. - Alternatively, the
IR wafer 8 andROTC wafer 9 can be bonded together by providing an adhesive on at least one of the oxide layers 18, 19. -
FIG. 7 shows the combined IR and ROTC wafers after removal of thesacrificial handle layer 15 and the BOX oxide layer 14 of theoriginal SOI wafer 12 that was used to create theIR wafer 8. Removal of thesesacrificial layers 14, 15 is preferably by grinding and/or etching. Following removal of thesesacrificial layers 14, 15, thethermistor 3, comprising the thin stack of Si and SiGe layers, has effectively been transferred from the IR wafer to the ROTC wafer. -
FIGS. 8A through 8H show the steps for defining thepixels 2 and creating a conductive contact 21 between the upper side of thepixels 2 and the supportinglegs 7. - First, a first thin film material, for example MoSi2 or TiAl, is deposited (as shown in
FIG. 8A ) over thethermistor layer 3 to act as an absorber layer 4 in the 7-14 μm range of the electromagnetic spectrum. Anoxide layer 22 is, preferably, then sputtered on top of the absorber layer 4, to protect it during a mask-less etching of the insulator layer which follows. Theoxide layer 22 may be considered optional, however, depending on the conditions of the etch processes involved. Acontact window 23 is then etched (as shown inFIG. 8B ) into theoxide layer 22 and the absorber layer 4 at a point above the supportinglegs 7 and a conductive thin-film material 24, for example AlSi, is then deposited (as shown inFIG. 8C ) on the surface of thethermistor layer 3 and theoxide layer 22 that are immediately adjacent to the walls of thecontact window 23 to form a top-side contact 24. Next, atrench 25 is etched (as shown inFIG. 8D ) into theoxide layer 22, the absorber layer 4 and thethermistor layer 3, at a position to the side of thecontact window 23, for separating thepixel 2 into two halves. - The outline of the
pixel 2 is then defined (as shown inFIG. 8E ) by etching through theoxide layer 22, the absorber layer 4, thethermistor layer 3 and thereflector layer 5. Next, thecontact window 23 is extended down (as shown inFIG. 8F ) through thepixel 2 to the underlying supportinglegs 7, formed within theROIC wafer 9, by etching through thethermistor layer 3, thereflector layer 5 and the bondedoxide layer 20 to form a via 26. - A skilled person will recognize that the etching processes described herein include etching steps that are common to several of them. The etching steps are, however, performed separately in order to minimize the fill factor loss caused by the inaccuracies of the alignment between the different lithography layers.
- A thin layer of
insulator material 27, for example Al2O3, is then deposited, preferably by atomic layer deposition (ALD) over the exposed surfaces, and then patterned such that it is removed from all the horizontal surfaces and kept on the vertical ones (as shown inFIG. 8G ). Theinsulator layer 27 provided on the sidewalls of the via 26 provides electrical insulation to thethermistor material 3. Finally, aconductive contact 28 is defined (as shown inFIG. 8H ) by metal deposition, for example TiAl, and then patterned. - The
insulator layer 27 can optionally be kept on top of the absorber layer 4, although performance of thepixel 2 decreases somewhat if it is not removed. In this alternative, a further patterning is required to etch open a contact window in theinsulator layer 27 to allow the etching of the sacrificial bondedoxide layer 20 underneath thepixel 2 in order to release it later on. -
FIG. 9 illustrates abonding frame 11 being formed on theROIC wafer 9, thebonding frame 11 being arranged around the perimeter of a focal plane array 1 to prepare it for encapsulation by acap wafer 10. Thebonding frame 11 is formed as follows.Oxide layer 32 is built up by additional oxide being deposited over the surface of the pixel structure, which is then patterned (as shown inFIG. 9A ) such that it covers the area of thepixels 2 to protect them from the deposition of ametal layer 33 that follows, as will be explained below. Next, acontact window 32 is etched (as shown inFIG. 9B ) into theoxide layer 22 down to theinsulator layer 16 which was previously deposited on theROIC wafer 9 during its preparation. Athin metal layer 33, for example TiW/Cu is then deposited (as shown inFIG. 9C ) on the exposed surfaces of theROIC wafer 9 and theoxide layer 22. Themetal layer 33 serves as a seed and adhesive for electroplating that follows. First, however, a thick electroplating resist is deposited 34 and patterned beforematerials bonding frame 11, such as Cu and Sn, are electroplated (as shown inFIG. 9D ) onto the surface of theROIC wafer 9 within thecontact window 32 to form thebonding frame 11. Finally, the electroplating resist 34 and the exposedmetal layer 33 are removed (as shown inFIG. 9E ), leaving thebonding frame 11 ready to receive thecap wafer 10. -
FIG. 10 shows the last step in defining thepixels 2, which is the removal of the sacrificial oxide layers 20, 22 to release thepixels 2. The sacrificial oxide layers 20, 22 are preferably removed using anhydrous vapor HF, which is compatible with all of the exposed materials. Following the release of thepixels 2, the FPA 1 is ready for cap bonding. Given the fact that at the moment of cap bonding thepixels 2 are already released, no wet chemical treatment of the wafers is allowed because of the fragility of the FPA 1. -
FIGS. 11A through 11F show the steps of forming thecap wafer 10 for encapsulating the FPA 1 under vacuum to reduce heat transfer away from thepixels 2. Thecap wafer 10 used for the hermetic vacuum encapsulation of the focal plane array is required to transmit the incident IR waves. Both Si and Ge exhibit high optical transmittance in the wavelength range of interest and are therefore both suitable for this purpose. However, the thermal expansion coefficient of Ge is high compared to that of Si, which will result in high thermal residual stresses being induced in the bonded materials and thus Si is the preferred choice. Selecting the thickness of thecap wafer 10 is a tradeoff between the need to minimize the absorption, wherein the thinner the wafer the better, and the requirements of safe handling during processing. Thecap wafer 10 can be formed as follows. - First,
cavities 37 are etched (as shown inFIG. 11A ) into the cap wafer, which is done for a number of reasons, such as: to accommodate the different thin films required by the functionality of the focal plane array, as described below; to cope with bowing of the cap wafer that results from the atmospheric pressure pressing from the top side of the cap; and to provide a sufficient distance above wire bonding pads that are provided outside the sealed cap (not shown) to allow subsequent sawing for the release of these pads. - An
antireflective coating 38 is then deposited (as shownFIG. 11B ) on one or both sides of thecap wafer 10 to minimize the reflection of the IR radiation. In the example shown, thecoating 38 has been deposited on both sides of thecap wafer 10. A long-wave pass (LWP) filter can also be provided on the surface of thecap wafer 10, preferably as part of theantireflective coating 38, to block short wavelengths and prevent the heating of thepixels 2 by direct exposure to sunlight. The LWP filter is, in principle, needed only on the outer top surface of thecap wafer 10. - However, such a difference in layers on the two sides of the
cap wafer 10 can introduce considerable stress and therefore cause thecap wafer 10 to bow. If severe, this bowing will prevent thecap wafer 10 from bonding. Both the LWP filter andantireflective coating 38 are therefore, preferably, deposited on both surfaces of thecap wafer 10. On the underside of thecap wafer 10 thecoating 38 and filter can be patterned so that it is removed from the areas to be bonded. - Next, an optional patterned thin film
non-evaporable getter 39 is deposited (as shown inFIG. 11C ), for example by means of shadow mask technology, to trap potential residual gases in the bonded cavities and thereby ensure the required vacuum level for the whole life time of the FPA. Thegetter 39 should not be placed above theactive pixels 2 in case it is not transparent to IR radiation. Thus it is located above the blind reference pixels and ROIC electronics. Similar to the formation of thebonding frame 11 on theROIC wafer 9, athin metal layer 40, for example TiW/Cu, is deposited (as shown inFIG. 11D ) on the unetched, raised portion of thecap wafer 10 to act as an adhesive and seed, before athick electroplating photoresist 41 is deposited and patterned (as shown inFIG. 11E ). Finally, metal layer(s) that will form the bonding frame, in this example Cu and Sn, or just Cu, are electroplated (as shown inFIG. 11F ) onto the surface of thecap wafer 10 to define thebonding frame 42 on the cap wafer, which is followed by the removal of thephotoresist 41 and thethin metal layer 40. - As explained above, the
cap wafer 10 encapsulates the focal plane array 1 by bonding thebonding frame 42 on thecap wafer 10 to thebonding frame 11 provided on theROIC wafer 9, under vacuum to seal thepixels 2 within the focal plane array 1. - Although the manufacture of an individual focal plane array 1 is discussed in the example above, the method of the present invention is preferably used to manufacture a plurality of focal plane arrays on a
single ROIC wafer 9, which are then encapsulated by asingle cap wafer 10 at wafer-level, using a suitable sealing method such as Cu—Sn bonding (although other approaches such as Au—Sn bonding are equally applicable) before being diced into a plurality of individual focal plane arrays. The method of the invention therefore enables more efficient and reliable manufacture of devices through wafer-level encapsulation prior to dicing.
Claims (29)
1. A method of forming a focal plane array comprising one or more pixels, the focal plane array being fabricated by:
preparing a first wafer having sensing material provided on a surface, which is covered by a first sacrificial layer;
preparing a second wafer including read-out integrated circuit (ROIC) and a contact pad, which is covered by a second sacrificial layer into which are formed one or more support legs in contact with the contact pad, the support legs being covered with a further sacrificial layer;
bonding the sacrificial layers of the first and second wafers together such that the sensing material is transferred from the first wafer to the second wafer when a sacrificial bulk layer of the first wafer is removed;
defining a pixel in the sensing material above each of the one or more support legs and forming a conductive via through each pixel defined for providing a connection between an uppermost surface of the pixel and its support legs; and
removing the sacrificial layers to release the one or more pixel, each of the one or more pixels being defined such that its support legs are arranged to be completely beneath the sensing material of the pixel.
2. The method of claim 1 , further comprising the step of providing a reflector layer between the surface of the first wafer and the sensing material provided on its surface.
3. The method of claim 2 , further comprising the step of providing an absorber layer on the surface of the sensing material after the bulk layer is removed.
4. The method of claim 3 , wherein the sensing material is infrared (IR) sensitive.
5. The method of claim 4 , wherein the sensing material is a thermistor material and the pixel is a bolometer pixel.
6. The method of claim 5 , further comprising the step of encapsulating the at least one pixel beneath a cap that is sealed over the focal plane array.
7. The method of claim 6 , further comprising the step of forming at least one bonding member on the second wafer for the cap to be bonded to.
8. The method of claim 7 , wherein a plurality of focal plane arrays are provided on the second wafer, each focal plane array being defined by a plurality of bonding members, wherein the plurality of focal plane arrays are sealed by a single cap wafer following which they can be divided into individual focal plane arrays.
9. A thermal imaging device comprising a focal plane array manufactured by the method of claim 1 .
10. A pixel assembly for a focal plane array, the pixel assembly comprising:
a pixel comprising:
a reflecting layer; and
a sensing layer comprising a sensing material formed on one side of the reflecting layer;
a support leg positioned entirely on a reverse side of the reflecting layer and arranged to support, in use, the pixel on a wafer and provide electrical connection between the pixel and the wafer,
wherein said support leg is completely beneath the sensing material when supporting the pixel on the wafer; and
a via associated with the support leg, each via providing electrical connection through the sensing layer from the support leg to the sensing material of the pixel.
11. A pixel assembly according to claim 10 formed as an infrared detector.
12. A focal plane array formed from a plurality of pixels in accordance with claim 10 .
13. The method of claim 1 , further comprising the step of providing an absorber layer on the surface of the sensing material after the bulk layer is removed.
14. The method of claim 13 , wherein the sensing material is infrared (IR) sensitive.
15. The method of claim 14 , wherein the sensing material is a thermistor material and the pixel is a bolometer pixel.
16. The method of claim 15 , further comprising the step of encapsulating the at least one pixel beneath a cap that is sealed over the focal plane array.
17. The method of claim 16 , further comprising the step of forming at least one bonding member on the second wafer for the cap to be bonded to.
18. The method of claim 17 , wherein a plurality of focal plane arrays are provided on the second wafer, each focal plane array being defined by a plurality of bonding members, wherein the plurality of focal plane arrays are sealed by a single cap wafer following which they can be divided into individual focal plane arrays.
19. The method of claim 1 , wherein the sensing material is infrared (IR) sensitive.
20. The method of claim 1 , further comprising the step of encapsulating the at least one pixel beneath a cap that is sealed over the focal plane array.
21. The pixel assembly of claim 10 , including a conductive contact that communicates electrically with the support leg and extends through the via to intersect the sensing material of the pixel.
22. The pixel assembly of claim 21 , wherein said support leg contacts the conductive contact.
23. The pixel assembly of claim 21 , wherein said support leg is elongated and projects laterally along the pixel and relative to the conductive contact.
24. A pixel assembly for a focal plane array, the pixel assembly comprising:
a pixel comprising:
a reflecting layer; and
a sensing layer comprising a sensing material formed on one side of the reflecting layer;
a support leg positioned entirely on a reverse side of the reflecting layer and arranged to support, in use, the pixel on a wafer and provide electrical connection between the pixel and the wafer,
wherein said support leg is completely beneath the sensing material when supporting the pixel on the wafer;
a via associated with the support leg, each via providing electrical connection through the sensing layer from the support leg to the sensing material of the pixel; and
a conductive contact that communicates electrically with the support leg and extends through the via to intersect the sensing material of the pixel,
wherein said support leg is elongated and projects laterally along the pixel and relative to the conductive contact, and
wherein said support leg presents opposite leg ends spaced laterally from one another, with one of the leg ends being attached to the conductive contact and the other one of the leg ends operable to be in supporting engagement with the wafer.
25. The pixel assembly of claim 24 , wherein said support leg includes a thin film material that extends between the leg ends.
26. The pixel assembly of claim 24 , wherein said one leg end is spaced laterally outboard from said other leg end.
27. The pixel assembly of claim 10 , wherein said support leg is spaced below the reflecting layer.
28. The pixel assembly of claim 10 , wherein said sensing material presents a laterally outermost extent and said support leg is located entirely within the laterally outermost extent of the sensing material.
29. The pixel assembly of claim 10 , wherein said support leg includes a thin film material.
Priority Applications (1)
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US14/595,003 US20150206908A1 (en) | 2010-03-02 | 2015-01-12 | Focal plane array and method for manufacturing the same |
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EP10155250.3 | 2010-03-02 | ||
EP10155250A EP2363888A1 (en) | 2010-03-02 | 2010-03-02 | Focal plane array and method for manufacturing the same |
PCT/EP2011/053049 WO2011107486A1 (en) | 2010-03-02 | 2011-03-01 | Focal plane array and method for manufacturing the same |
US201213582103A | 2012-10-04 | 2012-10-04 | |
US14/595,003 US20150206908A1 (en) | 2010-03-02 | 2015-01-12 | Focal plane array and method for manufacturing the same |
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PCT/EP2011/053049 Continuation WO2011107486A1 (en) | 2010-03-02 | 2011-03-01 | Focal plane array and method for manufacturing the same |
US13/582,103 Continuation US8952479B2 (en) | 2010-03-02 | 2011-03-01 | Focal plane array and method for manufacturing the same |
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US14/595,003 Abandoned US20150206908A1 (en) | 2010-03-02 | 2015-01-12 | Focal plane array and method for manufacturing the same |
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EP (2) | EP2363888A1 (en) |
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RU (1) | RU2568953C2 (en) |
WO (1) | WO2011107486A1 (en) |
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US8975583B2 (en) * | 2012-03-08 | 2015-03-10 | Bae Systems Information And Electronic Systems Integration Inc. | 3D stacked uncooled IR sensor device and method |
DE102012217154A1 (en) | 2012-09-24 | 2014-03-27 | Robert Bosch Gmbh | Semiconductor device and method of manufacturing a semiconductor device |
US10396012B2 (en) | 2016-05-27 | 2019-08-27 | International Business Machines Corporation | Advanced through substrate via metallization in three dimensional semiconductor integration |
US11187590B2 (en) * | 2018-11-13 | 2021-11-30 | Institut National D'optique | Microbolometer detectors and arrays for printed photonics applications |
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US6329649B1 (en) * | 1998-10-07 | 2001-12-11 | Raytheon Company | Mm-wave/IR monolithically integrated focal plane array |
US6287940B1 (en) * | 1999-08-02 | 2001-09-11 | Honeywell International Inc. | Dual wafer attachment process |
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JP3944465B2 (en) * | 2003-04-11 | 2007-07-11 | 三菱電機株式会社 | Thermal infrared detector and infrared focal plane array |
GB2411521A (en) * | 2004-02-27 | 2005-08-31 | Qinetiq Ltd | Fabrication method for micro-sensor device |
DE102006019080B3 (en) * | 2006-04-25 | 2007-08-30 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Housing manufacturing method for e.g. infrared sensor, involves enclosing electrical circuit along metal frame, where circuit is isolated along isolating contour that does not cut surface of substrate |
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2010
- 2010-03-02 EP EP10155250A patent/EP2363888A1/en not_active Withdrawn
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2011
- 2011-03-01 CN CN2011800120173A patent/CN102884628A/en active Pending
- 2011-03-01 RU RU2012141155/28A patent/RU2568953C2/en not_active IP Right Cessation
- 2011-03-01 CA CA2791336A patent/CA2791336A1/en not_active Abandoned
- 2011-03-01 US US13/582,103 patent/US8952479B2/en not_active Expired - Fee Related
- 2011-03-01 WO PCT/EP2011/053049 patent/WO2011107486A1/en active Application Filing
- 2011-03-01 EP EP11708757A patent/EP2543070A1/en not_active Withdrawn
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2015
- 2015-01-12 US US14/595,003 patent/US20150206908A1/en not_active Abandoned
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WO2011107486A1 (en) | 2011-09-09 |
US8952479B2 (en) | 2015-02-10 |
EP2543070A1 (en) | 2013-01-09 |
CA2791336A1 (en) | 2011-09-09 |
CN102884628A (en) | 2013-01-16 |
US20130026596A1 (en) | 2013-01-31 |
EP2363888A1 (en) | 2011-09-07 |
RU2012141155A (en) | 2014-04-10 |
RU2568953C2 (en) | 2015-11-20 |
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