US20140307382A1

US20140307382A1 - Semiconductor storage device and method of manufacturing the same

Info

Publication number: US20140307382A1
Application number: US14/307,288
Authority: US
Inventors: Takakatsu Moriai; Toyokazu Eguchi; Atsushi Kaneko; Atsushi Okada
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 2009-07-24
Filing date: 2014-06-17
Publication date: 2014-10-16
Also published as: US20110273834A1; US8787022B2

Abstract

According to one embodiment, coupling capacitance in a state in which a first heat radiation member is arranged between parallel flat plates of a first capacitor formed by a surface of a housing opposed to one surface of a printed circuit board and the printed circuit board is smaller than coupling capacitance in a state in which an integrally formed object having a relative dielectric constant of 5.8 is arranged between the first capacitor to cover a first radiating region containing the controller and the first nonvolatile semiconductor memories.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of and claims the benefit of priority under 35 U.S.C. §120 from U.S. application Ser. No. 13/010,475, filed Jan. 20, 2011, which is a continuation-in-part of application Ser. No. 12/839,785, filed Jul. 20, 2010, now abandoned, and is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2009-172942, filed on Jul. 24, 2009, Japanese Patent Application No. 2009-293492, filed on Dec. 24, 2009, and Japanese Patent Application No. 2010-121629, filed on May 27, 2010, the entire contents of all of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor storage device and a method of manufacturing the same.

BACKGROUND

As an auxiliary storage device mounted on a computer, an auxiliary storage device including a hard disk drive (HDD) (hereinafter, “HDD device”) is used (see Japanese Patent Application Laid-Open NO. 2004-30837).
In recent years, an auxiliary storage device including, as a recording medium, a nonvolatile semiconductor memory such as a NAND flash memory (so-called solid state disk, hereinafter, “SSD device”) is mounted on a computer instead of the HDD device. In the SSD device, a plurality of NAND flash memories (hereinafter, “NANDs”) and a controller integrated circuit (IC) that controls the NANDs are mounted on a printed circuit board via electrodes (bumps). The SSD device is mounted on the computer after being housed in a housing generally having an external dimension and a shape same as those of the HDD device specified by a standard (e.g., a housing having a size and a shape same as those of a 2.5-inch HDD device). There are several kinds of standards concerning the housing of the HDD device according to the sizes of magnetic disks. In general, a housing such as that for the 2.5-inch HDD device is a box made of metal.
When the SSD device actually operates (when data is actually read and written), a controller generates heat because switching operation is repeatedly performed at high speed. A part of the heat generated from the controller is transmitted to the printed circuit board via the bump set in contact with the controller and further transmitted to the NANDs via a wiring pattern on the printed circuit board the bumps set in contact with the NANDs. In an operation principle, under a high-temperature environment, the NANDs tend to unsteady operate because leak current increases. Therefore, operation guarantee temperature for the NANDs is set low compared with other kinds of ICs. For example, whereas the operation guarantee temperature of the NANDs is about 85° C., the operation guarantee temperature of the other kinds of ICs is about 100° C.
Therefore, in the SSD device, it is necessary to cool the controller to suppress the transmission of the heat from the controller to the NANDs. In the case of the HDD device including a magnetic disk as a recording medium, because the controller and the magnetic disk are arranged separately from each other, the heat generated from the controller does not affect a mechanical section and the like of the magnetic disk. Therefore, it can be said that this problem is peculiar to the SSD device.
As a structure for cooling the controller in the SSD device, it is conceivable to interpose a heat radiation sheet between the controller and a bottom housing. Even if the heat radiation sheet is interposed between the controller and the bottom housing, the entire heat generated from the controller is not always transmitted to the bottom housing. However, a part of the heat is transmitted to the bottom housing via the heat radiation sheet. Consequently, a heat quantity transmitted to the NANDs is reduced to maintain the temperature of the NAND not to exceed the operation guarantee temperature.
According to the improvement of the performance of the SSD device and the computer mounted with the SSD, a heat value during actual operation of the controller tends to increase. For example, a data transfer rate of the SSD in the past is 100 MByte/sec for readout and 40 MByte/sec for writing. Currently, the data transfer rate is improved to 240 MByte/sec for readout and 200 MByte/sec for writing. Therefore, even if the heat radiation sheet is arranged between the controller and the bottom housing, it is difficult to sufficiently radiate the heat generated from the controller. However, an SSD device that takes measures against this problem is not realized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a diagram of the configuration of an SSD device and the configuration of a lower surface of a printed circuit board according to a first embodiment;

FIG. 1B is a diagram of the configuration on the lower surface side of the printed circuit board of the SSD device according to the first embodiment;

FIG. 2 is a plan view of the internal structure of the SSD device according to the first embodiment;

FIG. 3A is a partially enlarged perspective view of an interference section of the printed circuit board in a state in which a screw is not inserted into a screw hole;

FIG. 3B is a partially enlarged perspective view of the interference section of the printed circuit board in a state in which the screw is inserted into the screw hole from a side;

FIG. 4 is a partially enlarged plan view of the periphery of the interference section in a circuit pattern;

FIG. 5A is an arrow sectional view taken along line VA, VB-VA, VB shown in FIG. 4 of a printed circuit board used in a module-type semiconductor storage device;

FIG. 5B is an arrow sectional view taken along line VA, VB-VA, VB shown in FIG. 4 of a printed circuit board used in a box-type semiconductor storage device;

FIG. 6 is a plan view of a sheet-like substrate;

FIG. 7 is a block diagram of the schematic configuration of a PC board processing apparatus;

FIG. 8 is a flowchart for explaining a PC board processing process;

FIG. 9 is a diagram of the configuration of a template including through-holes in places corresponding to a controller and NANDs;

FIG. 10 is a diagram of a state in which a gel member of a room temperature curing type before curing is injected into a predetermined position in a bottom housing;

FIG. 11 is diagram of a state after completion of assembly of an SSD apparatus including a semiconductor memory device;

FIG. 12 is a diagram of the configuration of an SSD device using a radiation sheet integrally formed to cover a radiating region containing the controller and NANDs;

FIG. 13 is a diagram of a model of a parallel flat capacitor formed by a printed circuit board and a bottom housing;

FIG. 14 is a graph of an EMI characteristic of an SSD device including individual heat radiation sheets;

FIG. 15 is a graph of an EMI characteristics of an SSD device using a radiation sheet integrally formed to cover the radiating region containing the controller and NANDs;

FIG. 16 is a diagram of an example in which one heat radiation sheet is arranged for each of a plurality of cooling targets;

FIG. 17 is a diagram of the configuration of an SSD device according to a second embodiment;

FIG. 18 is a perspective view of heat radiation sheets according to a third embodiment;

FIG. 19 is a diagram of the configuration of an SSD device including a printed circuit board mounted with NANDs on both sides thereof and the configuration of a lower surface of the printed circuit board mounted with the NANDs on both the sides;

FIGS. 20A and 20B are diagrams illustrating the printed circuit board of the SSD device according to a fourth embodiment;

FIG. 21A is a diagram illustrating temperature measurement results when a SSD device according to the fourth embodiment is caused to continuously write data at the transfer rate of 192 MB/sec;

FIG. 21B is a diagram illustrating temperature measurement locations on each component mounted on a printed circuit board; and

FIG. 22 is a diagram illustrating temperature differences between each device mounted on the printed circuit board and the housing and maximum temperatures of devices when the housing temperature is assumed to be 70° C.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor storage device includes: a printed circuit board mounted on with, one surface, respectively via a plurality of bumps, a plurality of first nonvolatile semiconductor memories and a controller that controls reading of data from and writing of data in the first nonvolatile semiconductor memories; a housing that is formed of a conductive material and houses the printed circuit board; and a first heat radiation member that is interposed between a surface of the housing opposed to one surface of the printed circuit board and the controller and first nonvolatile semiconductor memories and thermally connects the controller and first nonvolatile semiconductor memories and the housing. The coupling capacitance in a state in which the first radiation member is arranged between a first capacitor formed by the surface of the housing opposed to one surface of the printed circuit board and the printed circuit board is smaller than coupling capacitance in a state in which an integrally formed object having a relative dielectric constant of 5.8 is arranged between the first capacitor to cover a first radiating region containing the controller and the first nonvolatile semiconductor memories.
Exemplary embodiments of semiconductor storage device and method of manufacturing the same will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments.

First embodiment

FIG. 1A is a disassembled perspective view of the configuration of an SSD device according to a first embodiment. FIG. 1B is a perspective view of the configuration on a lower surface side of a printed circuit board 3. FIG. 2 is a plan view of the internal structure of the SSD device according to the first embodiment. The SSD device according to this embodiment includes the printed circuit board 3 mounted with, on the lower surface side, eight NANDs 5 as first nonvolatile semiconductor memories and a controller 6. The printed circuit board 3 is housed in a housing formed by a top cover 1 and a bottom housing 9. The top cover 1 and the bottom housing 9 are formed of a metal material such as aluminum or iron.
The top cover 1 and the bottom housing 9 are coupled by cover fixing screws 2 to form a housing having a substantial hexahedron shape opened on one side. The printed circuit board 3 is screwed to the bottom housing 9 by fixing screws 8 in a state in which heat radiation sheets 10 (first heat radiation members) are interposed between the controller 6 and NANDs 5 and the bottom housing 9. A connector 4 is arranged at one end of the printed circuit board 3. The connector 4 is an interface that connects a host apparatus such as a computer and the SSD device. A shape and the like of the connector 4 are decided to conform to, for example, a serial advanced technology attachment (SATA) standard as a connection interface standard. The connector 4 is exposed to the outside of the housing in an opened surface of the housing. The SSD device is connected to the computer as the host apparatus that is an apparatus on which the SSD is mounted. In the following explanation, the printed circuit board 3 mounted with the connector 4, the NANDs 5, and the controller 6 is also referred to as semiconductor memory device 50. The SSD device according to this embodiment is a box-type semiconductor storage device in which the semiconductor memory device 50 is housed in a housing of a 2.5-inch type same as the housing of the HDD device.
Each of the heat radiation sheets 10 is formed to have flexibility with a material containing silicone resin and ceramics filler. Each of the heat radiation sheets 10 is pressed by the controller 6, the NAND 5, and the bottom housing 9 mounted on the printed circuit board 3 and closely attached to both of the printed circuit board 3 and the controller 6, the NAND 5, and the bottom housing 9. Consequently, the controller 6, the NAND 5, and the bottom housing 9 are thermally connected. An SDRAM 7 has high heat resistance. No deficiency occurs even if heat from the controller 6 is transited to the SDRAM 7. Therefore, the heat radiation sheet 10 is not arranged between the SDRAM 7 and the bottom housing 9. The heat radiation sheet 10 has a size for realizing a heat radiation effect sufficient for preventing the temperature of the controller 6 and the NAND 5 from rising to be equal to or higher than a design value (e.g., 85° C. as the operation guarantee temperature). As explained later, the first heat radiation member is not limited to a heat radiation sheet molded in a sheet shape and can be a gel member. However, in an example explained below, the heat radiation sheet is used.
The printed circuit board 3 has a multilayer structure formed by superimposing synthetic resin. In this embodiment, the printed circuit board 3 has an eight-layer structure. On the printed circuit board 3, a circuit pattern 3 a (not shown in FIG. 1A) is formed in various shapes on the surfaces or the insides of the layers formed of the synthetic resin. The NANDs 5, the controller 6, and the connector 4 mounted on the printed circuit board 3 are electrically connected via the circuit pattern 3 a formed on the printed circuit board 3.
In the SSD device according to this embodiment as the box-type semiconductor storage device, in the semiconductor memory device 50, as shown in FIG. 2, a center axis AX thereof is arranged to be shifted with respect to a center axis BX of the bottom housing 9. This is because the position of the connector 4 with respect to the housing is decided by a standard such as serial ATA revision 2.6. Because the center axis AX and the center axis BX are shifted from each other, one side of the printed circuit board 3 is set close to a wall surface of the housing.
FIG. 3A is a partially enlarged perspective view of an interference section 3 b of the printed circuit board 3 in a state in which a screw 24 is not inserted into a screw hole 9 a. FIG. 3B is a partially enlarged perspective view of the interference section 3 b of the printed circuit board 3 in a state in which the screw 24 is inserted into the hole 9 a from a side. When the SSD device is fixed to the host apparatus such as the computer, the fixing screw 24 (housing fixing means) is inserted from the side or the bottom of the bottom housing 9. To insert the screw 24, screw holes 9 a are respectively formed on the side and the bottom.
The screw 24 inserted into the screw hole 9 a on a direction side to which the center axis AX of the semiconductor memory device 50 is shifted interferes with a part (the interference section 3 b) of the printed circuit board 3 set close to the wall surface of the housing.
In the printed circuit board 3 used in the SSD device according to this embodiment, the interference section 3 b is cut out to form a cutout 3 c. Therefore, the screw 24 and the printed circuit board 3 can be actually prevented from interfering with each other. Therefore, the printed circuit board 3 can be prevented from being broken or bent by interference with the screw 24. Specifically, the cutout 3 c is formed near the connector 4 and on one side of the printed circuit board 3 that is close to the wall surface of the housing when the semiconductor memory device 50 is housed in the housing.
The printed circuit board 3 can also be used in a module-type semiconductor storage device in which the semiconductor memory device 50 is used without being housed in a housing or the like to conform to the MO-297 standard set up by the Joint Electron Device Engineering Council (JEDEC).
In the semiconductor memory device 50 for the module-type semiconductor device and the semiconductor memory device 50 for the box-type semiconductor storage device, a part of a shape of the printed circuit board 3 included in the semiconductor memory device 50 is different. Specifically, a part of the printed circuit board 3 of the semiconductor memory device 50 for the box-type semiconductor storage device is cut out to form the cutout 3 c.
An external dimension and the like of the module-type semiconductor storage device are specified by, for example, the MO-297 standard of the JEDEC. In the module-type semiconductor storage device, because the semiconductor memory device 50 is used without being housed in the housing, an external dimension and the like of the semiconductor memory device 50 itself are specified. Consequently, an external dimension and the like of the printed circuit board 3 included in the semiconductor memory device 50 are also specified.
FIG. 4 is a partial enlarged plan view of the periphery of the interference section 3 b. The MO-297 standard of the JEDEC specifies that, as shown in FIG. 4, a hole 3 d is provided in a section equivalent to the cutout 3 c. Therefore, it is difficult to form the cutout 3 c in the printed circuit board 3 in the module-type semiconductor storage device. However, when the SSD device is used as the module-type semiconductor storage device, because the semiconductor memory device 50 is not housed in the housing, interference with a screw does not pose a problem even when the cutout 3 c is not formed. The hole 3 d provided in the section equivalent to the cutout 3 c is used, for example, when the SSD device as the module-type semiconductor storage device is fixed to the host apparatus such as the computer by using a screw. A hole 3 e formed near the hole 3 d is used when the semiconductor memory device 50 as the box-type semiconductor storage device is fixed to the housing (the bottom housing 9).
As explained above, the printed circuit board 3 is also used when the SSD device is configured as the module-type semiconductor storage device. Therefore, a discriminating section 14 is formed as shown in FIG. 2. The discriminating section 14 is formed to discriminate whether the printed circuit board 13 is used in the module-type semiconductor storage device or used in the box-type semiconductor storage device. Information necessary for manufacturing such as lot numbers of components mounted on the printed circuit board 3 can also be managed by using the discriminating section 14. The discriminating section 14 is, for example, a two-dimensional code printed to be readable from the surface of the printed circuit board 3. The discriminating section 14 is printed by a marker or the like before the NANDs 5 and the like are mounted. The discriminating section 14 is formed to avoid positions where the NANDs 5 and the like are mounted. Therefore, the discriminating section 14 is readable even after the NANDs 5 and the like are mounted. The discriminating section 14 only has to be able to discriminate whether the semiconductor memory device 50 is used as the module-type semiconductor memory or used as the box-type semiconductor storage device. The discriminating section 14 is not limited to the two-dimensional code. For example, the discriminating section 14 can be a barcode or can be an IC chip. The discriminating section 14 can be a difference of a shape such as unevenness formed on the printed circuit board 3. The discriminating section 14 can be formed in a place other than a position shown in the figure. For example, the discriminating section 14 can be printed on the surface of each of devices such as the NANDs 5.
The configuration of the circuit pattern 3 a formed on the printed circuit board 3 is explained below. FIG. 5A is an arrow sectional view taken along line VA, VB-VA, VB shown in FIG. 4 of the printed circuit board 3 used in the module-type semiconductor storage device. FIG. 5B is an arrow sectional view taken along line VA, VB-VA, VB shown in FIG. 4 of the printed circuit board 3 used in the box-type semiconductor storage device. A conductive metal material, for example, copper is used for the circuit pattern 3 a. The circuit pattern 3 a is formed in substantially the entire region in plan view of the printed circuit board 3. However, as shown in FIG. 4, the circuit pattern 3 a is formed to avoid the interference section 3 b. A space (a resin region where the circuit pattern 3 a is not formed) Y is provided between a cut line in cutting out the interference section 3 b (a formation line of the cutout 3 c) and the circuit pattern 3 a. In this embodiment, Y is set to 0.5 millimeter. In the semiconductor memory device 50, in some case, a screw inserted into the hole 3 d provided in the section equivalent to the cutout 3 c and the circuit pattern 3 a are set in contact with each other and grounded. By suppressing the space Y to a predetermined distance, the head of the screw and the circuit pattern 3 a can be set in contact with each other and grounded.
The circuit pattern 3 a is formed in other layers different from the layer shown in FIG. 4. Only an example of the circuit pattern 3 a is shown in FIG. 4. In all the layers different from the layer shown in FIG. 4, the circuit pattern 3 a is formed to avoid the interference section 3 b and the space Y is provided. The devices such as the NANDs 5 are not arranged in the interference section 3 b.
As shown in FIG. 5B, because the predetermined space Y is provided between the cut line in cutting out the interference section 3 b and the circuit pattern 3 a, the circuit pattern 3 a is not exposed at an edge 3 f when the interference section 3 b is cut out.
FIG. 6 is a plan view of a sheet-like substrate 19. The sheet-like substrate 19 includes printed circuit boards 3 and a peripheral section 16. The peripheral section 16 is provided to surround the printed circuit boards 3 and coupled to the printed circuit boards 3 via coupling sections 18. The peripheral section 16 surrounds the printed circuit boards 3 having unevenness in an external shape thereof and forms an external shape of the sheet-like substrate 19 in a substantially square shape. Consequently, handleability of the printed circuit boards 3 in mounting the NANDs 5 is improved.
The NANDs 5 and controllers 6 are mounted on the sections of the printed circuit boards 3 in a state of the sheet-like substrate 19 to which the peripheral section 16 is coupled. The peripheral section 16 can be separated to obtain the semiconductor memory device 50 from the sheet-like substrate 19 by cutting off the coupling sections 18 using a drill of a divider. Cutouts 3 c of the printed circuit boards 3 are formed when the coupling sections 18 are cut off. In this embodiment, four semiconductor memory devices 50 can be obtained from one sheet-like substrate 19 by separating the peripheral section 16 from the sheet-like substrate 19 mounted with the NANDs 5 and the controllers 6. The number of semiconductor memory devices 50 that can be obtained from the one sheet-like substrate 19 is not limited to four. A larger number of semiconductor memory devices 50 can be obtained from the one sheet-like substrate 19 by using a larger sheet-like substrate 19. One semiconductor memory device 50 can be obtained from the one sheet-like substrate 19.
FIG. 7 is a block diagram of the schematic configuration of a PC board processing apparatus (manufacturing apparatus). A PC board processing apparatus 30 includes a drill 31, a reading unit 33, and a control unit 34. The drill 31 functions as a cutting unit that cuts off the coupling sections 18 of the sheet-like substrate 19 and cuts out the interference section 3 b. The reading unit 33 reads the discriminating section 14 and discriminates whether the printed circuit board 13 is used in the module-type semiconductor storage device or used in the box-type semiconductor storage device. The control unit 34 automatically reads processing data and controls the drill 31 based on a discrimination result of the reading unit 33 to cut off the coupling sections 18 and cut out the interference section 3 b.
FIG. 8 is a flowchart for explaining a PC board processing process. First, devices such as the NANDs 5, the controllers 6, and connectors 4 are mounted on the sheet-like substrate 19 (step S1). Subsequently, discriminating sections 14 are read and processing data is automatically read based on a discrimination result (step S2). When it is discriminated that the printed circuit boards 3 are used in the box-type semiconductor storage device (“Yes” at step S3), the coupling sections 18 are cut off and interference sections 3 b are cutout by the drill 31 to form the cutouts 3 c (step S4). Consequently, the four semiconductor memory devices 50 in which the cutouts 3 c are formed are obtained from the one sheet-like substrate 19.
When it is discriminated at step S3 that the printed circuit boards 3 are not used in the box-type semiconductor storage device but is used in the module-type semiconductor storage device (“No” at step S3), the cutouts 3 c are not formed and the coupling sections 18 are cut off (step S5). Consequently, the four semiconductor memory devices 50 in which the cutouts 3 c are not formed are obtained from the one sheet-like substrate 19. The step of forming the cutouts 3 c and the step of cutting off the coupling sections 18 can be separately performed and whichever of the steps can be performed earlier.
As explained above, the circuit pattern 3 a is formed to avoid the interference section 3 b of the printed circuit board 3 and the devices such as the NANDs 5 are arranged to avoid the interference section 3 b. Therefore, the arrangement of the circuit pattern 3 a and the devices of the printed circuit board 3 can be used in common irrespectively of whether the semiconductor memory device 50 is used in the module-type semiconductor storage device or used in the box-type semiconductor storage device. The arrangement of the circuit pattern 3 a and the devices of the printed circuit board 3 can be used in common irrespectively of presence or absence of the cutout 3 c. This makes it possible to suppress design cost for the arrangement of the circuit pattern 3 a and the devices. Because mounting evaluation and performance evaluation can be used in common, it is also possible to suppress evaluation cost. Because the devices to be mounted can be used in common, it is also possible to suppress selection cost for the devices. When the semiconductor memory device 50 is used in the module-type semiconductor storage device, because the cutout 3 c is not formed, it is possible to satisfy the formation of a hole requested by the MO-297 standard. On the other hand, when the semiconductor memory device 50 is used in the box-type semiconductor storage device, it is possible to prevent interference between the screw and the printed circuit board 3 by forming the cutout 3 c.
Because the circuit pattern 3 a is formed to avoid the interference section 3 b, when the cutout 3 c is formed, the drill 31 does not have to be caused to cut off the circuit pattern 3 a. Consequently, when the cutout 3 c is formed, it is possible to cause the drill 31 to cut off only resin. Therefore, the life of the drill 31 can be extended. As shown in FIG. 5B, the circuit pattern 3 a is not exposed in the edge when the interference section 3 b is cut out. Therefore, a metal burr less easily occurs at the edge. This makes it possible to prevent the metal burr from short-circuiting the circuit patterns 3 a formed among the layers of the printed circuit board 3. It is also possible to prevent the metal burr from separating from the printed circuit board 3 to cause short-circuit and the like in other places.
In the above explanation, when the peripheral section is separated from the sheet-like substrate 19, the interference section 3 b is cut out to form the cutout 3 c. However, the formation of the cutout 3 c is not limited to this. For example, it is also possible to store the semiconductor memory device 50 as the module-type semiconductor storage device without forming the cutout 3 c when the peripheral section is separated and, when the semiconductor memory device 50 is used in the box-type semiconductor storage device a posteriori, cut out the interference section 3 b to form the cutout 3 c.
A procedure for assembling the SSD device including the semiconductor memory device 50 is explained below. First, as shown in FIG. 9, a template 20 including through-holes 20 a in places corresponding to the controller 6 and the NANDs 5 is arranged in a predetermined position in the bottom housing 9. The heat radiation sheets 10 are stuck to the inner surface of the bottom housing 9 via the through holes 20 a. After the heat radiation sheets 10 are stuck, the template 20 is removed from the bottom housing 9. The semiconductor memory device 50 is mounted on the template 20 and screwed to the template 20 by the fixing screws 8. (In the figure, a procedure for sticking heat radiation sheets using a template is shown. However, the heat radiation sheets can be directly stuck to a package of a corresponding IC without using the template. However, in that case, it is necessary to contrive means for preventing mounted components other than the IC from being damaged during sticking work.) The heat radiation sheets 10 are respectively interposed between the controller 6 and NANDs 5 and the bottom housing 9 through such a procedure, whereby setting workability for the heat radiation sheets 10 is improved. Because the printed circuit board 3 is assembled to cover the heat radiation sheets 10, the heat radiation sheets 10 do not fall from top surfaces (surfaces opposed to the bottom housing 9) of the controller 6 and the NANDs 5 during assembly work. Thereafter, the top cover 1 is placed over the bottom housing 9 and the cover fixing screws 2 are tightened, whereby the assembly of the SSD device is completed.
An assembling procedure for an SSD apparatus substituting a gel member for the heat radiation sheet as the first heat radiation member is explained below. First, as shown in FIG. 10, a gel member 22 of a room temperature curing type in a state of a fluid is injected into a predetermined position in the bottom housing 9. When the gel member 22 is injected, an application amount of the gel member 22 is controlled by a dispenser 23 or the like. Subsequently, the gel member 22 is left intact in a room temperature state and cured (set). Thereafter, the semiconductor device 50 is fixed to the bottom housing 9. The NAND 5 and the controller 6 are brought into contact with the gel member 22. Thereafter, the top cover 1 and the bottom housing 9 are laid one on top of the other and fastened by fixing screws. Consequently, as shown in FIG. 11, the assembly of the SSD apparatus is completed as shown in FIG. 11.
In this case, at a point when the semiconductor memory device 50 is housed in the bottom housing 9, a leak of the gel member 22 already less easily occurs. Extrusion and a leak of the gel member 22 do not easily occur. Therefore, it is easy to automate an injection process for the gel member 22 using an industrial robot or the like. It is possible to realize a reduction in manufacturing cost.
If the gel member 22 has viscosity and surface tension enough for not spreading exceeding a predetermined area (e.g., an area opposed to the NAND 5 and the controller 6) from application to curing of the gel member 22, it is also possible to house the semiconductor memory device 50 in the bottom housing 9 before the curing of the gel member 22. In other words, even if the gel member 22 is compressed by the NAND 5, the controller 6, and the bottom housing 9 when the semiconductor memory device 50 is housed in the bottom housing 9, an application amount of the gel member 22 only has to be controlled to an amount enough for maintaining a shape of the gel member 22 with the surface tension and the viscosity. When a certain length of time elapses after the semiconductor memory device 50 is housed in the bottom housing 9, the gel member 22 is cured. Therefore, even when the SSD apparatus is used as a product, it is possible to suppress a leak of the gel member 22.
In general, the gel member is more inexpensive than the heat radiation sheet. Therefore, if the gel member is used, it is possible to realize a further reduction in manufacturing cost for the SSD apparatus.
A reason for individualizing the heat radiation sheets 10 in this embodiment is explained below.
As measures against heat of the NANDs, it is conceivable to thermally connect the NANDs and the bottom housing via the heat radiation sheets. As an example of this structure, there is a structure in which a heat radiation sheet 11 having a minimum rectangular shape that covers a radiating region (first radiating region) containing a plurality of the NANDs 5 and the controller 6 is interposed between the controller 6 and NANDs 5 and the bottom housing 9. FIG. 12 is a disassembled perspective view of an SSD device having a configuration for covering the region containing the controller 6 and the NANDs 5 with one integrally formed heat radiation sheet 11. The SSD device is the same as the SSD device shown in FIG. 1A except that the heat radiation sheet 11 has the minimum rectangular shape for covering the controller 6 and the NANDs 5. The configuration of the lower surface of the printed circuit board 3 of the semiconductor memory device 50 is the same as that shown in FIG. 1B. The SSD device shown in FIG. 12 is explained below in comparison with the SSD device according to the first embodiment shown in FIG. 1A.
The printed circuit board 3 of the SSD device is arranged substantially parallel to the bottom housing 9. Therefore, it can be regarded that a parallel flat capacitor is formed by the printed circuit board 3 and the bottom housing 9. A model of the parallel flat capacitor formed by the printed circuit board 3 and the bottom housing 9 is shown in FIG. 13. The printed circuit board 3 and the bottom housing 9 are parallel flat plates and coupling capacitance (capacitance) is generated. Because the heat radiation sheets 10 or the heat radiation sheet 11 is arranged between the parallel flat plates, the coupling capacitance fluctuates according to an area of a region where the heat radiation sheets 10 or the heat radiation sheet 11 is present and a relative dielectric constant of the heat radiation sheets 10 or the heat radiation sheet 11.
The printed circuit board 3 receives the supply of electric power from the computer connected via the connector 4 and operates as an SSD. High-frequency noise occurs from the NANDs 5 and the controller 6 because of an internal operation clock and read/write data. The noise propagates to the bottom housing 9 according to capacitive coupling of the printed circuit board 3 and the bottom housing 9.
The bottom housing 9 resonates with respect to an electromagnetic wave having a frequency (1/n) times (n=1, 2, 4, 8, . . . ) as high as a frequency with a dimension in a longitudinal, lateral, or diagonal direction of the bottom housing 9 set as one wavelength and functions as an efficient antenna. For example, if the long side, the short side, and the diagonal of the bottom housing 9 are 0.1 meter, 0.06985 meter, and 0.122 meter, respectively, in the long side direction, electromagnetic waves having frequencies 3 GHz, 1.5 GHz, 0.75 GHz, 0.375 GHz, and the like resonate. In the short side direction, electromagnetic waves having frequencies 4.295 GHz, 2.147 GHz, 1.074 GHz, 0.537 GHz, and the like resonate. In the diagonal direction, electromagnetic waves having frequencies 2.459 GHz, 1.230 GHz, 0.615 GHz, 0.307 GHz, and the like resonate. The electromagnetic waves having these frequencies are radiated into the air via the bottom housing 9 as an antenna.
In the example explained above, resonant frequencies are present over substantially all bands of 300 MHz to 1 GHz included as measurement ranges in electromagnetic interference (EMI) standards of countries and regions specified in the CE, the Voluntary Control Council for Interference by information technology equipment (VCCI), the Federal Communications Commission (FCC), and the like. However, because of a difference in dimensions in the longitudinal, lateral, and diagonal directions of the bottom housing 9, the resonant frequency of 0.537 GHz at ⅛ wavelength in the short side direction, the resonant frequency of 0.615 GHz at ¼ wavelength in the diagonal direction, and the resonant frequency of 0.750 GHz at ¼ wavelength in the long side direction have a small frequency difference of a resonant frequency. When operation speed of the SSD device is increased, noise corresponding to the bands tends to occur and resonate with the bottom housing 9. Therefore, unnecessary radiation caused by the bottom housing 9 functioning as an antenna becomes more conspicuous according to the increase in the operation speed of the SSD device.
As explained above, the arrangement of the heat radiation sheets 10 or the heat radiation sheet 11 to cool the controller 6 and the NANDs 5 is nothing but insertion of an object having a relative dielectric constant (a relative dielectric constant of a material of the heat radiation sheets 10 or the heat radiation sheet 11) between the parallel flat plates of the parallel flat capacitor (between the printed circuit board 3 and the bottom housing 9). Therefore, when the heat radiation sheets 10 or the heat radiation sheet 11 is arranged, the coupling capacitance of the parallel flat capacitor increases compared with coupling capacitance in a state in which the printed circuit board 3 and the bottom housing 9 are simply opposed to each other. The bottom housing 9 easily functions as an antenna. When the heat radiation sheet 11 integrally formed to cover the radiating region containing the controller 6 and the NANDs 5 is set, the coupling capacitance of the capacitor increases more than the coupling capacitance of the capacitor obtained when the individual heat radiation sheets 10 are arranged. Therefore, the heat radiation sheet 11 integrally formed to cover the radiating region containing the controller 6 and the NANDs 5 is disadvantageous in terms of a reduction in unnecessary radiation caused by the bottom housing 9 functioning as the antenna.
A relative dielectric constant of a material of an existing heat radiation sheet is about 5.8. When the heat radiation sheet is integrally formed and arranged to cover the radiating region containing the controller 6 and the NANDs 5, an EMI characteristic of the SSD device can conform to the EMI standard at the very limit. It is likely that the EMI characteristic does not conform to the standard depending on shield performance of a computer as an apparatus on which the SSD device is mounted. If the operation speed of the SSD device is further increased, it is more highly likely that the EMI characteristic does not conform to the EMI standard. When a margin is given to the EMI standard and stricter specifications are required, it is likely that the required specifications cannot be met even by the current operation speed.
In this embodiment, with the above points taken into account, the individual heat radiation sheets 10 are adopted to suppress an increase in the coupling capacitance of the parallel flat capacitor. Because the heat radiation sheets 10 are individualized, a total of areas occupied by the heat radiation sheets 10 is small compared with an area of the heat radiation sheet 11 integrally formed to cover the radiating region containing the controller 6 and the NANDs 5. Therefore, the coupling capacitance of the capacitor decreases, impedance from a noise source to an antenna side increases, a transmission level decreases, and the unnecessary radiation caused by the bottom housing 9 functioning as the antenna is reduced.
A difference between the use of the individual heat radiation sheets 10 and the use of the heat radiation sheet 11 integrally formed to cover the radiating region containing the controller 6 and the NANDs 5 is explained more in detail below with reference to specific numerical values as examples. However, the present invention is not limited to the numerical values referred to as the examples.
Each of the individual heat radiation sheets 10 has longitudinal and lateral length of 0.01 meter and thickness of 0.003 meter. The printed circuit board 3 has longitudinal length of 0.063 meter and lateral length of 0.0865 meter. The bottom housing 9 has a long side of 0.1 meter, a short side of 0.06985 meter, and a diagonal of 0.122 meter.
A space between the printed circuit board 3 and the bottom housing 9 is 0.0044 meter. Mounting height of the controller 6 and the NANDs 5 is 0.0014 meter. Therefore, a space between the controller 6 and NANDs 5 and the bottom housing 9 is 0.003 meter.
The heat radiation sheet 11 integrally formed to cover the radiating region containing the controller 6 and the NANDs 5 has longitudinal length of 0.05 meter, lateral length of 0.07 meter, and thickness of 0.003 meter.
An area of each of the individual heat radiation sheet 10 is 0.0001 m²and an area of the heat radiation sheet 11 integrally formed to cover the radiating region containing the controller 6 and the NANDs 5 is 0.0035 m². Nine individual heat radiation sheets 10 are used in total to correspond to the controller 6 and the NANDs 5, respectively. Therefore, an area ratio of a total area S₁of the individual heat radiation sheet 10 and an area S₂of the heat radiation sheet 11 integrally formed to cover the radiating region containing the controller 6 and the NANDs 5 is S₁:S₂=0.0009:0.0035=1:3.9.
Coupling capacitance C of the parallel flat capacitor is represented by the following Formula (1):
C=ε ₀ ×ε×S ₃ ÷d (1)
In Formula (1), ε₀represents a dielectric constant (F/m) in the vacuum, ε represents a relative dielectric constant of an object present between the parallel flat plates, S₃represents an area (m²) of the parallel flat plates, and d represents a distance (m) between the parallel flat plates.
In the SSD device according to this embodiment, an area of the printed circuit board 3 smaller than the bottom housing 9 is the area of the parallel flat plates: S₃=0.063×0.0865=0.0054495 m². When the heat radiation sheets 10 or the heat radiation sheet 11 is present in a part between the parallel flat plates, the coupling capacitance of the capacitor is a sum of coupling capacitance of a region where the heat radiation sheets 10 or the heat radiation sheet 11 is present and coupling capacitance of a region where the heat radiation sheets 10 or the heat radiation sheet 11 is not present.
It is assumed that a relative dielectric constant of the air is approximated as 1. For simplification of explanation, it is assumed that a relative dielectric constant of electric components such as the controller 6 and the NANDs 5 is 1.
When the heat radiation sheets 10 or the heat radiation sheet 11 is not used, because only the air is present between the parallel flat plates, from Formula (1), coupling capacitance is 8.85419×10⁻¹²×1×0.0054495÷0.0044=1.10×10⁻¹²F=11.0 pF.
When the individual heat radiation sheets 10 are used, an area of a region where the heat radiation sheets 10 are present is 0.0009 m²and an area of a region where the heat radiation sheets 10 are not present is 0.0045495 m². From Formula (1), coupling capacitance of the region where the heat radiation sheets 10 are not present is 8.85419×10⁻¹²×1×0.0045495÷0.0044=9.16×10⁻¹²F=9.16 pF.
On the other hand, coupling capacitance of the region where the heat radiation sheets 10 are present is series coupling capacitance of coupling capacitance of sections of the heat radiation sheets and coupling capacitance of sections of the electronic components. Series coupling capacitance C_cof two capacitors C_Aand C_Bis represented by the following Formula (2):
1/C _c=(1/C _A)+(1/C _B) (2)
From formula (1), coupling capacitance of sections of the heat radiation sheets 10 is 8.85419×10⁻¹²×5.8×0.0009÷0.003=5.9×10 ⁻¹²=5.69 pF. From Formula (1), coupling capacitance of sections of the electronic components is 8.85419×10⁻¹²×1×0.0009÷0.0014=1.5×10 ⁻¹¹F=15.4 pF. Therefore, from Formula (2), coupling capacitance of the entire area where the heat radiation sheets 10 are present is 4.16 pF. Therefore, coupling capacitance of the entire capacitors is 9.16 pF+4.16 pF−13.32 pF.
When the heat radiation sheet 11 integrally formed to cover the radiating region containing the controller 6 and the NANDs 5 is used, an area of a region where the heat radiation sheet 11 is present is 0.0035 m²and an area of a region where the heat radiation sheet 11 is not present is 0.0019495 m². According to calculation same as the calculation performed when the individual heat radiation sheet 10 is used, coupling capacitance of the region where the heat radiation sheet 11 is not present is 3.92 pF and coupling capacitance of the region where the heat radiation sheet 11 is present is 16.2 pF. Therefore, coupling capacitance of the entire capacitors is 20.1 pF.
As a result, the coupling capacitance can be reduced by about 44% by using the individual heat radiation sheets 10 compared with the coupling capacitance obtained when the heat radiation sheet 11 integrally formed to cover the radiating region containing the controller 6 and the NANDs 5 is used.
An EMI characteristic of the SSD device including the individual heat radiation sheets 10 is shown in FIG. 14. An EMI characteristic of the SSD device including the heat radiation sheet 11 integrally formed to cover the radiating region containing the controller 6 and the NANDs 5 is shown in FIG. 15. Measurement results by a test method specified in the VCCI are shown in the figures. The computer is caused to operate in a state in which the SSD alone connected to the computer by an extension cable is set on the outside of the computer (originally, the computer is caused to operate in a state in which the SSD is incorporated in the computer as the apparatus on which the SSD is mounted). Intensity of an electromagnetic wave (unnecessary radiation) entering an antenna set in a place 10 meters apart from the computer is measured. A condition conforming to the VCCI standard is that the intensity is equal to or lower than 30 decibels in a band of 30 MHz to 230 MHz and is equal to or lower than 37 decibels in a band of 230 MHz to 1000 MHz. In the SSD device including the heat radiation sheet 11 integrally formed to cover the radiating region containing the controller 6 and the NANDs 5, the intensity of the unnecessary radiation is over the standard value near 700 MHz. On the other hand, in the SSD device including the individual heat radiation sheets 10, the intensity of the unnecessary radiation is reduced by about 16 decibels to be equal to or lower than the standard value near 700 MHz.
By using the individualized heat radiation sheets 10, the coupling capacitance of the capacitor is reduced and the unnecessary radiation caused by the bottom housing 9 functioning as the antenna is reduced. To realize, with the heat radiation sheet 11 integrally formed to cover the radiating region containing the controller 6 and the NANDs 5, coupling capacitance equivalent to that of the individual heat radiation sheets 10, it is necessary to form the heat radiation sheet 11 with a material having a relative dielectric constant of 1.586. However, in the present situation, it is difficult to form the heat radiation sheet 11 with such a material. In other words, by using the individualized heat radiation sheets 10, it is possible to reduce the coupling capacitance to a level that cannot be realized when the heat radiation sheet 11 integrally formed to cover the radiating region containing the controller 6 and the NANDs 5 is used and reduce the unnecessary radiation.
By individualizing the heat radiation sheet 10, it is also possible to reduce the weight of the SSD device. When the specific gravity of the heat radiation sheets 10 and 11 is set to 2.7, in the above example, a difference in an area is 0.0026 m²and the thickness of the sheet is 0.003 meter, a weight difference is about 21 grams. In other words, by using the individual heat radiation sheets 10, it is possible to reduce the weight by about 21 grams compared with the SSD device including the heat radiation sheet 11 integrally formed to cover the radiating region containing the controller 6 and the NANDs 5.
In the example of the configuration explained above, the individual heat radiation sheets 10 are respectively arranged in the controller 6 and the NANDs 5. However, as shown in FIG. 16, one heat radiation sheet can be arranged in each of a plurality of cooling targets. In FIG. 16, each of heat radiation sheets 10 a, 10 b, and 10 c covers three cooling targets (one controller 6 and eight NANDs 5). By adopting such a configuration, it is possible to reduce manhour of work for sticking the heat radiation sheets and improve assembly workability. As the number of cooling targets covered by one heat radiation sheet increases, the assembly workability is higher. On the other hand, the coupling capacitance of the capacitor increases because the heat radiation sheets are arranged in regions where cooling targets are not present. The unnecessary radiation caused by the bottom housing 9 functioning as the antenna increases. In this way, the assembly workability in arranging the heat radiation sheets and the EMI characteristic of the SSD device are in a tradeoff relation. Therefore, it is advisable to select the number of cooling targets covered by one radiation sheet according to required specifications.

Second Embodiment

FIG. 17 is a disassembled perspective view of the configuration of an SSD device according to a second embodiment. The configuration of the SSD device according to the second embodiment is the same as the configuration shown in FIG. 12. One heat radiation sheet 12 covers the controller 6 and the eight NANDs 5. The configuration of the lower surface of the printed circuit board 3 of the semiconductor memory device 50 is also the same as that in the first embodiment. However, in this embodiment, the relative dielectric constant of the heat radiation sheet 12 is 3.8, which is lower than that of the heat radiation sheets 10 in the first embodiment.
As it is evident from Formula (1), the coupling capacitance of the parallel flat capacitor is proportional to the relative dielectric constant of an object present between the parallel flat plates. It is assumed that dimensions of the heat radiation sheet 12 are the same as the dimensions of the heat radiation sheet 11 explained in the first embodiment and other conditions such as an area of the printed circuit board 3 and a space between the bottom housing 9 and the printed circuit board 3 are also the same. In this case, as the coupling capacitance of the parallel flat capacitor, according to Formulas (1) and (2), the coupling capacitance of a region where the heat radiation sheet 12 is not present is 3.92 pF and the coupling capacitance of a region where the heat radiation sheet 12 is present is 14.1 pF. Therefore, the coupling capacitance of the entire capacitor is 18.0 pF. Therefore, by applying a heat radiation sheet formed of a material having a low relative dielectric constant, it is possible to reduce the coupling capacitance of the capacitor formed by the printed circuit board and the bottom housing and reduce the unnecessary radiation caused by the bottom housing functioning as the antenna.

Third Embodiment

In an SSD device according to a third embodiment, as in the second embodiment, one heat radiation sheet covers a controller and eight NANDs. A perspective view of a heat radiation sheet 13 according to this embodiment is shown in FIG. 18. The heat radiation sheet 13 has a structure in which pieces 13 a corresponding to cooling targets and a tabular section 13 b including the pieces 13 a on the surface thereof are integrally molded. By reducing a thickness dimension of the tabular section 13 b, it is possible to suppress an increase in coupling capacitance due to the presence of the tabular section 13 b between the printed circuit board 3 and the bottom housing 9 compared with an increase in coupling capacitance due to arranging a heat radiation sheet integrally formed to cover the radiating region containing the controller 6 and the NANDs 5. Therefore, in this embodiment, the coupling capacitance of a capacitor can be reduced compared with that in the case of the heat radiation sheet is integrally formed to cover the radiating region containing the controller 6 and the NANDs 5. The heat radiation sheet 13 only has to be stuck once. Therefore, it is possible to realize both an EMI characteristic and assembly workability.

Fourth Embodiment

FIGS. 20A and 20B are diagrams illustrating the printed circuit board 3 of the SSD device according to the fourth embodiment. The SSD device according to the present embodiment has, like in the first embodiment, the connector 4, the NANDs 5, the controller 6, and the SDRAM 7 mounted on the printed circuit board 3. Also, the individually-segmented radiation sheets 10 are arranged on the controller 6 and the NANDs 5. In the present embodiment, however, the radiation sheets 10 are arranged on not all of the controller 6 and the NANDs 5, but a portion thereof. FIG. 20A illustrates a configuration in which six sheets of the radiation sheet 10 are arranged and FIG. 20B illustrates a configuration in which five sheets of the radiation sheet 10 are arranged. In both configurations, the radiation sheet 10 is not arranged on the NANDs 5 positioned at corners of a cluster in a substantial rectangular shape of the SDRAM 7, the controller 6, and the NANDs 5 arranged in a rectangular cluster.
The printed circuit board 3 has a temperature sensor IC 60 having a function to output temperature measurement results mounted thereon.
FIG. 21A is a diagram illustrating temperature measurement results (Celsius temperature) when an SSD device according to the present embodiment is caused to continuously write data at the transfer rate of 192 MB/sec at room temperature in an atmosphere of no wind. FIG. 21B is a diagram illustrating temperature measurement locations on each device mounted on the printed circuit board 3. No. 2 to No. 6 measurement locations in FIG. 21A are locations indicated by arrows of (2) to (6) in FIG. 21B. No. 1 measurement location in FIG. 21A is an atmosphere in which the SSD device is installed and No. 7 measurement location is a surface of the housing on the side of the controller 6. Temperature measurement results at each location when, as illustrated in FIG. 12, the SSD device is caused to continuously write data at 192 MB/sec by covering a substantially entire surface of the printed circuit board 3 with one radiation sheet, temperature measurement results at each location when the SSD device is caused to continuously write data at 189 MB/sec with no radiation sheet, and temperature measurement results at each location when the SSD device is caused to continuously write data at 192 MB/sec by arranging the radiation sheet 10 on all of the controller 6 and the NANDs 5 are illustrated for comparison. A thermocouple is used for temperature measurement. Further, measurement results by the temperature sensor IC 60 are also illustrated together with temperature measurement results at each location. Regarding each configuration in which a radiation sheet is provided, measurement results by the thermocouple on each device mounted on the printed circuit board 3 and measurement results by the temperature sensor IC 60 are values close to each other, which illustrates that measurement results by the temperature sensor IC 60 are reliable.
The temperature of the controller 6 is lower when the number of the radiation sheets 10 is six (6 pcs) than when the number of the radiation sheets 10 is five (5 pcs). The temperature of the controller 6 when the number of the radiation sheets 10 is nine (9 pcs) is approximately the same as the temperature of the controller 6 when the number of the radiation sheets 10 is six (6 pcs). The temperature of the NAND 5 is approximately the same when the number of the radiation sheets 10 is five and the number of the radiation sheets 10 is six. The temperature of the NAND 5 when the number of the radiation sheets 10 is nine is further lower than the temperature of the NAND 5 when the number of the radiation sheets 10 is six.
It is assumed here that the temperature of each device should be 85° C. or less when the temperature of the housing is set to 70° C. and an increase in temperature at each location will be calculated based on temperature measurement results illustrated in FIG. 21A. (Calculate temperature differences from the temperature of the housing) FIG. 22 is a diagram illustrating temperature differences between each device mounted on the printed circuit board 3 and the housing and maximum temperatures of devices when the housing temperature is assumed to be 70° C. In all configurations in which the number of the radiation sheets 10 is five, six, and nine, the maximum value of temperature difference between the housing and each device (the SDRAM 7, the controller 6, and the NAND 5) is less than 15° C. and thus, if the temperature of the housing is set to 70° C., the temperature of all devices is less than 85° C. so that it is possible to verify that requirements concerning the device temperature can be met.
The configuration in which the number of the radiation sheets 10 is five is lighter and costs less, but the temperature difference from the temperature of the housing is large. Though the configuration in which the number of the radiation sheets 10 is six is heavier than the configuration in which the number of the radiation sheets 10 is five, the temperature difference from the temperature of the housing becomes smaller. Thus, the number of the radiation sheets 10 can be decided as appropriate by considering the weight, cost, and the magnitude of temperature difference from the temperature of the housing within the range in which a product meets requirements concerning the device temperature. Therefore, heat dissipation performance can be ensured while reducing the weight and material costs by arranging the radiation sheets 10 on a portion of the controller 6 and the NANDs 5.
In the configuration explained as the example in the embodiments, the controller 6 and the NANDs 5 are mounted on the lower surface of the printed circuit board 3 and the heat radiation sheets 10, the heat radiation sheet 12, or the heat radiation sheet 13 is arranged between the printed circuit board 3 and the bottom housing 9. However, it goes without saying that the same effect can be obtained even when the controller 6 and the NANDs 5 are mounted on the upper surface of the printed circuit board 3 and a heat radiation sheet(s) is arranged between the printed circuit board 3 and the top cover 1.
In the configuration explained as the example in the embodiments, the NANDs 5 are mounted on only the lower surface of the printed circuit board 2. However, it is also possible to adopt a configuration in which the printed circuit board 3 mounted with the NANDs 5 on both the surfaces is used. FIG. 19 is a disassembled perspective view of the configuration of an SSD device including the printed circuit board 3 mounted with the NANDs 5 on both the surfaces. The configuration of the lower surface of the printed circuit board 3 of the semiconductor memory device 50 is the same as that shown in FIG. 1B. When the printed circuit board 3 mounted with the NANDs 5 on both the surfaces is used, individual heat radiation sheets 15 (second heat radiation members) same as the heat radiation sheets 10 in the first embodiment are arranged between the NANDs 5 as second nonvolatile semiconductor memories on the upper surface side of the printed circuit board 3 and the top cover 1. This makes it possible the coupling capacitance of a parallel flat capacitor formed by the printed circuit board 3 and the top cover 1 is smaller than the coupling capacitance when an integrally formed object having a relative dielectric constant of 5.8 is arranged between the capacitor to cover a radiating region (second radiating region) containing the second nonvolatile semiconductor memories on the upper surface side of the printed circuit board 3 and reduce unnecessary radiation caused by the top cover 1 functioning as an antenna. It goes without saying that the same effect can be obtained even if the heat radiation sheets 15 are the same as those in the second, third and fourth embodiments. It goes without saying that, like the first heat radiation member, the second heat radiation member can be a gel member.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the sprit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

Claims

1. A semiconductor memory device comprising:

a circuit board including a circuit pattern;

a nonvolatile semiconductor memory; and

a connector that is capable of being coupled with a host apparatus, wherein

the circuit board includes a first surface, a second surface located opposite to the first surface, a first end having the connector, a second end in which a cutout is formed, and a corner intersected with the first end and the second end,

the nonvolatile semiconductor memory is mounted on the first surface,

the semiconductor memory device is configured to be capable of being housed in a housing, the housing including a first side and a second side, the second side being adjacent to the first side, the housing including a coupling portion, the coupling portion being fixed to the host apparatus and located on the second side, the second side facing the second end,

the connector is configured to pass through the first side of the housing, the semiconductor memory device is configured to be capable of being housed in the housing in a position in which a center axis of the first surface along a direction in which the connector connects to the host apparatus is shifted toward the second side with respect to a center axis of the housing along the direction in which the connector connects to the host apparatus, and

the cutout is configured to be capable of holding, inside, a part of the coupling portion.

2. The semiconductor memory device according to claim 1, wherein

the coupling portion includes a screw and a screw hole through which the screw is inserted, the screw hole being formed through the second side.

3. The semiconductor memory device according to claim 2, wherein

the screw projects into the housing, wherein

the cutout is configured to avoid interference between the projecting screw and the circuit board.

4. The semiconductor memory device according to claim 3, wherein

a shape of the connector and a position of the connector with respect to the housing conform to a Serial Advanced Technology Attachment standard.

5. The semiconductor memory device according to claim 4, wherein

the housing is a 2.5-inch-type housing.

6. The semiconductor memory device according to claim 1, wherein

a predetermined space is formed between the cutout and the circuit pattern.

7. The semiconductor memory device according to claim 1, wherein

the circuit board has an eight-layer structure.

8. The semiconductor memory device according to claim 1, wherein

the circuit board has a substantially rectangular shape in plane view, wherein the first end is an end of longer dimension of the circuit board, wherein the second end is an end of shorter dimension of the circuit board.

9. The semiconductor memory device according to claim 1, wherein

the nonvolatile semiconductor memory is a NAND flash memory.

10. A box-type semiconductor memory device comprising:

a semiconductor memory including:

a circuit board including a circuit pattern;

a nonvolatile semiconductor memory; and

a connector that is capable of being coupled with a host apparatus; and

a housing that houses the semiconductor memory, wherein

the housing includes:

a first side; and

a second side, the second side being adjacent to the first side and on the second side, a coupling portion being fixed to the host apparatus,

the nonvolatile semiconductor memory is mounted on the first surface,

the connector is configured to pass through the first side of the housing,

the housing is configured to house the semiconductor memory in a position in which a center axis of the first surface along a direction in which the connector connects to the host apparatus is shifted toward the second side with respect to a center axis of the housing along the direction in which the connector connects to the host apparatus, and

the cutout is configured to hold inside, a part of the coupling portion.

11. The box-type semiconductor memory device according to claim 10, wherein

12. The box-type semiconductor memory device according to claim 11, wherein

the screw projects into the housing, and

13. The box-type semiconductor memory device according to claim 12, wherein

14. The box-type semiconductor memory device according to claim 13, wherein

the housing is a 2.5-inch-type housing.

15. The box-type semiconductor memory device according to claim 10, wherein

a predetermined space is formed between the cutout and the circuit pattern.

16. The box-type semiconductor memory device according to claim 10, wherein

the circuit board has an eight-layer structure.

17. The box-type semiconductor memory device according to claim 10, wherein

the circuit board has a substantially rectangular shape in plane view, wherein

the first end is an end of longer dimension of the circuit board, wherein

the second end is an end of shorter dimension of the circuit board.

18. The box-type semiconductor memory device according to claim 10, wherein

the nonvolatile semiconductor memory is a NAND flash memory.

19. A semiconductor memory device comprising:

a nonvolatile semiconductor memory; and

a circuit board including a first end having a connector and a second end in which a cutout portion is formed, wherein,

in a state in which the circuit board is mounted in a housing, the cutout portion is configured to be capable of holding, inside, at least a part of a fixing portion, the fixing portion being formed through a side of the housing, the fixing portion being fixed to an external host apparatus.

20. A memory system comprising:

a housing in which, through a side, a fixing portion being fixed to an external host apparatus is formed;

a nonvolatile semiconductor memory;

a connector that is capable of being coupled with the external host apparatus; and

a circuit board including a first end having the connector and a second end in which a cutout is formed, the cutout holding, inside, at least a part of the fixing portion.