US20130326873A1 - Method of fabricating multi-chip stack package structure having inner layer heat-dissipating board - Google Patents
Method of fabricating multi-chip stack package structure having inner layer heat-dissipating board Download PDFInfo
- Publication number
- US20130326873A1 US20130326873A1 US13/964,488 US201313964488A US2013326873A1 US 20130326873 A1 US20130326873 A1 US 20130326873A1 US 201313964488 A US201313964488 A US 201313964488A US 2013326873 A1 US2013326873 A1 US 2013326873A1
- Authority
- US
- United States
- Prior art keywords
- chip
- layer heat
- dissipating
- board
- oxidative
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49139—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Definitions
- This invention relates to an inner-layer heat-dissipating board, a multi-chip stack package structure having the inner-layer heat-dissipating board and a fabrication method thereof, and, more particularly, to a multi-chip stack package structure that provides a heat-dissipating path and increases the overall structural rigidity in an stacked structure and a fabrication method thereof.
- manufactures have developed a technique to dispose a plurality of semiconductor chips on a circuit board or a packing substrate, in order to increase the electrical functionality.
- a limited number of semiconductor chips can be disposed on a single packaging substrate, in that the packaging substrate does not have a large enough area.
- the planer disposition of the semiconductor chips on the packaging substrate is contradictory to the requirements of having a low-profile and compact size.
- a package structure has been designed to have a plurality of semiconductor chips stacked on one another.
- Such a package structure having the semiconductor chips stacked has a short transmission path, and characteristics of high efficiency, low power consumption and high functionality. Compared to the conventional package structure in which a plurality of semiconductor chips are disposed on a packaging substrate one by one, the package structure in which the semiconductor chips are stacked on one another may dramatically reduce the area of the packaging substrate.
- a multi-chip stack package structure is shown according to the prior art.
- a first semiconductor chip 11 is electrically connected through solder balls 110 to a packaging substrate 10 .
- a second semiconductor chip 12 is stacked on the first semiconductor chip 11 .
- a third semiconductor chip 13 is stacked on the second semiconductor chip 12 .
- the second semiconductor chip 12 , and the third semiconductor chip 13 are electrically connected to the packaging substrate 10 by solder wires 14 in a wire bonding manner.
- the second semiconductor chip 12 has to be smaller than the first semiconductor chip 11 and the third semiconductor chip 13 also has to be smaller than the second semiconductor chip 12 , such that the first and second semiconductor chips 11 and 12 may provide an area on top for the solder wires 14 to be bonded thereon.
- the solder wires 14 are in the shape of an arc, which also limits the reduction of the volume of the package structure.
- semiconductor manufacturers have developed a technique that vertically stack on a packaging substrate a plurality of semiconductor chips each of which has through-silicon vias (TSVs) in which a conductive material is filled, to constitute a semiconductor package structure.
- TSVs through-silicon vias
- the semiconductor package structure not only has good electrical functionality and enhanced electrical transmission efficiency, but can also meet the demands of high-end electronic products.
- FIG. 2A a multi-chip stack package structure with TSVs is shown.
- a plurality of TSV chips 21 are stacked on and electrically connected to a packaging substrate 20 by solder balls 201 .
- a semiconductor chip 22 is disposed on the very top one of the TSV chips 21 .
- a metal heat-dissipating sheet 23 is further adhered to a surface of the semiconductor chip 22 that is exposed to air, as shown in FIG. 2B .
- heat generated by the TSV chips 21 disposed in the middle of the stack may be dissipated through a conductive material such as the solder balls 201 and the TSVs to the metal heat-dissipating sheet 23 .
- the metal heat-dissipating sheet 23 that is disposed on the semiconductor chip 22 should not have an area much greater than that of the semiconductor chip 22 , or adherence and stress problems may occur, and the semiconductor chip 22 may be easily broken.
- the present invention provides an inner-layer heat-dissipating board, comprising: a metal board body; and a plurality of conductive through holes penetrating the metal board body, each of the conductive through holes including a plurality of nano wires and an oxidative block having a plurality of nano apertures filled with the nano wires.
- the metal board body may be made of aluminum, and the oxidative block may be made of aluminum oxide.
- the inner-layer heat-dissipating board may further include a plurality of first bumps disposed on end surfaces of the conductive through holes.
- Each of the nano wires may have a width less than or equal to 100 nano meters, or have an aspect ration greater than 1000.
- the nano wires may be made of metal, such as copper, nickel, platinum or gold.
- the present invention further provides a multi-chip stack package structure, comprising: an inner-layer heat-dissipating board including a metal board body and a plurality of conductive through holes penetrating the metal board body, each of the conductive through holes including a plurality of nano wires and an oxidative block having a plurality of nano apertures filled with the nano wires; a first chip disposed on a first surface of the inner-layer heat-dissipating board; and an electronic component disposed on a second surface of the inner-layer heat-dissipating board, the second surface opposing the first surface.
- the electronic component may be a circuit board or a second chip.
- the first chip and the electronic components have a plurality of second bumps disposed thereon electrically connected to the first bumps via the second bumps.
- the electronic component may be a second chip disposed on the inner-layer heat-dissipating board via a top surface thereof, and the multi-chip stack package structure further comprises a circuit board disposed under a bottom surface of the second chip.
- the multi-chip stack package structure may further comprise an underfill material formed between the inner-layer heat-dissipating board and the first chip, between the inner-layer heat-dissipating board and the second chip and between the circuit board and the second chip.
- Each of the nano wires may have a width less than or equal to 100 nano meters, or have an aspect ration greater than 1000.
- the nano wires may be made of metal, such as copper, nickel, platinum or gold.
- the present invention further provides a method of fabricating multi-chip stack package structure, comprising: providing an inner-layer heat-dissipating board including a metal board body and a plurality of conductive through holes penetrating the metal board body, each of the conductive through holes including a plurality of nano wires and an oxidative block having a plurality of nano apertures filled with the nano wires; and disposing a first chip on a first surface of the inner-layer heat-dissipating board, disposing an electronic component on a second surface of the inner-layer heat-dissipating board, the second surface opposing the first surface, and electrically connecting the first chip and the electronic component to the conductive through holes.
- the conductive through holes may be made by: forming on a surface of the metal board body a resist layer having a plurality of openings, allowing the openings to expose a portion of the metal board body; oxidizing the exposed portion of the metal board body to form oxidative blocks; patterning and etching the oxidative blocks to form the nano apertures in the oxidative blocks; forming the nano wires in the nano apertures; and exposing the oxidative blocks and the nano wires from the metal board body, so as to form the conductive through holes.
- the method may further comprise removing the resist layer before or after the oxidative blocks and the nano wires are exposed from the metal board body. Moreover, another surface of the metal board body on which the resist layer is not formed is polished or etched, so as to expose the oxidative blocks and the nano wires.
- the method may further comprise forming a plurality of first bumps. For instance, the first bumps may be formed on the end surfaces of the conductive through holes before the oxidative blocks and the nano wires are exposed.
- the first chip and the electronic components comprise a plurality of second bumps disposed thereon electrically connected to the first bumps.
- the first chip and the electronic component are electrically connected to the first bumps through a plurality of second bumps.
- the electronic components may be a second chip disposed on the inner-layer heat-dissipating board via a top surface thereof, and the multi-chip stack package structure and the method thereof may further comprise disposing a circuit board under a bottom surface of the second chip.
- the method of fabricating the multi-chip stack package structure may further comprises forming an underfill material between the inner-layer heat-dissipating board and the first chip, between the inner-layer heat-dissipating board and the second chip and between the circuit board and the second chip.
- a bottom surface of the electronic component is stacked on another inner-layer heat-dissipating board, a bottom surface of the inner-layer heat-dissipating board may be stacked on another electronic component, e.g., a third chip, and a bottom surface of the third chip may be also disposed on the circuit board.
- the multi-chip stack package structure and the fabrication method thereof may provide an inner-layer heat-dissipating board having a metal board body and conductive through holes penetrating the metal board body that are filled with nano wires.
- Two chips electrically connected to the conductive through holes are disposed on two surfaces of the inner-layer heat-dissipating board, respectively, such that the inner-layer heat-dissipating board is sandwiched between the stacked chips, and provides a fast heat-dissipating path for those of the chips disposed in the middle of the stack. Therefore, the problem of poor heat-dissipating efficiency is solved.
- a metal board body having oxidative blocks is used as a heat-dissipating board, and the multi-chip stack package structure thus has an enhanced overall rigidity, lowering the risk of being damaged.
- FIG. 1 is a cross-sectional view of a stack package structure having a plurality of semiconductor chips according to the prior art
- FIGS. 2A and 2B are cross-sectional views of a package structure having a plurality of stacked TSV chips according to the prior art, wherein FIG. 2B is another embodiment of FIG. 2A ; and
- FIGS. 3A to 3I are cross-sectional views illustrating embodiments of a method of fabricating an inner-layer heat-dissipating board and a multi-chip stack package structure having the inner-layer heat-dissipating board according to the present invention, wherein FIGS. 3D-1 , 3 E- 1 and 3 F- 1 are locally enlarged diagrams of FIGS. 3D , 3 E and 3 F, respectively, and FIG. 3 I′ is another embodiment of FIG. 3I .
- FIGS. 3A to 3G an embodiment of a method of fabricating an inner-layer heat-dissipating board is shown in FIGS. 3A to 3G according to the present invention.
- a resist layer 31 is formed on a surface of the metal board body 30 , and is patterned to form a plurality of openings 310 that expose a portion of the metal board body 30 .
- the portion of the metal board body 30 exposed in the openings 310 is oxidized to form a plurality of oxidative blocks 301 that may or may not penetrate into the metal board body 30 , as shown in the embodiment.
- the oxidative blocks 301 are made of aluminum.
- the oxidative blocks 301 are etched in a dry or wet etching process, so as to form a plurality of nano apertures 301 a in each of the oxidative blocks 301 .
- nano wires 301 b are deposited in the nano apertures 301 a in an electroplated or chemical deposition process.
- the nano wires 301 b are defined having a traverse length less than 100 nano meters (without limitation in longitudinal length).
- each of the nano wires 301 b has a width less than or equal to 100 nano meters, or has an aspect ratio greater than 1000.
- the nano wires 301 b are made of metal, such as copper, nickel, platinum or gold.
- the conductive through holes 32 are made by polishing or etching a surface of the metal board body 30 that opposes the surface of the metal board body 30 on which the resist layer 31 is formed, i.e., removing a surface of the metal board body 30 on which the resist layer 31 is not formed, so as to expose the oxidative block 301 and the nano wires 301 b and form the conductive through holes 32 .
- Another embodiment of the method according to the present invention further comprises, before exposing the oxidative blocks 301 and the nano wires 301 b , removing the resist layer 31 .
- the resist layer 31 is removed before the end surfaces of the oxidative block 301 and the nano wires 301 b are exposed from the metal board body 30 , or after the metal board body 30 is polished or etched.
- a plurality of first bumps 33 a such as bumps made of solder, are formed on end surfaces of the conductive through holes 32 , such that the first bumps 33 a are formed on both end surfaces of the conductive through holes 32 .
- Copper pillars may be formed on the end surfaces of the conductive through holes 32 before the formation of the conductive through holes 32 .
- the present invention provides an inner-layer heat-dissipating board, comprising: a metal board body 30 made of aluminum, for example; a plurality of conductive through holes 32 penetrating the top and bottom surfaces of the metal board body 30 , each of the conductive through holes 32 including a plurality of nano wires 301 b and an oxidative block 301 having a plurality of nano apertures 301 a filled with the nano wires 301 b.
- the inner-layer heat-dissipating board may further comprise a plurality of first bumps 33 a disposed on end surfaces of the conductive through holes 32 .
- FIGS. 3H to 3I a method of fabricating a multi-chip stack package structure is shown having the inner-layer heat-dissipating board 3 .
- a first chip 34 a and an electronic component such as a second chip 34 b are disposed on a first surface 3 a and a second surface 3 b of the inner-layer heat-dissipating board, respectively.
- the electronic component is not limited to be the second chip, and may be a circuit board.
- the first and second chips 34 a and 34 b may have a TSV design, or comprise circuits disposed on top and bottom surfaces thereof that are electrically connected to the conductive through holes 32 .
- the first chip 34 a and the second chip 34 b may be electrically connected to the first bumps 33 a disposed on the end surfaces of the conductive through holes 32 of the inner-layer heat-dissipating board 3 through conductive elements such as solder balls.
- the conductive elements may comprise metal pillars and metal bumps formed on the metal pillar that are made of solder balls, such as metal pillars 33 d formed on electrode pads 331 on a bottom surface of the second chip 34 b and third bumps 33 c formed on the metal pillar 33 d .
- the conductive elements have a structure that may be applied to other chips or inner-layer heat-dissipating boards.
- corresponding electrode pads 331 are formed on surfaces of two chips disposed on the first and second surfaces 3 a and 3 b of the inner-layer heat-dissipating board 3 , respectively.
- the electrode pads 331 are disposed on a bottom surface of the first chip 34 a and electrically connected to the conductive through holes 32 of the inner-layer heat-dissipating board 3 ;
- the electrode pads 331 are disposed on a top surface of the second chip 34 b and electrically connected to the conductive through holes 32 of the inner-layer heat-dissipating board 3 ;
- the electronic pads 331 disposed on the bottom surface of the second chip 34 b may be disposed with and electrically connected to other inner-layer heat-dissipating board or electronic components, such as circuit boards or chips.
- the inner-layer heat-dissipating board 3 may provide a fast heat-dissipating path in the multi-chip stack structure, to overcome the drawback that heat-dissipating efficiency is reduced due to the disposition of the chips in the middle of the stack.
- the present invention takes a metal board body having oxidative blocks as an inner-layer heat-dissipating board, such that the multi-chip stack package structure has an increased overall structural rigidity, reducing the risk of the multi-chip stack package structure from being damaged.
- An underfill material 36 may be further formed between the inner-layer heat-dissipating board 3 and the first chip 34 a and between the inner-layer heat-dissipating board 3 and the second chip 34 b , and may encapsulate the first bumps 33 a and the second bumps 33 b.
- FIGS. 3 I and 3 I′ illustrate, but are not intended to limit, extended stack aspects of a multi-chip stack package structure according to the present invention.
- the electronic component of the second chip 34 b is disposed on the inner-layer heat-dissipating board 3 via the top surface thereof, and the bottom surface of the second chip 34 b is stacked on a circuit board 35 through third bumps 33 c such as solder balls; or the bottom surface of the second chip 34 b is stacked on another inner-layer heat-dissipating board 3 ′, the bottom surface of the inner-layer heat-dissipating board 3 ′ is stacked on another electronic component such as a third chip 34 b ′, and the bottom surface of the third chip 34 b ′ is disposed on the circuit board 35 through third bumps 33 c such as solder balls, as shown in FIG. 3 I′.
- the circuit board 35 may be a motherboard or a packaging substrate.
- An underfill material 36 may be further formed between the circuit board 35 and the second chip 34 b , or between the circuit board 35 and the third chip 34 b ′; or between the inner-layer heat-dissipating board 3 ′ and the third chip 34 b ′ and the second chip 34 b , and may be made of a material the same as or different from the underfill material 36 formed between the inner-layer heat-dissipating board 3 and the first chip 34 a and between the inner-layer heat-dissipating board 3 and the second chip 34 b.
- the present invention also provides a multi-chip stack package structure having an inner-layer heat-dissipating board, comprising: an inner-layer heat-dissipating board 3 including a metal board body 30 and a plurality of conductive through holes 32 penetrating the metal board body 30 , each of the conductive through holes 32 including a plurality of nano wires 301 b and an oxidative block 301 having a plurality of nano apertures 301 a filled with the nano wires 301 b ; a first chip 34 a disposed on a first surface 3 a of the inner-layer heat-dissipating board 3 ; and an electronic component such as a second chip 34 b disposed on a second surface 3 b of the inner-layer heat-dissipating board 3 , and electrically connecting the first chip 34 a and the second chip 34 b to the conductive through holes, the first surface 3 a opposing the second surface 3 b.
- the metal board body 30 is made of aluminum
- the oxidative block 301 is made of aluminum oxide.
- the inner-layer heat-dissipating board 3 further comprises a plurality of first bumps 33 a disposed on end surfaces of the conductive through holes 32 .
- the first chip 34 a and the second chip 34 b have a plurality of second bumps 33 b disposed thereon that are electrically connected to the first bumps 33 a on end surfaces of the conductive through holes 32 of the inner-layer heat-dissipating board 3 .
- the multi-chip stack package structure may further comprise a circuit board 35 disposed on a bottom surface of the second chip 34 b.
- the multi-chip stack package structure further comprises an underfill material 36 formed between the inner-layer heat-dissipating board 3 and the first chip 34 a , between the inner-layer heat-dissipating board 3 and the second chip 34 b and between the circuit board 35 and the second chip 34 b , and encapsulates the first bumps 33 a and the second bumps 33 b.
- the top surface of the electronic component of the second chip 34 b is disposed on the inner-layer heat-dissipating board 3
- the bottom surface of the second chip 34 b is stacked on another inner-layer heat-dissipating board 3 ′
- another electronic component such as a third chip 34 b ′ may be disposed on the bottom surface of the inner-layer heat-dissipating board 3 ′
- third bumps 33 c such as solder balls are disposed on the bottom surface of the third chip 34 b ′ and on the circuit board 35 .
- the circuit board 35 may be a motherboard or a packaging substrate
- an inner-layer heat-dissipating board having the inner-layer heat-dissipating board and a fabrication method thereof according to the present invention
- an inner-layer heat-dissipating board is provided that has a plurality of conductive through holes filled with nano wires, and chips are disposed on two surfaces of the inner-layer heat-dissipating board and electrically connected to the conductive through holes, such that the stacked chips sandwich the inner-layer heat-dissipating board, and the inner-layer heat-dissipating board provides a fast heat-dissipating path for the chips disposed in the middle of the stack. Therefore, the problem of poor heat-dissipating efficiency is improved.
- a metal board body having oxidative blocks is used as a heat-dissipating board. Accordingly, the multi-chip stack package structure has an enhanced overall rigidity, and has a reduced risk of being damaged.
Abstract
An inner-layer heat-dissipating board and a multi-chip stack package structure having the inner-layer heat-dissipating board are disclosed. The inner-layer heat-dissipating board includes a metal board body formed with a plurality of penetrating conductive through holes each comprising a plurality of nano wires and an oxidative block having nano apertures filled with the nano wires. The multi-chip stack package structure includes a first chip and an electronic component respectively disposed on the inner-layer heat-dissipating board to thereby facilitate heat dissipation in the multi-chip stack structure as well as increase the overall package rigidity.
Description
- 1. Field of the Invention
- This invention relates to an inner-layer heat-dissipating board, a multi-chip stack package structure having the inner-layer heat-dissipating board and a fabrication method thereof, and, more particularly, to a multi-chip stack package structure that provides a heat-dissipating path and increases the overall structural rigidity in an stacked structure and a fabrication method thereof.
- 2. Description of Related Art
- With the rapid development of technology, a variety of novel products constantly come to the market. These products are designed to be increasingly low-profiled and compact sized, so as to meet the consumers' demands for ease of use and protability.
- In addition to the characteristics of being low-profile and compact in size, modern electronic products are preferred to have high efficiency, low power consumption and high functionality as well. Accordingly, manufactures have developed a technique to dispose a plurality of semiconductor chips on a circuit board or a packing substrate, in order to increase the electrical functionality. However, only a limited number of semiconductor chips can be disposed on a single packaging substrate, in that the packaging substrate does not have a large enough area. Moreover, the planer disposition of the semiconductor chips on the packaging substrate is contradictory to the requirements of having a low-profile and compact size. To address this problem, a package structure has been designed to have a plurality of semiconductor chips stacked on one another. Such a package structure having the semiconductor chips stacked has a short transmission path, and characteristics of high efficiency, low power consumption and high functionality. Compared to the conventional package structure in which a plurality of semiconductor chips are disposed on a packaging substrate one by one, the package structure in which the semiconductor chips are stacked on one another may dramatically reduce the area of the packaging substrate.
- Referring to
FIG. 1 , a multi-chip stack package structure is shown according to the prior art. Afirst semiconductor chip 11 is electrically connected throughsolder balls 110 to apackaging substrate 10. Asecond semiconductor chip 12 is stacked on thefirst semiconductor chip 11. Athird semiconductor chip 13 is stacked on thesecond semiconductor chip 12. Thesecond semiconductor chip 12, and thethird semiconductor chip 13 are electrically connected to thepackaging substrate 10 bysolder wires 14 in a wire bonding manner. - However, the
second semiconductor chip 12 has to be smaller than thefirst semiconductor chip 11 and thethird semiconductor chip 13 also has to be smaller than thesecond semiconductor chip 12, such that the first andsecond semiconductor chips solder wires 14 to be bonded thereon. As a result, a limited number of semiconductor chips may be installed on the packaging substrate. On the other hand, thesolder wires 14 are in the shape of an arc, which also limits the reduction of the volume of the package structure. - In order to solve the problems, enhance the electrical functionality and transmission efficiency, and meet the trends toward functional integration, semiconductor manufacturers have developed a technique that vertically stack on a packaging substrate a plurality of semiconductor chips each of which has through-silicon vias (TSVs) in which a conductive material is filled, to constitute a semiconductor package structure. The semiconductor package structure not only has good electrical functionality and enhanced electrical transmission efficiency, but can also meet the demands of high-end electronic products.
- Referring to
FIG. 2A , a multi-chip stack package structure with TSVs is shown. A plurality ofTSV chips 21 are stacked on and electrically connected to apackaging substrate 20 bysolder balls 201. Asemiconductor chip 22 is disposed on the very top one of the TSVchips 21. - However, heat generated by the TSV
chips 21, particularly those disposed in the middle of the stack, is difficult to dissipate to a region outside of the stack, since the gaps between any two adjacent ones of the TSVchips 21 are very small. If the temperature goes too high, it may severely impact the operation of the TSVchips 21, or even damage the TSVchips 21. - To address the above problem, a metal heat-dissipating
sheet 23 is further adhered to a surface of thesemiconductor chip 22 that is exposed to air, as shown inFIG. 2B . As a result, heat generated by the TSVchips 21 disposed in the middle of the stack may be dissipated through a conductive material such as thesolder balls 201 and the TSVs to the metal heat-dissipatingsheet 23. - However, heat generated by the TSV
chips 21 in the middle of the stack needs to travel a long path to arrive at the metal heat-dissipatingsheet 23, which reduces the heat-dissipating efficiency. Moreover, the metal heat-dissipatingsheet 23 that is disposed on thesemiconductor chip 22 should not have an area much greater than that of thesemiconductor chip 22, or adherence and stress problems may occur, and thesemiconductor chip 22 may be easily broken. - Therefore, finding a way to provide an inner layer heat-dissipating board, a multi-chip stack package structure having the inner layer heat-dissipating board and fabrication method thereof is becoming one of the most popular issues in the art.
- In view of the above-mentioned problems of the prior art, the present invention provides an inner-layer heat-dissipating board, comprising: a metal board body; and a plurality of conductive through holes penetrating the metal board body, each of the conductive through holes including a plurality of nano wires and an oxidative block having a plurality of nano apertures filled with the nano wires.
- The metal board body may be made of aluminum, and the oxidative block may be made of aluminum oxide.
- The inner-layer heat-dissipating board may further include a plurality of first bumps disposed on end surfaces of the conductive through holes.
- Each of the nano wires may have a width less than or equal to 100 nano meters, or have an aspect ration greater than 1000. The nano wires may be made of metal, such as copper, nickel, platinum or gold.
- The present invention further provides a multi-chip stack package structure, comprising: an inner-layer heat-dissipating board including a metal board body and a plurality of conductive through holes penetrating the metal board body, each of the conductive through holes including a plurality of nano wires and an oxidative block having a plurality of nano apertures filled with the nano wires; a first chip disposed on a first surface of the inner-layer heat-dissipating board; and an electronic component disposed on a second surface of the inner-layer heat-dissipating board, the second surface opposing the first surface.
- The electronic component may be a circuit board or a second chip.
- The first chip and the electronic components have a plurality of second bumps disposed thereon electrically connected to the first bumps via the second bumps.
- In the multi-chip stack package structure, the electronic component may be a second chip disposed on the inner-layer heat-dissipating board via a top surface thereof, and the multi-chip stack package structure further comprises a circuit board disposed under a bottom surface of the second chip.
- The multi-chip stack package structure may further comprise an underfill material formed between the inner-layer heat-dissipating board and the first chip, between the inner-layer heat-dissipating board and the second chip and between the circuit board and the second chip.
- Each of the nano wires may have a width less than or equal to 100 nano meters, or have an aspect ration greater than 1000. The nano wires may be made of metal, such as copper, nickel, platinum or gold.
- The present invention further provides a method of fabricating multi-chip stack package structure, comprising: providing an inner-layer heat-dissipating board including a metal board body and a plurality of conductive through holes penetrating the metal board body, each of the conductive through holes including a plurality of nano wires and an oxidative block having a plurality of nano apertures filled with the nano wires; and disposing a first chip on a first surface of the inner-layer heat-dissipating board, disposing an electronic component on a second surface of the inner-layer heat-dissipating board, the second surface opposing the first surface, and electrically connecting the first chip and the electronic component to the conductive through holes.
- The conductive through holes may be made by: forming on a surface of the metal board body a resist layer having a plurality of openings, allowing the openings to expose a portion of the metal board body; oxidizing the exposed portion of the metal board body to form oxidative blocks; patterning and etching the oxidative blocks to form the nano apertures in the oxidative blocks; forming the nano wires in the nano apertures; and exposing the oxidative blocks and the nano wires from the metal board body, so as to form the conductive through holes.
- The method may further comprise removing the resist layer before or after the oxidative blocks and the nano wires are exposed from the metal board body. Moreover, another surface of the metal board body on which the resist layer is not formed is polished or etched, so as to expose the oxidative blocks and the nano wires. The method may further comprise forming a plurality of first bumps. For instance, the first bumps may be formed on the end surfaces of the conductive through holes before the oxidative blocks and the nano wires are exposed.
- In the multi-chip stack package structure, the first chip and the electronic components comprise a plurality of second bumps disposed thereon electrically connected to the first bumps.
- In the method of fabricating a multi-chip stack package structure, the first chip and the electronic component are electrically connected to the first bumps through a plurality of second bumps.
- The electronic components may be a second chip disposed on the inner-layer heat-dissipating board via a top surface thereof, and the multi-chip stack package structure and the method thereof may further comprise disposing a circuit board under a bottom surface of the second chip.
- The method of fabricating the multi-chip stack package structure may further comprises forming an underfill material between the inner-layer heat-dissipating board and the first chip, between the inner-layer heat-dissipating board and the second chip and between the circuit board and the second chip.
- In another embodiment of the present invention, a bottom surface of the electronic component is stacked on another inner-layer heat-dissipating board, a bottom surface of the inner-layer heat-dissipating board may be stacked on another electronic component, e.g., a third chip, and a bottom surface of the third chip may be also disposed on the circuit board.
- It is known from the above that the multi-chip stack package structure and the fabrication method thereof may provide an inner-layer heat-dissipating board having a metal board body and conductive through holes penetrating the metal board body that are filled with nano wires. Two chips electrically connected to the conductive through holes are disposed on two surfaces of the inner-layer heat-dissipating board, respectively, such that the inner-layer heat-dissipating board is sandwiched between the stacked chips, and provides a fast heat-dissipating path for those of the chips disposed in the middle of the stack. Therefore, the problem of poor heat-dissipating efficiency is solved. Moreover, in the present invention a metal board body having oxidative blocks is used as a heat-dissipating board, and the multi-chip stack package structure thus has an enhanced overall rigidity, lowering the risk of being damaged.
- The invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
-
FIG. 1 is a cross-sectional view of a stack package structure having a plurality of semiconductor chips according to the prior art; -
FIGS. 2A and 2B are cross-sectional views of a package structure having a plurality of stacked TSV chips according to the prior art, whereinFIG. 2B is another embodiment ofFIG. 2A ; and -
FIGS. 3A to 3I are cross-sectional views illustrating embodiments of a method of fabricating an inner-layer heat-dissipating board and a multi-chip stack package structure having the inner-layer heat-dissipating board according to the present invention, whereinFIGS. 3D-1 , 3E-1 and 3F-1 are locally enlarged diagrams ofFIGS. 3D , 3E and 3F, respectively, and FIG. 3I′ is another embodiment ofFIG. 3I . - The following illustrative embodiments are provided to illustrate the present invention and its advantages, these and other advantages and effects being readily understood by those in the art after reading the disclosure of this specification. The present invention can also be performed or applied by different embodiments. The details of the specification are on the basis of specific applications, and numerous modifications and variations can be devised without departing from the spirit of the present invention.
- To obtain a multi-chip stack package structure according to the present invention, an embodiment of a method of fabricating an inner-layer heat-dissipating board is shown in
FIGS. 3A to 3G according to the present invention. - As shown in
FIG. 3A , ametal board body 30 made of aluminum, for example, is provided. - As shown in
FIG. 3B , a resistlayer 31 is formed on a surface of themetal board body 30, and is patterned to form a plurality ofopenings 310 that expose a portion of themetal board body 30. - As shown in
FIG. 3C , the portion of themetal board body 30 exposed in theopenings 310 is oxidized to form a plurality ofoxidative blocks 301 that may or may not penetrate into themetal board body 30, as shown in the embodiment. In an embodiment of the present invention, theoxidative blocks 301 are made of aluminum. - As shown in FIGS. 3D and 3D-1, the
oxidative blocks 301 are etched in a dry or wet etching process, so as to form a plurality ofnano apertures 301 a in each of the oxidative blocks 301. - As shown in FIGS. 3E and 3E-1,
nano wires 301 b are deposited in thenano apertures 301 a in an electroplated or chemical deposition process. In physics, thenano wires 301 b are defined having a traverse length less than 100 nano meters (without limitation in longitudinal length). In an embodiment of the present invention, each of thenano wires 301 b has a width less than or equal to 100 nano meters, or has an aspect ratio greater than 1000. Thenano wires 301 b are made of metal, such as copper, nickel, platinum or gold. - As shown in FIGS. 3F and 3F-1, end surfaces of the
oxidative blocks 301 and thenano wires 301 b are exposed from themetal board body 30, so as to form conductive through holes 32. In practice, the conductive throughholes 32 are made by polishing or etching a surface of themetal board body 30 that opposes the surface of themetal board body 30 on which the resistlayer 31 is formed, i.e., removing a surface of themetal board body 30 on which the resistlayer 31 is not formed, so as to expose theoxidative block 301 and thenano wires 301 b and form the conductive through holes 32. Another embodiment of the method according to the present invention further comprises, before exposing theoxidative blocks 301 and thenano wires 301 b, removing the resistlayer 31. For example, as shown inFIG. 3E (with reference toFIG. 3B ), the resistlayer 31 is removed before the end surfaces of theoxidative block 301 and thenano wires 301 b are exposed from themetal board body 30, or after themetal board body 30 is polished or etched. - As shown in
FIG. 3G , a plurality offirst bumps 33 a such as bumps made of solder, are formed on end surfaces of the conductive throughholes 32, such that thefirst bumps 33 a are formed on both end surfaces of the conductive through holes 32. Copper pillars may be formed on the end surfaces of the conductive throughholes 32 before the formation of the conductive through holes 32. - According to the embodiments of the above method, the present invention provides an inner-layer heat-dissipating board, comprising: a
metal board body 30 made of aluminum, for example; a plurality of conductive throughholes 32 penetrating the top and bottom surfaces of themetal board body 30, each of the conductive throughholes 32 including a plurality ofnano wires 301 b and anoxidative block 301 having a plurality ofnano apertures 301 a filled with thenano wires 301 b. - In an embodiment of the present invention, the inner-layer heat-dissipating board may further comprise a plurality of
first bumps 33 a disposed on end surfaces of the conductive through holes 32. - Referring to
FIGS. 3H to 3I , a method of fabricating a multi-chip stack package structure is shown having the inner-layer heat-dissipatingboard 3. - As shown in
FIG. 3H , afirst chip 34 a and an electronic component such as asecond chip 34 b are disposed on afirst surface 3 a and asecond surface 3 b of the inner-layer heat-dissipating board, respectively. The electronic component is not limited to be the second chip, and may be a circuit board. The first andsecond chips first chip 34 a and thesecond chip 34 b may be electrically connected to thefirst bumps 33 a disposed on the end surfaces of the conductive throughholes 32 of the inner-layer heat-dissipatingboard 3 through conductive elements such as solder balls. The conductive elements may comprise metal pillars and metal bumps formed on the metal pillar that are made of solder balls, such asmetal pillars 33 d formed onelectrode pads 331 on a bottom surface of thesecond chip 34 b andthird bumps 33 c formed on themetal pillar 33 d. Of course, the conductive elements have a structure that may be applied to other chips or inner-layer heat-dissipating boards. In general, correspondingelectrode pads 331 are formed on surfaces of two chips disposed on the first andsecond surfaces board 3, respectively. For instance, theelectrode pads 331 are disposed on a bottom surface of thefirst chip 34 a and electrically connected to the conductive throughholes 32 of the inner-layer heat-dissipatingboard 3; theelectrode pads 331 are disposed on a top surface of thesecond chip 34 b and electrically connected to the conductive throughholes 32 of the inner-layer heat-dissipatingboard 3; and theelectronic pads 331 disposed on the bottom surface of thesecond chip 34 b may be disposed with and electrically connected to other inner-layer heat-dissipating board or electronic components, such as circuit boards or chips. The inner-layer heat-dissipatingboard 3 may provide a fast heat-dissipating path in the multi-chip stack structure, to overcome the drawback that heat-dissipating efficiency is reduced due to the disposition of the chips in the middle of the stack. Moreover, the present invention takes a metal board body having oxidative blocks as an inner-layer heat-dissipating board, such that the multi-chip stack package structure has an increased overall structural rigidity, reducing the risk of the multi-chip stack package structure from being damaged. - An
underfill material 36 may be further formed between the inner-layer heat-dissipatingboard 3 and thefirst chip 34 a and between the inner-layer heat-dissipatingboard 3 and thesecond chip 34 b, and may encapsulate thefirst bumps 33 a and thesecond bumps 33 b. - Further, FIGS. 3I and 3I′ illustrate, but are not intended to limit, extended stack aspects of a multi-chip stack package structure according to the present invention. As shown in
FIG. 3I , the electronic component of thesecond chip 34 b is disposed on the inner-layer heat-dissipatingboard 3 via the top surface thereof, and the bottom surface of thesecond chip 34 b is stacked on acircuit board 35 throughthird bumps 33 c such as solder balls; or the bottom surface of thesecond chip 34 b is stacked on another inner-layer heat-dissipatingboard 3′, the bottom surface of the inner-layer heat-dissipatingboard 3′ is stacked on another electronic component such as athird chip 34 b′, and the bottom surface of thethird chip 34 b′ is disposed on thecircuit board 35 throughthird bumps 33 c such as solder balls, as shown in FIG. 3I′. In an embodiment of the present invention, thecircuit board 35 may be a motherboard or a packaging substrate. - An
underfill material 36 may be further formed between thecircuit board 35 and thesecond chip 34 b, or between thecircuit board 35 and thethird chip 34 b′; or between the inner-layer heat-dissipatingboard 3′ and thethird chip 34 b′ and thesecond chip 34 b, and may be made of a material the same as or different from theunderfill material 36 formed between the inner-layer heat-dissipatingboard 3 and thefirst chip 34 a and between the inner-layer heat-dissipatingboard 3 and thesecond chip 34 b. - According to the embodiments of the above method, the present invention also provides a multi-chip stack package structure having an inner-layer heat-dissipating board, comprising: an inner-layer heat-dissipating
board 3 including ametal board body 30 and a plurality of conductive throughholes 32 penetrating themetal board body 30, each of the conductive throughholes 32 including a plurality ofnano wires 301 b and anoxidative block 301 having a plurality ofnano apertures 301 a filled with thenano wires 301 b; afirst chip 34 a disposed on afirst surface 3 a of the inner-layer heat-dissipatingboard 3; and an electronic component such as asecond chip 34 b disposed on asecond surface 3 b of the inner-layer heat-dissipatingboard 3, and electrically connecting thefirst chip 34 a and thesecond chip 34 b to the conductive through holes, thefirst surface 3 a opposing thesecond surface 3 b. - In an embodiment of the present invention, the
metal board body 30 is made of aluminum, and theoxidative block 301 is made of aluminum oxide. - In an embodiment of the present invention, the inner-layer heat-dissipating
board 3 further comprises a plurality offirst bumps 33 a disposed on end surfaces of the conductive through holes 32. Thefirst chip 34 a and thesecond chip 34 b have a plurality ofsecond bumps 33 b disposed thereon that are electrically connected to thefirst bumps 33 a on end surfaces of the conductive throughholes 32 of the inner-layer heat-dissipatingboard 3. Moreover, if the top surface of the electronic component of thesecond chip 34 b is disposed on the inner-layer heat-dissipatingboard 3, the multi-chip stack package structure may further comprise acircuit board 35 disposed on a bottom surface of thesecond chip 34 b. - The multi-chip stack package structure further comprises an
underfill material 36 formed between the inner-layer heat-dissipatingboard 3 and thefirst chip 34 a, between the inner-layer heat-dissipatingboard 3 and thesecond chip 34 b and between thecircuit board 35 and thesecond chip 34 b, and encapsulates thefirst bumps 33 a and thesecond bumps 33 b. - Alternatively, if the top surface of the electronic component of the
second chip 34 b is disposed on the inner-layer heat-dissipatingboard 3, and the bottom surface of thesecond chip 34 b is stacked on another inner-layer heat-dissipatingboard 3′, another electronic component such as athird chip 34 b′ may be disposed on the bottom surface of the inner-layer heat-dissipatingboard 3′, andthird bumps 33 c such as solder balls are disposed on the bottom surface of thethird chip 34 b′ and on thecircuit board 35. Thecircuit board 35 may be a motherboard or a packaging substrate - In an inner-layer heat-dissipating board, a multi-chip stack package structure having the inner-layer heat-dissipating board and a fabrication method thereof according to the present invention, an inner-layer heat-dissipating board is provided that has a plurality of conductive through holes filled with nano wires, and chips are disposed on two surfaces of the inner-layer heat-dissipating board and electrically connected to the conductive through holes, such that the stacked chips sandwich the inner-layer heat-dissipating board, and the inner-layer heat-dissipating board provides a fast heat-dissipating path for the chips disposed in the middle of the stack. Therefore, the problem of poor heat-dissipating efficiency is improved. In the present invention, a metal board body having oxidative blocks is used as a heat-dissipating board. Accordingly, the multi-chip stack package structure has an enhanced overall rigidity, and has a reduced risk of being damaged.
- The foregoing descriptions of the detailed embodiments are illustrated to disclose the features and functions of the present invention and are not intended to be restrictive of the scope of the present invention. It should be understood to those in the art that all modifications and variations made according to the spirit and principles in the disclosure of the present invention will fall within the scope of the appended claims.
Claims (12)
1-15. (canceled)
16. A method of fabricating a multi-chip stack package structure, comprising the steps of:
providing an inner-layer heat-dissipating board including a metal board body and a plurality of conductive through holes penetrating the metal board body, each of the conductive through holes including a plurality of nano wires and an oxidative block having a plurality of nano apertures filled with the nano wires; and
disposing a first chip on a first surface of the inner-layer heat-dissipating board, disposing an electronic component on a second surface of the inner-layer heat-dissipating board, the second surface opposing the first surface, and electrically connecting the first chip and the electronic component to the conductive through holes.
17. The method of claim 16 , wherein the metal board body is made of aluminum, and the oxidative block is made of aluminum oxide.
18. The method of claim 16 , wherein the conductive through holes are made by the steps of:
forming on a surface of the metal board body a resist layer having a plurality of openings, allowing the openings to expose a portion of the metal board body;
oxidizing the exposed portion of the metal board body to form oxidative blocks;
patterning and etching the oxidative blocks to form the nano apertures in the oxidative blocks;
forming the nano wires in the nano apertures; and
exposing the oxidative blocks and the nano wires from the metal board body, so as to form the conductive through holes.
19. The method of claim 18 , further comprising removing the resist layer.
20. The method of claim 18 , wherein the step of exposing the oxidative blocks and the nano wires from the metal board body comprises polishing or etching another surface of the metal board body on which the resist layer is not formed, so as to expose the oxidative blocks and the nano wires.
21. The method of claim 18 , further comprising forming first bumps on end surfaces of the conductive through holes.
22. The method of claim 21 , wherein the first chip and the electronic component are electrically connected to the first bumps through a plurality of second bumps correspondingly.
23. The method of claim 16 , wherein the electronic component is a circuit board or a second chip.
24. The method of claim 23 , wherein the electronic component is the second chip, and the second chip is disposed on the inner-layer heat-dissipating board via a top surface thereof, and has a bottom surface under which a circuit board is disposed.
25. The method of claim 24 , further comprising forming an underfill material between the inner-layer heat-dissipating board and the first chip, between the inner-layer heat-dissipating board and the second chip and between the circuit board and the second chip.
26. The method of claim 16 , further comprising stacking another inner-layer heat-dissipating board on a bottom surface of the electronic component.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/964,488 US20130326873A1 (en) | 2011-03-02 | 2013-08-12 | Method of fabricating multi-chip stack package structure having inner layer heat-dissipating board |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW100106829A TWI434380B (en) | 2011-03-02 | 2011-03-02 | Inner layer heat-dissipating board and multi-chip stack package structure having inner layer heat-dissipating board and fabrication method thereof |
TW100106829 | 2011-03-02 | ||
US13/112,253 US8520391B2 (en) | 2011-03-02 | 2011-05-20 | Inner-layer heat-dissipating board, multi-chip stack package structure having the inner layer heat-dissipating board and fabrication method thereof |
US13/964,488 US20130326873A1 (en) | 2011-03-02 | 2013-08-12 | Method of fabricating multi-chip stack package structure having inner layer heat-dissipating board |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/112,253 Division US8520391B2 (en) | 2011-03-02 | 2011-05-20 | Inner-layer heat-dissipating board, multi-chip stack package structure having the inner layer heat-dissipating board and fabrication method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
US20130326873A1 true US20130326873A1 (en) | 2013-12-12 |
Family
ID=46753172
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/112,253 Expired - Fee Related US8520391B2 (en) | 2011-03-02 | 2011-05-20 | Inner-layer heat-dissipating board, multi-chip stack package structure having the inner layer heat-dissipating board and fabrication method thereof |
US13/964,488 Abandoned US20130326873A1 (en) | 2011-03-02 | 2013-08-12 | Method of fabricating multi-chip stack package structure having inner layer heat-dissipating board |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/112,253 Expired - Fee Related US8520391B2 (en) | 2011-03-02 | 2011-05-20 | Inner-layer heat-dissipating board, multi-chip stack package structure having the inner layer heat-dissipating board and fabrication method thereof |
Country Status (2)
Country | Link |
---|---|
US (2) | US8520391B2 (en) |
TW (1) | TWI434380B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10854530B1 (en) * | 2019-07-31 | 2020-12-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Heat dissipation structures |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201533882A (en) * | 2014-02-21 | 2015-09-01 | Chipmos Technologies Inc | Stacked flip chip package |
KR20170019676A (en) * | 2015-08-12 | 2017-02-22 | 삼성전자주식회사 | Fabricating method of a semiconductor device |
CN108170239A (en) * | 2018-01-30 | 2018-06-15 | 石家庄东远散热技术有限公司 | A kind of water-filled radiator for being used to dig ore deposit device |
CN116435290B (en) * | 2023-06-13 | 2023-08-22 | 中诚华隆计算机技术有限公司 | Three-dimensional stacking structure and stacking method of chips |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6129901A (en) * | 1997-11-18 | 2000-10-10 | Martin Moskovits | Controlled synthesis and metal-filling of aligned carbon nanotubes |
US6319829B1 (en) * | 1999-08-18 | 2001-11-20 | International Business Machines Corporation | Enhanced interconnection to ceramic substrates |
US20040173914A1 (en) * | 2003-03-06 | 2004-09-09 | Takashi Kurihara | Semiconductor device |
US7301191B1 (en) * | 2004-09-16 | 2007-11-27 | Atomate Corporation | Fabricating carbon nanotube transistor devices |
US20110220404A1 (en) * | 2010-03-11 | 2011-09-15 | Shinko Electric Industries Co., Ltd. | Wiring substrate and method of manufacturing the same |
US8048794B2 (en) * | 2009-08-18 | 2011-11-01 | International Business Machines Corporation | 3D silicon-silicon die stack structure and method for fine pitch interconnection and vertical heat transport |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7112472B2 (en) * | 2003-06-25 | 2006-09-26 | Intel Corporation | Methods of fabricating a composite carbon nanotube thermal interface device |
US7538422B2 (en) * | 2003-08-25 | 2009-05-26 | Nanoconduction Inc. | Integrated circuit micro-cooler having multi-layers of tubes of a CNT array |
US7504453B2 (en) * | 2004-02-02 | 2009-03-17 | The Board Of Trustees Of The Leland Stanford Junior University | Composite thermal interface material including particles and nanofibers |
US8106510B2 (en) * | 2009-08-04 | 2012-01-31 | Raytheon Company | Nano-tube thermal interface structure |
-
2011
- 2011-03-02 TW TW100106829A patent/TWI434380B/en not_active IP Right Cessation
- 2011-05-20 US US13/112,253 patent/US8520391B2/en not_active Expired - Fee Related
-
2013
- 2013-08-12 US US13/964,488 patent/US20130326873A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6129901A (en) * | 1997-11-18 | 2000-10-10 | Martin Moskovits | Controlled synthesis and metal-filling of aligned carbon nanotubes |
US6319829B1 (en) * | 1999-08-18 | 2001-11-20 | International Business Machines Corporation | Enhanced interconnection to ceramic substrates |
US20040173914A1 (en) * | 2003-03-06 | 2004-09-09 | Takashi Kurihara | Semiconductor device |
US7301191B1 (en) * | 2004-09-16 | 2007-11-27 | Atomate Corporation | Fabricating carbon nanotube transistor devices |
US8048794B2 (en) * | 2009-08-18 | 2011-11-01 | International Business Machines Corporation | 3D silicon-silicon die stack structure and method for fine pitch interconnection and vertical heat transport |
US20110220404A1 (en) * | 2010-03-11 | 2011-09-15 | Shinko Electric Industries Co., Ltd. | Wiring substrate and method of manufacturing the same |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10854530B1 (en) * | 2019-07-31 | 2020-12-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Heat dissipation structures |
CN112310051A (en) * | 2019-07-31 | 2021-02-02 | 台湾积体电路制造股份有限公司 | Heat dissipation structure and stacking structure |
KR20210016250A (en) * | 2019-07-31 | 2021-02-15 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Heat dissipation structures |
KR102318311B1 (en) | 2019-07-31 | 2021-10-29 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Heat dissipation structures |
TWI744830B (en) * | 2019-07-31 | 2021-11-01 | 台灣積體電路製造股份有限公司 | Stacking structure |
US11670562B2 (en) | 2019-07-31 | 2023-06-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Heat dissipation structures |
Also Published As
Publication number | Publication date |
---|---|
US20120224328A1 (en) | 2012-09-06 |
TWI434380B (en) | 2014-04-11 |
TW201238015A (en) | 2012-09-16 |
US8520391B2 (en) | 2013-08-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI651828B (en) | Chip package structure and method of manufacturing same | |
US9899249B2 (en) | Fabrication method of coreless packaging substrate | |
US10796970B2 (en) | Method for fabricating electronic package | |
US8004079B2 (en) | Chip package structure and manufacturing method thereof | |
TWI496270B (en) | Semiconductor package and method of manufacture | |
US20120049366A1 (en) | Package structure having through-silicon-via (tsv) chip embedded therein and fabrication method thereof | |
KR101107858B1 (en) | Conductive pillar structure for semiconductor substrate and method of manufacture | |
US20140367850A1 (en) | Stacked package and method of fabricating the same | |
US20140306340A1 (en) | Package structure having embedded electronic component | |
CN103782381A (en) | Electronic assembly including die on substrate with heat spreader having an open window on the die | |
US20120146216A1 (en) | Semiconductor package and fabrication method thereof | |
US8933561B2 (en) | Semiconductor device for semiconductor package having through silicon vias of different heights | |
US20130326873A1 (en) | Method of fabricating multi-chip stack package structure having inner layer heat-dissipating board | |
TWI467735B (en) | Multi-chip stack package structure and fabrication method thereof | |
US7626260B2 (en) | Stack-type semiconductor device having cooling path on its bottom surface | |
TWI467731B (en) | Semiconductor package and method for fabricating the same | |
TW200910560A (en) | Packaging substrate structure with capacitor embedded therein and method for fabricating the same | |
JP2010074072A (en) | Semiconductor device and method of manufacturing semiconductor device | |
US20110042806A1 (en) | Multi-chip module and method of manufacturing the same | |
TWI455271B (en) | Semiconductor component and method of making same | |
JP2015057827A (en) | Semiconductor package | |
TWI438880B (en) | Package structure having (tsv) through-silicon-vias chip embedded therein and fabrication method thereof | |
CN108633174B (en) | Circuit board stacking structure and manufacturing method thereof | |
KR101450761B1 (en) | A semiconductor package, stacked semiconductor package and manufacturing method thereof | |
JP2011061132A (en) | Interposer |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |