US20130181324A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- US20130181324A1 US20130181324A1 US13/788,542 US201313788542A US2013181324A1 US 20130181324 A1 US20130181324 A1 US 20130181324A1 US 201313788542 A US201313788542 A US 201313788542A US 2013181324 A1 US2013181324 A1 US 2013181324A1
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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Abstract
A semiconductor device sends and receives electrical signals. The semiconductor device includes a first substrate provided with a first circuit region containing a first circuit; a multi-level interconnect structure provided on the first substrate; a first inductor provided in the multi-level interconnect structure so as to include the first circuit region; and a second inductor provided in the multi-level interconnect structure so as to include the first circuit region, wherein one of the first inductor and the second inductor is connected to the first circuit and the other of the first inductor and the second inductor is connected to a second circuit.
Description
- The present application is based on Japanese Patent Application No. 2009-061276.
- 1. Field of the Invention
- The present invention relates to a semiconductor device which can transmit electrical signals between two circuits whose input electrical signals differ in electrical potential.
- 2. Description of the Related Art
- A photocoupler is often used to transmit electrical signals between two circuits whose input electrical signals differ in electrical potential. The photocoupler has a light emitting element such as a light emitting diode and a light receiving element such as a phototransistor. Thus, the photocoupler converts an inputted electrical signal into light using the light emitting element, reconverts the light into an electrical signal using the light receiving element, and thereby transmits the electrical signal.
- However, the photocoupler, which has a light emitting element and light receiving element, is difficult to downsize. Also, the photocoupler cannot follow high-frequency electrical signals. To solve these problems, a technique which transmits an electrical signal by inductively coupling two inductors has been developed, such as described in National Publication of International Patent Application No. 2001-513276.
- Also, Japanese Patent Laid-Open No. 2008-283172 and International Publication No. 2004-112138 describe a technique which involves placing a circuit inside an inductor when seen in planar view, where the inductor is used as an antenna.
- However, the present inventor has newly noticed the following problem. To downsize elements which transmit electrical signals between two circuits whose input electrical signals differ in electrical potential, it is conceivable to form inductors in interconnect layers using manufacturing technology for semiconductor device and placing the inductors face to face to each other. When two inductors in a semiconductor device are inductively coupled in this way to transmit electrical signals, the installation of the two inductors may increase the size of the semiconductor device.
- The present invention provides a semiconductor device comprising: a first substrate provided with a first circuit region containing a first circuit; a multi-level interconnect structure provided on the first substrate; a first inductor provided in the multi-level interconnect structure so as to include the first circuit region; and a second inductor provided in the multi-level interconnect structure so as to include the first circuit region, wherein one of the first inductor and the second inductor is connected to the first circuit and the other of the first inductor and the second inductor is connected to a second circuit.
- Since electrical signals can be sent and received using the first inductor and second inductor provided in the multi-level interconnect structure in such a way as to include the first circuit region, the present invention can limit increases in the size of the semiconductor device.
- The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
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FIG. 1 is a sectional view illustrating a configuration of a semiconductor device according to a first embodiment; -
FIG. 2 is a schematic plan view of the semiconductor device illustrated inFIG. 1 ; -
FIG. 3 is a schematic plan view illustrating a configuration of a semiconductor device according to a second embodiment; -
FIG. 4 is a schematic plan view illustrating a configuration of a semiconductor device according to a third embodiment; -
FIG. 5 is a schematic plan view illustrating a configuration of a semiconductor device according to a variation of the semiconductor device inFIG. 4 ; -
FIG. 6 is a schematic plan view illustrating a configuration of a semiconductor device according to a fourth embodiment; -
FIG. 7 is a schematic plan view illustrating a configuration of a semiconductor device according to a fifth embodiment; and -
FIG. 8 is a sectional view illustrating a configuration of a semiconductor device according to a sixth embodiment. - The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes.
- Embodiments of the present invention will be described below with reference to the drawings, throughout which similar components are denoted by the same reference numerals, and description thereof will be omitted as required.
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FIG. 1 is a sectional view illustrating a configuration of a semiconductor device according to a first embodiment. The semiconductor device has afirst semiconductor chip 10. Thefirst semiconductor chip 10 includes afirst substrate 102,first circuit 100,multi-level interconnect structure 400, first inductor 310 (transmitting inductor), and second inductor 320 (receiving inductor). Thefirst substrate 102 is a semiconductor substrate such as a silicon substrate. Thefirst circuit 100 is formed on thefirst substrate 102. Themulti-level interconnect structure 400 is formed on thefirst substrate 102. Thefirst inductor 310 is formed in themulti-level interconnect structure 400 and wound up in a plane parallel to thefirst substrate 102. Thesecond inductor 320 is formed in themulti-level interconnect structure 400, wound up in a plane parallel to thefirst substrate 102, and superimposed on thefirst inductor 310 when seen in planar view. Thefirst circuit 100 is connected to one of thefirst inductor 310 andsecond inductor 320. When seen in planar view, at least part of thefirst circuit 100 is located inside thefirst inductor 310 andsecond inductor 320. - The
first inductor 310 andsecond inductor 320 make up asignal transmission device 300. By being inductively coupled to each other, thefirst inductor 310 andsecond inductor 320 transmit electrical signals to each other. The electrical signals, for example, are digital signals, but may be analog signals. - According to the present embodiment, the
first inductor 310 is connected to thefirst circuit 100 while thesecond inductor 320 is connected to asecond semiconductor chip 20. Thefirst circuit 100 is a transmit circuit. That is, thefirst inductor 310 functions as a transmitting inductor and thesecond inductor 320 functions as a receiving inductor. For example,bonding wires 520 are used to connect thesecond inductor 320 andsecond semiconductor chip 20. Thesecond semiconductor chip 20 includes asecond substrate 202,second circuit 200, andmulti-level interconnect structure 600. Thesecond circuit 200 includes a receive circuit and is connected to thesecond inductor 320 via themulti-level interconnect structure 600 andbonding wires 520. - As illustrated in
FIG. 2 , thefirst circuit 100 includes amodulator 155 which modulates digital signals into transmit signals and atransmit driver circuit 150 which outputs the modulated signals to thefirst inductor 310. Thesecond circuit 200 includes areceive circuit 260 connected to thesecond inductor 320 as well as includes a receive driver circuit 250 (e.g., gate driver). The receivecircuit 260 demodulates the modulated signals into digital signals. The receivecircuit 260 outputs the resulting digital signals to the receivedriver circuit 250. - The
first circuit 100 andsecond circuit 200 differ from each other in the electrical potential of inputted electrical signals, but since thefirst inductor 310 andsecond inductor 320 send and receive electrical signals using inductive coupling, thefirst circuit 100 andsecond circuit 200 do not encounter any problem. Incidentally, in the configuration illustrated inFIG. 1 , possible cases in which “inputted electrical signals differ from each other in electrical potential” include a case in which the electrical signals differ from each other in amplitude (electrical potential represented by 0 and electrical potential represented by 1), a case in which the electrical signals differ from each other in reference voltage (electrical potential represented by 0), and a case in which the electrical signals differ from each other in both amplitude and reference voltage. - The
first circuit 100 of thefirst semiconductor chip 10 has first transistors. The first transistors include a first-conductivity type transistor and second-conductivity type transistor. The first-conductivity typefirst transistor 121 is formed in a second-conductivity type well 120 and has two first-conductivity type dopedregions 124 and agate electrode 126, where the first-conductivity type dopedregions 124 serve as a source and drain. The second-conductivity typefirst transistor 141 is formed in a first-conductivity type well 140 and has two second-conductivity type dopedregions 144 and agate electrode 146, where the second-conductivity type dopedregions 144 serve as a source and drain. A gate insulating film is formed under each of thegate electrodes first transistors - A second-conductivity type doped
region 122 is formed in the well 120 and a first-conductivity type dopedregion 142 is formed in thewell 140. The dopedregion 122 is connected with a wire which gives a reference voltage (ground potential) for the first-conductivity typefirst transistor 121 and the dopedregion 142 is connected with a wire which gives a reference voltage for the second-conductivity typefirst transistor 141. - The
second circuit 200 of thesecond semiconductor chip 20 has second transistors. The second transistors also include a first-conductivity type transistor and second-conductivity type transistor. The first-conductivity typesecond transistor 221 is formed in a second-conductivity type well 220 and has two first-conductivity type dopedregions 224 and agate electrode 226, where the first-conductivity type dopedregions 224 serve as a source and drain. The second-conductivity typesecond transistor 241 is formed in a first-conductivity type well 240 and has two second-conductivity type dopedregions 244 and agate electrode 246, where the second-conductivity type dopedregions 244 serve as a source and drain. A gate insulating film is formed under each of thegate electrodes second transistors driver circuit 250 and receivecircuit 260. - A second-conductivity type doped
region 222 is formed in the well 220 and a first-conductivity type dopedregion 242 is formed in thewell 240. The dopedregion 222 is connected with a wire which gives a reference voltage for the first-conductivity typesecond transistor 221 and the dopedregion 242 is connected with a wire which gives a reference voltage for the second-conductivity typesecond transistor 241. - In the example illustrated in
FIG. 1 , the gate insulating films differ in thickness between the first transistors (121 and 141) and second transistors (221 and 241), but may have the same thickness. - According to the present embodiment, the
first inductor 310 andsecond inductor 320 are spiral wiring patterns formed in different interconnect layers. Thefirst inductor 310 is located, for example, in thelowermost interconnect layer 412 and thesecond inductor 320 is located, for example, in theuppermost interconnect layer 442. - When seen in planar view, the
first circuit 100 fits entirely in the space occupied by thefirst inductor 310 andsecond inductor 320. The spacing between thefirst inductor 310 andsecond inductor 320 is smaller than the diameter of thefirst inductor 310 and diameter of thesecond inductor 320. This makes it easier to inductively couple thefirst inductor 310 andsecond inductor 320. - The
multi-level interconnect structure 400 is formed by alternately stacking an insulation layer and interconnect layer in this order t times (t≧3) each. Thefirst inductor 310 is provided in the nth interconnect layer of themulti-level interconnect structure 400. Thesecond inductor 320 is provided in the mth interconnect layer (t≧m≧n+2) of themulti-level interconnect structure 400 and located above thefirst inductor 310. That is, thefirst inductor 310 andsecond inductor 320 are formed in different interconnect layers. No inductor is provided in any interconnect layer between the nth interconnect layer and mth interconnect layer, i.e., between thefirst inductor 310 andsecond inductor 320. According to the present embodiment, themulti-level interconnect structure 400 is formed by stacking aninsulation layer 410, theinterconnect layer 412, aninsulation layer 420, aninterconnect layer 422, aninsulation layer 430, aninterconnect layer 432, aninsulation layer 440, and theinterconnect layer 442 in this order. Each of the insulation layers 410, 420, 430, and 440 may be a stack of multiple insulating films or a single insulating film. - The wires used for the interconnect layers 412, 422, 432, and 442 are Cu wires formed by the Damascene process and are buried in grooves formed in the interconnect layers 412, 422, 432, and 442, respectively. Pads (not shown) are formed on the uppermost interconnect layer. Incidentally, at least one of the interconnect layers 412, 422, 432, and 442 may be made of Al alloy wires. The wires formed in the interconnect layers 412, 422, 432, and 442 are interconnected via plugs buried in the insulation layers 410, 420, 430, and 440.
- The insulating films in the insulation layers and interconnect layers may be SiO2 films or low-dielectric films. The low-dielectric films may have a relative dielectric constant of 3.3 or below, and preferably 2.9 or below. In addition to SiOC, possible material of the low-dielectric films include hydrogen polysiloxanes such as HSQ (hydrogen silsesquioxane), MSQ (methyl silsesquioxane), and MHSQ (methylated hydrogen silsesquioxane); aromatic organic materials such as polyarylether (PAE), divinyl siloxane-bis-benzocyclobutene (BCB), and Silk (registered trademark); SOG; FOX(flowable oxide); Cytop; and BCB (Bensocyclobutene). Also, porous films of the materials listed above may be used as the low-dielectric films.
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FIG. 2 is a schematic plan view of the semiconductor device illustrated inFIG. 1 . As described above, thefirst circuit 100 is located inside thefirst inductor 310 andsecond inductor 320 when seen in planar view. Thefirst circuit 100 includes the transmitdriver 150. At least part of the transmit driver 150 (for example, an inverter) is made up of thefirst transistors driver 150 is connected with oneend 312 of thefirst inductor 310. Theother end 314 of thefirst inductor 310 is connected to a power wire or ground wire. - Next, a manufacturing method of the
first semiconductor chip 10 will be described. To begin with, thefirst circuit 100 is formed on thefirst substrate 102. Then, themulti-level interconnect structure 400 is formed on thefirst substrate 102. When themulti-level interconnect structure 400 is formed, thefirst inductor 310 andsecond inductor 320 are formed as well. Also, thefirst inductor 310 is connected to thefirst circuit 100 via wiring in themulti-level interconnect structure 400. - Next, operation and advantages of the present embodiment will be described. Inductor requires a relatively large area (e.g., a diameter of 500 μm). Consequently, the
first inductor 310 andsecond inductor 320, when installed in thefirst semiconductor chip 10 to transmit electrical signals, tend to increase the size of thefirst semiconductor chip 10. On the other hand, according to the present embodiment, at least part of thefirst circuit 100 is located inside thefirst inductor 310 andsecond inductor 320 when seen in planar view. This limits increases in the size of thefirst semiconductor chip 10. This effect is especially pronounced when thefirst circuit 100 fits entirely in the space occupied by thefirst inductor 310 andsecond inductor 320 when seen in planar view. - Also, the spacing between the
first inductor 310 andsecond inductor 320 can be made smaller than the diameter of thefirst inductor 310 and diameter of thesecond inductor 320. When thefirst inductor 310 andsecond inductor 320 are inductively coupled, preferably the diameter of thefirst inductor 310 andsecond inductor 320 is increased and the spacing between thefirst inductor 310 andsecond inductor 320 is decreased. Thus, when the spacing between thefirst inductor 310 andsecond inductor 320 is made smaller than the diameter of thefirst inductor 310 and diameter of thesecond inductor 320 as in the case of the present embodiment, it becomes easier to inductively couple thefirst inductor 310 andsecond inductor 320, increasing signal transmission efficiency between thefirst inductor 310 andsecond inductor 320. -
FIG. 3 is a schematic plan view illustrating a configuration of a semiconductor device according to a second embodiment and corresponds toFIG. 2 according to the first embodiment. In the semiconductor device, an external terminal (e.g., pad) 12 of thefirst semiconductor chip 10 is located inside thefirst inductor 310 andsecond inductor 320 when seen in planar view. Otherwise, the configuration is the same as in the first embodiment. - The present embodiment provides advantages similar to those of the first embodiment. Also, since the
external terminal 12 of thefirst semiconductor chip 10 is located inside thefirst inductor 310 andsecond inductor 320 when seen in planar view, there is no need for wiring to cross thefirst inductor 310 andsecond inductor 320 when connecting circuits formed in thefirst semiconductor chip 10 with theexternal terminal 12. This makes it easier to route wiring. -
FIG. 4 is a schematic plan view illustrating a configuration of a semiconductor device according to a third embodiment. The semiconductor device has the same configuration as the first and second embodiments except that thefirst semiconductor chip 10 andsecond semiconductor chip 20 send and receive signals bidirectionally and that thefirst semiconductor chip 10 andsecond semiconductor chip 20 each include afirst circuit 100,first inductor 310,second inductor 320, andsecond circuit 200. Incidentally, themodulator 155 illustrated inFIGS. 2 and 3 is omitted from illustration inFIG. 4 . - That is, the
first circuit 100 of thefirst semiconductor chip 10 is connected to thesecond circuit 200 of thesecond semiconductor chip 20 via thefirst inductor 310,second inductor 320, andbonding wires 520 of thefirst semiconductor chip 10. Also, thefirst circuit 100 of thesecond semiconductor chip 20 is connected to thesecond circuit 200 of thefirst semiconductor chip 10 via thefirst inductor 310,second inductor 320, andbonding wires 520 of thesecond semiconductor chip 20. - The present embodiment also provides advantages similar to those of the first or second embodiment. Incidentally, according to the present embodiment, as illustrated in
FIG. 5 , in both thefirst semiconductor chip 10 andsecond semiconductor chip 20, thefirst circuit 100 andsecond circuit 200 may be placed inside thefirst inductor 310 andsecond inductor 320 when seen in planar view. -
FIG. 6 is a schematic plan view illustrating a configuration of a semiconductor device according to a fourth embodiment. The semiconductor device has the same configuration as the third embodiment except that two pairs of thefirst inductor 310 andsecond inductor 320 are both formed on thefirst semiconductor chip 10. Themodulator 155 is omitted from illustration inFIG. 6 . - The
second circuit 200 of thefirst semiconductor chip 10 is connected with thefirst inductor 310 as a receiving inductor. When seen in planar view, at least part of, and preferably all of, thesecond circuit 200 is located inside thefirst inductor 310 and thesecond inductor 320 inductively coupled with thefirst inductor 310. - The present embodiment also provides advantages similar to those of the third embodiment.
-
FIG. 7 is a schematic plan view illustrating a configuration of a semiconductor device according to a fifth embodiment and corresponds toFIG. 2 according to the first embodiment. The semiconductor device has the same configuration as the semiconductor device according to the first embodiment except that thefirst circuit 100 includes a receive circuit 152 and a receive driver circuit 154 (e.g., gate driver) and that thesecond circuit 200 is a transmit circuit. According to the present embodiment, thesecond inductor 320 functions as a transmitting inductor and thefirst inductor 310 functions as a receiving inductor. - The
second circuit 200 includes a modulator which modulates digital signals into transmit signals and a transmit driver circuit which outputs the modulated signals to thesecond inductor 320. The receive circuit 152 of thefirst circuit 100 demodulates the modulated signals into digital signals. The receive circuit 152 outputs the resulting digital signals to the receive driver circuit 154. - The receive driver circuit 154 includes the
first transistors FIG. 1 according to the first embodiment. Thefirst transistors - The present embodiment also provides advantages similar to those of the first embodiment.
-
FIG. 8 is a sectional view illustrating a configuration of a semiconductor device according to a sixth embodiment. The semiconductor device has the same configuration as the semiconductor device according to any of the first to fifth embodiments except that thefirst substrate 102 is an SOI (Silicon On Insulator) substrate and that thesecond circuit 200 is formed on thefirst substrate 102. That is, whereas according to the first to fifth embodiments, the semiconductor device is implemented on two semiconductor chips, according to the present embodiment, the semiconductor device is implemented on a single semiconductor chip. - A
device isolation film 104 is buried in a silicon layer of thefirst substrate 102. A lower end of thedevice isolation film 104 reaches an insulation layer of thefirst substrate 102. Thedevice isolation film 104 insulates thefirst circuit 100 andsecond circuit 200 from each other. This prevents thefirst circuit 100 andsecond circuit 200 from affecting each other even if they differ in reference voltage. - The present embodiment also provides advantages similar to those of the first to fifth embodiments. In addition, the
first circuit 100 andsecond circuit 200 can be formed in a single semiconductor chip. - It should be noted that embodiments described above with reference to the drawings are only exemplary of the present invention and that various configurations other than those described above can be adopted according to the present invention. For example, the
first inductor 310 andsecond inductor 320 may be placed in such a way as not to overlap when seen in planar view. In that case, thefirst inductor 310 andsecond inductor 320 may be formed in the same interconnect layer. Alternatively, a half of one inductor may overlap the other inductor and the remaining half may be placed without overlapping the other inductor. - It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and sprit of the invention.
Claims (14)
1. A semiconductor device comprising:
a multi-level interconnect structure provided over a substrate;
an inductor provided in the multi-level interconnect structure so as to surround all external connection terminals provided over the substrate in a plan view; and
a further inductor provided in the multi-level interconnect structure so as to surround the all external connection terminals provided over the substrate in a plan view,
wherein the further inductor is provided over the inductor.
2. The semiconductor device according to claim 1 , wherein the external connection terminal is a pad.
3. The semiconductor device according to claim 1 ,
wherein the substrate is provided with a circuit region including a circuit such that each of the inductor and the further inductor is provided so as to surround all transistors included in the circuit and such that one of the inductor and the further inductor is connected to the circuit.
4. A semiconductor device comprising:
a multi-level interconnect structure provided over a substrate;
an inductor provided in the multi-level interconnect structure so as to surround all external connection terminals provided over the substrate in a plan view; and
a further inductor provided in the multi-level interconnect structure so as to arranged within all circuits provided over a circuit region of the substrate in a plan view,
wherein the further inductor is provided over the inductor.
5. The semiconductor device according to claim 4 , wherein the external connection terminal is a pad.
6. The semiconductor device according to claim 4 ,
wherein each of the inductor and the further inductor is provided so as to surround all transistors included in the all circuits, and such that one of the inductor and the further inductor is connected to the circuit.
7. A semiconductor device comprising:
a multi-level interconnect structure provided over a substrate;
an inductor provided in the multi-level interconnect structure so as to surround all external connection terminals provided over the substrate in a plan view.
8. The semiconductor device according to claim 7 , further comprising:
a further inductor provided in the multi-level interconnect structure and over the substrate in a plan view such that the further inductor is provided over the inductor.
9. The semiconductor device according to claim 7 ,
wherein the inductor is provided so as to surround all transistors included in a circuit of the substrate such that the inductor is connected to the circuit.
10. The semiconductor device according to claim 7 ,
wherein the external connection terminal is a pad.
11. A semiconductor device comprising:
a multi-level interconnect structure provided over a substrate;
an inductor provided in the multi-level interconnect structure so as to arranged within all circuits provided over the substrate in a plan view.
12. The semiconductor device according to claim 11 , further comprising:
a further inductor provided in the multi-level interconnect structure so as to surround all external connection terminals provided over the substrate in a plan view,
wherein the inductor is provided over the further inductor.
13. The semiconductor device according to claim 12 ,
wherein the external connection terminal is a pad.
14. The semiconductor device according to claim 11 ,
wherein the inductor is provided so as to surround all transistors included in the circuits for connecting thereto.
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US14/638,287 US9922926B2 (en) | 2009-03-13 | 2015-03-04 | Semiconductor device for transmitting electrical signals between two circuits |
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2010
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2013
- 2013-03-07 US US13/788,542 patent/US20130181324A1/en not_active Abandoned
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2015
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Also Published As
Publication number | Publication date |
---|---|
JP5578797B2 (en) | 2014-08-27 |
US9922926B2 (en) | 2018-03-20 |
US20100230783A1 (en) | 2010-09-16 |
US8410493B2 (en) | 2013-04-02 |
JP2010219122A (en) | 2010-09-30 |
US20150179572A1 (en) | 2015-06-25 |
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