US20130135051A1 - Switch with reduced insertion loss - Google Patents
Switch with reduced insertion loss Download PDFInfo
- Publication number
- US20130135051A1 US20130135051A1 US13/446,115 US201213446115A US2013135051A1 US 20130135051 A1 US20130135051 A1 US 20130135051A1 US 201213446115 A US201213446115 A US 201213446115A US 2013135051 A1 US2013135051 A1 US 2013135051A1
- Authority
- US
- United States
- Prior art keywords
- well
- transistor
- amplifier
- circuit
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
- H03F3/16—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G1/00—Details of arrangements for controlling amplification
- H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
- H03G1/0088—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using discontinuously variable devices, e.g. switch-operated
Definitions
- the invention relates to the design and implementation of switches, and more specifically to the design and implementation of switches with reduced insertion loss.
- RF switches at millimeter-wave (mmWave) frequencies are fabricated using GaAs metal epitaxial semiconductor field effect transistors (MESFETs) or PIN diodes, either as discrete components, or on a GaAs integrated circuit.
- MSFETs metal epitaxial semiconductor field effect transistors
- PIN diodes either as discrete components, or on a GaAs integrated circuit.
- GaAs and other III-V semiconductor materials are more expensive than silicon and typically require higher supply voltages and consume more power then Si integrated circuits (ICs).
- ICs Si integrated circuits
- CMOS complementary metal-oxide-semiconductor
- An illustrative embodiment of the present invention includes a circuit comprising an amplifier having an input and an output; and at least one transistor comprising at least one terminal and at least one isolated well.
- the input of the amplifier is electrically connected to the at least one terminal of the transistor; and the output of the amplifier is electrically connected to the at least one isolated well of the at least one transistor.
- Another illustrative embodiment of the present invention includes a design structure embodied in a machine readable medium, the design structure comprising an amplifier having an input and an output; and at least one transistor comprising at least one terminal and at least one isolated well.
- the input of the amplifier is electrically connected to the at least one terminal of the transistor; and the output of the amplifier is electrically connected to the at least one isolated well of the at least one transistor.
- FIG. 1 shows a switch similar to that described in the prior art
- FIG. 2 shows another switch similar to that described in the prior art
- FIG. 3 is a cross-section of an exemplary triple-well NFET suitable for use in an illustrative embodiment of the present invention
- FIG. 4 is a schematic representation of the exemplary triple-well NFET shown in FIG. 3 ;
- FIG. 5 shows an exemplary switching circuit according to an aspect of the present invention
- FIG. 6 shows a preferred embodiment in which the switch shown in FIG. 5 is implemented using a BiCMOS process
- FIG. 7 shows a simulation of the signal transmission of the circuit in FIG. 6 ;
- FIG. 8 shows an exemplary switching circuit according to a further aspect of the invention.
- FIG. 9 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test.
- CMOS switch CMOS switch
- illustrative embodiments of the present invention may be particularly well-suited for use in a high-frequency and/or millimeter-wave receiver or transceiver
- illustrative embodiments of the present invention may be used in a variety of contexts, including a broad range of communications, radar, and radiometry applications.
- FIG. 1 shows an exemplary switch similar to that described in Z. Li et al., “5.8-GHz CMOS T/R Switches With High and Low Substrate Resistances in a 0.18- ⁇ m CMOS Process,” IEEE Microwave and Wireless Component Letters, vol. 13, no. 1, pp. 1-3, January 2003, the disclosure of which is incorporated by reference herein.
- This switch reduces the loss related to the gate capacitance of n-channel field effect transistor FET (through the channel and gate resistances) by including biasing resistor R bias in series with the gate terminal of the NFET. This allows the gate to follow the RF signal, increasing the effective shunt resistance seen by the signal.
- the loss related to the channel, source-, and drain-to-substrate capacitances remains, and this component of loss can become significant at mmWave frequencies. More specifically, the insertion loss due to the source-, drain-, and channel-to-substrate capacitances varies depending on the effective value of substrate resistance R sub , with loss decreasing as R sub increases.
- the substrate resistance depends on substrate resistivity and layout, but high-resistivity substrates which reduce the loss due to this mechanism are more expensive and exacerbate latch-up issues in CMOS.
- FIG. 2 shows an exemplary switch similar to that described in N. A. Talwalkar et al., “Integrated CMOS Transmit-Receive Switch Using LC-Tuned Substrate Bias for 2.4-GHz and 5.2-GHz Applications”, IEEE JSSC , vol. 39, no. 4, pp. 863-870, June 2004, the disclosure of which is incorporated therein.
- this switch includes biasing resistor R bias in series with the gate terminal of the NFET.
- the effective substrate resistance R sub is increased by inserting a parallel resonant circuit, an LC tank comprising inductor L and capacitor C, in series with the substrate ground connection. This increases the effective substrate resistance at the frequency at which L and C resonate.
- this technique is limited by the quality-factor (Q) of on-chip inductor L.
- triple-well NFETs are used as series switches in a SPDT arrangement, and the P-wells under the NFET channels are allowed to float by biasing the P-wells through a relatively large (5 k ⁇ ) resistor.
- a relatively large resistor 5 k ⁇ resistor.
- capacitances are significant at mmWave frequencies, and they couple the NFET source, drain, and channel to ground through the effective substrate resistance, which results in significant signal loss.
- FIG. 3 is a cross-section of an exemplary “triple-well” or “deep N-well” NFET available in many advanced CMOS and BiCMOS processes and suitable for use in this invention.
- a deep N-well diffusion isolates the P-well (or bulk) under the gate or channel (G), drain (D), and source (S) terminals of the NFET from the P-substrate below, allowing both P-well and N-well to be biased or driven with a signal at potentials different from that of P-substrate.
- FIG. 4 is a schematic representation of the exemplary triple-well NFET shown in FIG. 3 . Because the entire substrate need not be floated at the resonant frequency, greater flexibility may be achieved in reducing or eliminating the aforementioned switching loss.
- FIG. 5 is an exemplary single-pull, double-throw (SPDT) switching circuit according to an aspect of the present invention.
- Devices M 1 and M 2 are triple-well NFETs.
- Amplifier AMP drives the N-wells of M 1 and M 2 with a signal which is proportional to the voltage of the RF signal present at RF_COMMON.
- the potential of the N-wells under devices M 1 and M 2 follows the signal present at the source, drain, and channel terminals of M 1 and M 2 , significantly reducing the lossy conduction through the channel-, source-, and drain-to-substrate capacitances and the channel and substrate resistances.
- Triple-well NFETs may be used for M 3 and M 4 as well as for M 1 and M 2 .
- triple-well NFETs for M 3 and M 4 advantageously reduces the insertion loss.
- the switch isolation is also reduced, and the buffer amplifier is also forced to drive a larger capacitive load.
- n is equal to 1 or 2.
- FIG. 6 shows a preferred embodiment in which the switch shown in FIG. 5 is implemented using a 0.13 ⁇ m SiGe BiCMOS process.
- a bipolar junction transistor (BJT) is used in an emitter-follower configuration to implement the buffer amplifier, which is biased at 1.5 mA from a 2.7-V supply (4 mW power consumption).
- the CMOS devices (including triple-well NFET switches M 1 and M 2 ) are operated from a 1.5-V supply.
- the buffer amplifier preferably has a gain of approximately 0.85 at 60 GHz, which results in an insertion loss of 1.3 dB at 60 GHz.
- Biasing resistors R bias and R bias1 each have a resistance of 10 k ⁇
- biasing resistor R bias2 has a resistance of 5 k ⁇
- inductor L match has an inductance of 250 pH
- capacitors C 1 and C 2 each have a capacitor of 200 fF. Without the buffer amplifier, the insertion loss of the SPDT switch is >3 dB. It is to be appreciated that it is readily apparent to one of ordinary skill in the art to use a source-follower configuration to implement the buffer amplifier.
- FIG. 7 shows a simulation of the signal transmission (S 21 ) in dB of the circuit in FIG. 6 from an input signal at RF_COMMON to an output signal at RF_PORT 0 , as a function of the amplifier gain.
- the insertion loss of the SPDT switch shown in FIG. 5 is >3 dB.
- the insertion loss drops to 1.1 dB, and with an amplifier gain of 1, the insertion loss is ⁇ 1 dB.
- amplifier gains of 1.3 or more the switch can actually have insertion gain instead of insertion loss.
- FIG. 8 shows an exemplary switching circuit according to a further aspect of the invention.
- the circuit shown in FIG. 8 is similar to the circuit shown in FIG. 6 .
- matching inductors L match0 , L match1 , L match2 are included at all RF ports, not just at RF_COMMON. These matching inductors are used to tune out the effective shunt capacitance of NFET switches M 1 , M 2 , M 3 and M 4 at the operating frequency of 60 GHz, thereby providing a good impedance match in a 50- ⁇ system.
- the use of three inductors instead of one can provide better impedance matching and increased isolation, at the expense of increased circuit area.
- impedance matching schemes such as series inductors instead of shunt inductors, etc.
- a resonant load is used for the amplifier as shown by the inclusion of inductor L tune , which is selected to resonate with the total effective shunt capacitance of the driven N-wells at the operating frequency of 60 GHz. This therefore tunes out the shunt capacitance at the operating frequency, increasing the load impedance seen by the amplifier, and thereby increasing the amplifier gain.
- NFET Negative-channel Field Effect Transistor
- PFET Positive-channel Field Effect Transistor
- NFET Negative-channel Field Effect Transistor
- PFET Positive-channel Field Effect Transistor
- illustrative embodiments of the present invention may incorporate PFETs in addition to or instead of NFETs.
- the exemplary circuits described herein would require modification to allow for correct biasing of the PFET wells, such modification would be within the scope of one having skill in the art. For example, one could use an active amplifier to drive the n-well of an ordinary PFET or one of the wells of a triple-well PFET to reduce the insertion loss of the PFET switch.
- At least a portion of the circuit of the present invention may be implemented in an integrated circuit.
- a plurality of identical die is typically fabricated in a repeated pattern on a surface of a semiconductor wafer.
- Each die includes a device described herein, and may include other structures and/or circuits.
- the individual die are cut or diced from the wafer, then packaged as an integrated circuit.
- One skilled in the art would know how to dice wafers and package die to produce integrated circuits. Integrated circuits so manufactured are considered part of this invention.
- FIG. 9 shows a block diagram of an exemplary design flow 900 used for example, in semiconductor design, manufacturing, and/or test.
- Design flow 900 may vary depending on the type of integrated circuit (IC) being designed.
- a design flow 900 for building an application specific IC (ASIC) may differ from a design flow 900 for designing a standard component.
- Design structure 920 is preferably an input to a design process 910 and may come from an IC provider, a core developer, or other design company or may be generated by the operator of the design flow, or from other sources.
- Design structure 920 may comprise an embodiment of the invention as shown in FIGS.
- Design structure 920 may be contained on one or more machine readable medium.
- design structure 920 may be a text file or a graphical representation of an embodiment of the invention as shown in FIGS. 5 , 7 and/or 8 .
- Design process 910 preferably synthesizes (or translates) an embodiment of the invention as shown in FIGS. 5 , 6 and/or 8 into a netlist 980 , where netlist 980 is, for example, a list of wires, transistors, logic gates, control circuits, I/O, models, etc. that describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one of machine readable medium. This may be an iterative process in which netlist 980 is resynthesized one or more times depending on design specifications and parameters for the circuit.
- Design process 910 may include using a variety of inputs; for example, inputs from library elements 930 which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications 940 , characterization data 950 , verification data 960 , design rules 970 , and test data files 985 (which may include test patterns and other testing information). Design process 910 may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.
- standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.
- Design process 910 preferably translates an embodiment of the invention as shown in FIGS. 5 , 6 and/or 8 , along with any additional integrated circuit design or data (if applicable), into a second design structure 990 .
- Design structure 990 resides on a storage medium in a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design structures).
- GDSII GDS2
- GL1 GL1, OASIS, map files, or any other suitable format for storing such design structures.
- Design structure 990 may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce an embodiment of the invention as shown in FIGS. 5 , 6 and/or 8 .
- Design structure 990 may then proceed to a stage 995 where, for example, design structure 990 : proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.
Abstract
Description
- This application is a divisional of U.S. patent application Ser. No. 12/123,735 filed on May 20, 2008, the disclosure of which is incorporated by reference herein and which claims the benefit of U.S. Provisional Application No. 60/949,685, filed Jul. 13, 2007, the disclosure of which is incorporated by reference herein.
- The invention disclosed herein was made with U.S. Government support under Contract Nos. N66001-02-C-8014 and N66001-05-C-8013 awarded by the Defense Advanced Research Projects Agency (DARPA). The Government has certain rights in this invention.
- The invention relates to the design and implementation of switches, and more specifically to the design and implementation of switches with reduced insertion loss.
- Traditionally, radio frequency (RF) switches at millimeter-wave (mmWave) frequencies are fabricated using GaAs metal epitaxial semiconductor field effect transistors (MESFETs) or PIN diodes, either as discrete components, or on a GaAs integrated circuit. But GaAs and other III-V semiconductor materials are more expensive than silicon and typically require higher supply voltages and consume more power then Si integrated circuits (ICs). Thus, it is desirable to produce an RF switch in Si with insertion loss comparable to GaAs devices.
- However, it is difficult to produce a low insertion loss switch for radio frequency (RF) signals, especially at millimeter-wave (mmWave) frequencies, in a silicon complementary metal-oxide-semiconductor (CMOS) process because the silicon FETs and the silicon substrate itself are very lossy. Similar problems are associated with a silicon BiCMOS process in which CMOS devices and bipolar junction transistors (BJT) are integrated in a single device. For example, in the arrangement disclosed by U.S. Pat. No. 7,123,898, the disclosure of which is incorporated herein, elaborate circuits are used for biasing the gates of the field effect transistors (FETs) in a single-pull double-throw (SPDT) switch, but no arrangements are made for minimizing substrate-related losses.
- An illustrative embodiment of the present invention includes a circuit comprising an amplifier having an input and an output; and at least one transistor comprising at least one terminal and at least one isolated well. The input of the amplifier is electrically connected to the at least one terminal of the transistor; and the output of the amplifier is electrically connected to the at least one isolated well of the at least one transistor.
- Another illustrative embodiment of the present invention includes a design structure embodied in a machine readable medium, the design structure comprising an amplifier having an input and an output; and at least one transistor comprising at least one terminal and at least one isolated well. The input of the amplifier is electrically connected to the at least one terminal of the transistor; and the output of the amplifier is electrically connected to the at least one isolated well of the at least one transistor.
- These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
-
FIG. 1 shows a switch similar to that described in the prior art; -
FIG. 2 shows another switch similar to that described in the prior art; -
FIG. 3 is a cross-section of an exemplary triple-well NFET suitable for use in an illustrative embodiment of the present invention; -
FIG. 4 is a schematic representation of the exemplary triple-well NFET shown inFIG. 3 ; -
FIG. 5 shows an exemplary switching circuit according to an aspect of the present invention; -
FIG. 6 shows a preferred embodiment in which the switch shown inFIG. 5 is implemented using a BiCMOS process; -
FIG. 7 shows a simulation of the signal transmission of the circuit inFIG. 6 ; -
FIG. 8 shows an exemplary switching circuit according to a further aspect of the invention; -
FIG. 9 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test. - The present invention will be described herein in the context of an exemplary CMOS switch. Although illustrative embodiments of the present invention may be particularly well-suited for use in a high-frequency and/or millimeter-wave receiver or transceiver, illustrative embodiments of the present invention may be used in a variety of contexts, including a broad range of communications, radar, and radiometry applications.
- It is therefore to be understood that the techniques of the present invention are not limited to the methods and apparatus shown and described herein. Rather, alternative methods and apparatus within the scope of this invention will become apparent to those skilled in the art given the teachings herein.
-
FIG. 1 shows an exemplary switch similar to that described in Z. Li et al., “5.8-GHz CMOS T/R Switches With High and Low Substrate Resistances in a 0.18-μm CMOS Process,” IEEE Microwave and Wireless Component Letters, vol. 13, no. 1, pp. 1-3, January 2003, the disclosure of which is incorporated by reference herein. This switch reduces the loss related to the gate capacitance of n-channel field effect transistor FET (through the channel and gate resistances) by including biasing resistor Rbias in series with the gate terminal of the NFET. This allows the gate to follow the RF signal, increasing the effective shunt resistance seen by the signal. However, the loss related to the channel, source-, and drain-to-substrate capacitances (through the channel and substrate resistances) remains, and this component of loss can become significant at mmWave frequencies. More specifically, the insertion loss due to the source-, drain-, and channel-to-substrate capacitances varies depending on the effective value of substrate resistance Rsub, with loss decreasing as Rsub increases. The substrate resistance depends on substrate resistivity and layout, but high-resistivity substrates which reduce the loss due to this mechanism are more expensive and exacerbate latch-up issues in CMOS. -
FIG. 2 shows an exemplary switch similar to that described in N. A. Talwalkar et al., “Integrated CMOS Transmit-Receive Switch Using LC-Tuned Substrate Bias for 2.4-GHz and 5.2-GHz Applications”, IEEE JSSC, vol. 39, no. 4, pp. 863-870, June 2004, the disclosure of which is incorporated therein. As with the switch shown inFIG. 1 , this switch includes biasing resistor Rbias in series with the gate terminal of the NFET. Here, the effective substrate resistance Rsub is increased by inserting a parallel resonant circuit, an LC tank comprising inductor L and capacitor C, in series with the substrate ground connection. This increases the effective substrate resistance at the frequency at which L and C resonate. However, this technique is limited by the quality-factor (Q) of on-chip inductor L. - In M.-C. Yeh et al., “Design and Analysis for a Miniature CMOS SPDT Switch Using Body-Floating Technique to Improve Power Performance”, IEEE MTT, vol. 54, no. 1, pp. 31-39, January 2006, the disclosure of which is incorporated by reference herein, triple-well NFETs are used as series switches in a SPDT arrangement, and the P-wells under the NFET channels are allowed to float by biasing the P-wells through a relatively large (5 kΩ) resistor. However, as will be discussed in the context of
FIG. 6 , even if the P-well is left floating, there are still relatively large capacitances between the P-well and N-well, and between the N-well and substrate. These capacitances are significant at mmWave frequencies, and they couple the NFET source, drain, and channel to ground through the effective substrate resistance, which results in significant signal loss. -
FIG. 3 is a cross-section of an exemplary “triple-well” or “deep N-well” NFET available in many advanced CMOS and BiCMOS processes and suitable for use in this invention. In a triple-well NFET, a deep N-well diffusion isolates the P-well (or bulk) under the gate or channel (G), drain (D), and source (S) terminals of the NFET from the P-substrate below, allowing both P-well and N-well to be biased or driven with a signal at potentials different from that of P-substrate.FIG. 4 is a schematic representation of the exemplary triple-well NFET shown inFIG. 3 . Because the entire substrate need not be floated at the resonant frequency, greater flexibility may be achieved in reducing or eliminating the aforementioned switching loss. -
FIG. 5 is an exemplary single-pull, double-throw (SPDT) switching circuit according to an aspect of the present invention. Devices M1 and M2 are triple-well NFETs. Amplifier AMP drives the N-wells of M1 and M2 with a signal which is proportional to the voltage of the RF signal present at RF_COMMON. Thus, the potential of the N-wells under devices M1 and M2 follows the signal present at the source, drain, and channel terminals of M1 and M2, significantly reducing the lossy conduction through the channel-, source-, and drain-to-substrate capacitances and the channel and substrate resistances. Triple-well NFETs may be used for M3 and M4 as well as for M1 and M2. The use of triple-well NFETs for M3 and M4 advantageously reduces the insertion loss. However, the switch isolation is also reduced, and the buffer amplifier is also forced to drive a larger capacitive load. While the illustrative embodiment shows a single-pull, double-throw switching circuit, it is to be appreciated that it is readily apparent to one of ordinary skill in the art to use an n-pull, double-throw switching circuit, where n is equal to 1 or 2. -
FIG. 6 shows a preferred embodiment in which the switch shown inFIG. 5 is implemented using a 0.13 μm SiGe BiCMOS process. A bipolar junction transistor (BJT) is used in an emitter-follower configuration to implement the buffer amplifier, which is biased at 1.5 mA from a 2.7-V supply (4 mW power consumption). The CMOS devices (including triple-well NFET switches M1 and M2) are operated from a 1.5-V supply. The buffer amplifier preferably has a gain of approximately 0.85 at 60 GHz, which results in an insertion loss of 1.3 dB at 60 GHz. Biasing resistors Rbias and Rbias1 each have a resistance of 10 kΩ, biasing resistor Rbias2 has a resistance of 5 kΩ, inductor Lmatch has an inductance of 250 pH, and capacitors C1 and C2 each have a capacitor of 200 fF. Without the buffer amplifier, the insertion loss of the SPDT switch is >3 dB. It is to be appreciated that it is readily apparent to one of ordinary skill in the art to use a source-follower configuration to implement the buffer amplifier. -
FIG. 7 shows a simulation of the signal transmission (S21) in dB of the circuit inFIG. 6 from an input signal at RF_COMMON to an output signal at RF_PORT0, as a function of the amplifier gain. With no amplifier, and assuming a substrate resistance Rsub of 50 Ω, the insertion loss of the SPDT switch shown inFIG. 5 is >3 dB. With an amplifier gain of 0.9, the insertion loss drops to 1.1 dB, and with an amplifier gain of 1, the insertion loss is <1 dB. With amplifier gains of 1.3 or more, the switch can actually have insertion gain instead of insertion loss. However, it is most practical from a standpoint of circuit complexity and power consumption to implement a simple buffer amplifier with high input impedance and a gain less than unity (a voltage follower). -
FIG. 8 shows an exemplary switching circuit according to a further aspect of the invention. The circuit shown inFIG. 8 is similar to the circuit shown inFIG. 6 . However, matching inductors Lmatch0, Lmatch1, Lmatch2 are included at all RF ports, not just at RF_COMMON. These matching inductors are used to tune out the effective shunt capacitance of NFET switches M1, M2, M3 and M4 at the operating frequency of 60 GHz, thereby providing a good impedance match in a 50-Ω system. The use of three inductors instead of one can provide better impedance matching and increased isolation, at the expense of increased circuit area. Of course, many other impedance matching schemes (such as series inductors instead of shunt inductors, etc.) could be also used within illustrative embodiments of the invention. - Also, a resonant load is used for the amplifier as shown by the inclusion of inductor Ltune, which is selected to resonate with the total effective shunt capacitance of the driven N-wells at the operating frequency of 60 GHz. This therefore tunes out the shunt capacitance at the operating frequency, increasing the load impedance seen by the amplifier, and thereby increasing the amplifier gain.
- The preferred embodiments of the present invention heretofore described use Negative-channel Field Effect Transistor (NFET) devices rather than Positive-channel Field Effect Transistor (PFET) devices. It is generally preferable to use NFETs for RF switches than PFETs because PFETs have lower transconductance than NFETs; the lower PFET transconductance results in a switch which has higher on-state resistance and higher insertion loss. However, illustrative embodiments of the present invention may incorporate PFETs in addition to or instead of NFETs. Although the exemplary circuits described herein would require modification to allow for correct biasing of the PFET wells, such modification would be within the scope of one having skill in the art. For example, one could use an active amplifier to drive the n-well of an ordinary PFET or one of the wells of a triple-well PFET to reduce the insertion loss of the PFET switch.
- At least a portion of the circuit of the present invention may be implemented in an integrated circuit. In forming integrated circuits, a plurality of identical die is typically fabricated in a repeated pattern on a surface of a semiconductor wafer. Each die includes a device described herein, and may include other structures and/or circuits. The individual die are cut or diced from the wafer, then packaged as an integrated circuit. One skilled in the art would know how to dice wafers and package die to produce integrated circuits. Integrated circuits so manufactured are considered part of this invention.
-
FIG. 9 shows a block diagram of anexemplary design flow 900 used for example, in semiconductor design, manufacturing, and/or test.Design flow 900 may vary depending on the type of integrated circuit (IC) being designed. For example, adesign flow 900 for building an application specific IC (ASIC) may differ from adesign flow 900 for designing a standard component.Design structure 920 is preferably an input to adesign process 910 and may come from an IC provider, a core developer, or other design company or may be generated by the operator of the design flow, or from other sources.Design structure 920 may comprise an embodiment of the invention as shown inFIGS. 5 , 7 and/or 8 in the form of schematics or HDL, a hardware-description language (e.g., Verilog, VHDL, C, etc.).Design structure 920 may be contained on one or more machine readable medium. For example,design structure 920 may be a text file or a graphical representation of an embodiment of the invention as shown inFIGS. 5 , 7 and/or 8.Design process 910 preferably synthesizes (or translates) an embodiment of the invention as shown inFIGS. 5 , 6 and/or 8 into anetlist 980, wherenetlist 980 is, for example, a list of wires, transistors, logic gates, control circuits, I/O, models, etc. that describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one of machine readable medium. This may be an iterative process in which netlist 980 is resynthesized one or more times depending on design specifications and parameters for the circuit. -
Design process 910 may include using a variety of inputs; for example, inputs fromlibrary elements 930 which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.),design specifications 940,characterization data 950,verification data 960,design rules 970, and test data files 985 (which may include test patterns and other testing information).Design process 910 may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used indesign process 910 without deviating from the scope and spirit of the invention. The design structure of the invention is not limited to any specific design flow. -
Design process 910 preferably translates an embodiment of the invention as shown inFIGS. 5 , 6 and/or 8, along with any additional integrated circuit design or data (if applicable), into asecond design structure 990.Design structure 990 resides on a storage medium in a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design structures).Design structure 990 may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce an embodiment of the invention as shown inFIGS. 5 , 6 and/or 8.Design structure 990 may then proceed to astage 995 where, for example, design structure 990: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc. - Although illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made by one skilled in the art without departing from the scope or spirit of the invention.
Claims (17)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/446,115 US8466736B1 (en) | 2007-07-13 | 2012-04-13 | Switch with reduced insertion loss |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US94968507P | 2007-07-13 | 2007-07-13 | |
US12/123,735 US8228112B2 (en) | 2007-07-13 | 2008-05-20 | Switch with reduced insertion loss |
US13/446,115 US8466736B1 (en) | 2007-07-13 | 2012-04-13 | Switch with reduced insertion loss |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/123,735 Division US8228112B2 (en) | 2007-07-13 | 2008-05-20 | Switch with reduced insertion loss |
Publications (2)
Publication Number | Publication Date |
---|---|
US20130135051A1 true US20130135051A1 (en) | 2013-05-30 |
US8466736B1 US8466736B1 (en) | 2013-06-18 |
Family
ID=40252617
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/123,735 Active 2029-08-08 US8228112B2 (en) | 2007-07-13 | 2008-05-20 | Switch with reduced insertion loss |
US12/127,379 Expired - Fee Related US7629850B2 (en) | 2007-07-13 | 2008-05-27 | Variable-gain image-reject low-noise amplifier |
US12/127,389 Active 2028-06-02 US7825741B2 (en) | 2007-07-13 | 2008-05-27 | Frequency multipliers using multi-phase oscillation |
US13/446,115 Active US8466736B1 (en) | 2007-07-13 | 2012-04-13 | Switch with reduced insertion loss |
Family Applications Before (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/123,735 Active 2029-08-08 US8228112B2 (en) | 2007-07-13 | 2008-05-20 | Switch with reduced insertion loss |
US12/127,379 Expired - Fee Related US7629850B2 (en) | 2007-07-13 | 2008-05-27 | Variable-gain image-reject low-noise amplifier |
US12/127,389 Active 2028-06-02 US7825741B2 (en) | 2007-07-13 | 2008-05-27 | Frequency multipliers using multi-phase oscillation |
Country Status (1)
Country | Link |
---|---|
US (4) | US8228112B2 (en) |
Families Citing this family (59)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8595538B2 (en) * | 2008-03-03 | 2013-11-26 | Quintic Holdings | Single-clock-based multiple-clock frequency generator |
US7830199B2 (en) * | 2008-07-02 | 2010-11-09 | Analog Devices, Inc. | Dynamically-driven deep n-well circuit |
US7928794B2 (en) * | 2008-07-21 | 2011-04-19 | Analog Devices, Inc. | Method and apparatus for a dynamically self-bootstrapped switch |
US7944290B2 (en) * | 2009-01-26 | 2011-05-17 | Sumitomo Electric Industries, Ltd. | Trans-impedance amplifier |
US8018288B2 (en) * | 2009-04-13 | 2011-09-13 | Intel Corporation | High-linearity low noise amplifier |
US7898325B2 (en) * | 2009-05-28 | 2011-03-01 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Amplifier with bypass switch |
TWI483542B (en) * | 2009-07-10 | 2015-05-01 | Chi Mei Comm Systems Inc | Amplifier circuit |
US8279019B2 (en) | 2010-05-10 | 2012-10-02 | Mediatek Singapore Pte. Ltd. | Millimeter-wave switches and attenuators |
US8279008B2 (en) | 2010-08-06 | 2012-10-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | CMOS millimeter-wave variable-gain low-noise amplifier |
US8427240B2 (en) | 2010-08-06 | 2013-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Low-noise amplifier with gain enhancement |
US8643427B2 (en) * | 2010-10-04 | 2014-02-04 | Mediatek Singapore Pte. Ltd. | Switching device |
US8891266B2 (en) * | 2012-03-13 | 2014-11-18 | International Business Machines Corporation | Monolithic high voltage multiplier having high voltage semiconductor diodes and high-k capacitors |
CN102647171A (en) * | 2012-04-28 | 2012-08-22 | 成都泰格微波技术股份有限公司 | Low power consumption and high isolation single-pole double-throw switch circuit |
US20150056940A1 (en) * | 2013-08-23 | 2015-02-26 | Qualcomm Incorporated | Harmonic trap for common gate amplifier |
WO2015042814A1 (en) * | 2013-09-25 | 2015-04-02 | Huawei Technologies Co., Ltd. | Wideband injection locked frequency multipliers, oscillators and dividers using higher order lc resonant tank |
US10455729B2 (en) | 2014-01-10 | 2019-10-22 | Reno Technologies, Inc. | Enclosure cooling system |
US9496122B1 (en) | 2014-01-10 | 2016-11-15 | Reno Technologies, Inc. | Electronically variable capacitor and RF matching network incorporating same |
US10431428B2 (en) | 2014-01-10 | 2019-10-01 | Reno Technologies, Inc. | System for providing variable capacitance |
US9755641B1 (en) | 2014-01-10 | 2017-09-05 | Reno Technologies, Inc. | High speed high voltage switching circuit |
US9697991B2 (en) | 2014-01-10 | 2017-07-04 | Reno Technologies, Inc. | RF impedance matching network |
US9844127B2 (en) | 2014-01-10 | 2017-12-12 | Reno Technologies, Inc. | High voltage switching circuit |
US9196459B2 (en) | 2014-01-10 | 2015-11-24 | Reno Technologies, Inc. | RF impedance matching network |
US9865432B1 (en) | 2014-01-10 | 2018-01-09 | Reno Technologies, Inc. | RF impedance matching network |
US10097171B2 (en) * | 2014-07-25 | 2018-10-09 | Rfaxis, Inc. | Radio frequency switch with low oxide stress |
US9479160B2 (en) | 2014-12-17 | 2016-10-25 | GlobalFoundries, Inc. | Resonant radio frequency switch |
US9306533B1 (en) | 2015-02-20 | 2016-04-05 | Reno Technologies, Inc. | RF impedance matching network |
US10340879B2 (en) | 2015-02-18 | 2019-07-02 | Reno Technologies, Inc. | Switching circuit |
US11017983B2 (en) | 2015-02-18 | 2021-05-25 | Reno Technologies, Inc. | RF power amplifier |
US9525412B2 (en) | 2015-02-18 | 2016-12-20 | Reno Technologies, Inc. | Switching circuit |
US9729122B2 (en) | 2015-02-18 | 2017-08-08 | Reno Technologies, Inc. | Switching circuit |
TW201642582A (en) * | 2015-05-19 | 2016-12-01 | 穩懋半導體股份有限公司 | Low-noise amplifier |
TW201642583A (en) * | 2015-05-19 | 2016-12-01 | 穩懋半導體股份有限公司 | Power amplifier |
US10692699B2 (en) | 2015-06-29 | 2020-06-23 | Reno Technologies, Inc. | Impedance matching with restricted capacitor switching |
US11335540B2 (en) | 2015-06-29 | 2022-05-17 | Reno Technologies, Inc. | Impedance matching network and method |
US11081316B2 (en) | 2015-06-29 | 2021-08-03 | Reno Technologies, Inc. | Impedance matching network and method |
US11342161B2 (en) | 2015-06-29 | 2022-05-24 | Reno Technologies, Inc. | Switching circuit with voltage bias |
US11150283B2 (en) | 2015-06-29 | 2021-10-19 | Reno Technologies, Inc. | Amplitude and phase detection circuit |
US11342160B2 (en) | 2015-06-29 | 2022-05-24 | Reno Technologies, Inc. | Filter for impedance matching |
US10984986B2 (en) | 2015-06-29 | 2021-04-20 | Reno Technologies, Inc. | Impedance matching network and method |
CN105049015B (en) * | 2015-08-07 | 2018-01-16 | 康希通信科技(上海)有限公司 | The single-pole double throw RF switch and hilted broadsword of single-pole single-throw(SPST RF switch and its composition throw RF switch more |
US9716475B1 (en) * | 2016-01-21 | 2017-07-25 | Peregrine Semiconductor Corporation | Programmable low noise amplifier |
KR102585866B1 (en) * | 2016-06-21 | 2023-10-06 | 삼성전기주식회사 | Resonance apparatus and apparatus for transmiting power wirelessly using the same |
US11315758B2 (en) | 2017-07-10 | 2022-04-26 | Reno Technologies, Inc. | Impedance matching using electronically variable capacitance and frequency considerations |
US11289307B2 (en) | 2017-07-10 | 2022-03-29 | Reno Technologies, Inc. | Impedance matching network and method |
US11521833B2 (en) | 2017-07-10 | 2022-12-06 | Reno Technologies, Inc. | Combined RF generator and RF solid-state matching network |
US11101110B2 (en) | 2017-07-10 | 2021-08-24 | Reno Technologies, Inc. | Impedance matching network and method |
US10483090B2 (en) | 2017-07-10 | 2019-11-19 | Reno Technologies, Inc. | Restricted capacitor switching |
US11476091B2 (en) | 2017-07-10 | 2022-10-18 | Reno Technologies, Inc. | Impedance matching network for diagnosing plasma chamber |
US11398370B2 (en) | 2017-07-10 | 2022-07-26 | Reno Technologies, Inc. | Semiconductor manufacturing using artificial intelligence |
US10714314B1 (en) | 2017-07-10 | 2020-07-14 | Reno Technologies, Inc. | Impedance matching network and method |
US10727029B2 (en) | 2017-07-10 | 2020-07-28 | Reno Technologies, Inc | Impedance matching using independent capacitance and frequency control |
US11114280B2 (en) | 2017-07-10 | 2021-09-07 | Reno Technologies, Inc. | Impedance matching with multi-level power setpoint |
US11393659B2 (en) | 2017-07-10 | 2022-07-19 | Reno Technologies, Inc. | Impedance matching network and method |
EP3751733A4 (en) * | 2018-05-11 | 2021-04-28 | Huawei Technologies Co., Ltd. | Amplifier, amplifying circuit and phase shifter |
DE102018210089A1 (en) | 2018-06-21 | 2019-12-24 | Infineon Technologies Ag | Frequency multiplier and method for frequency multiplication |
KR20200099798A (en) * | 2019-02-15 | 2020-08-25 | 삼성전자주식회사 | Voltage converter suppressing harmonics |
US11349520B2 (en) | 2019-04-21 | 2022-05-31 | Siklu Communication ltd. | Generation of millimeter-wave frequencies for microwave systems |
US11538662B2 (en) | 2019-05-21 | 2022-12-27 | Reno Technologies, Inc. | Impedance matching network and method with reduced memory requirements |
US11437992B2 (en) | 2020-07-30 | 2022-09-06 | Mobix Labs, Inc. | Low-loss mm-wave CMOS resonant switch |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4714894A (en) * | 1985-03-25 | 1987-12-22 | Zdzislaw Gulczynski | Operational amplifier |
US4849651A (en) * | 1988-02-24 | 1989-07-18 | Hughes Aircraft Company | Two-state, bilateral, single-pole, double-throw, half-bridge power-switching apparatus and power supply means for such electronic power switching apparatus |
US5546043A (en) * | 1992-05-07 | 1996-08-13 | Siemens Nixdorf Informationssysteme Aktiengesellschaft | Circuit arrangement for driving an MOS field-effect transistor |
US6720734B2 (en) * | 2002-08-08 | 2004-04-13 | Datex-Ohmeda, Inc. | Oximeter with nulled op-amp current feedback |
US20060119451A1 (en) * | 2004-12-08 | 2006-06-08 | Airoha Technology Corp. | Switching circuits |
US20060176112A1 (en) * | 2001-10-05 | 2006-08-10 | Toshifumi Nakatani | Variable gain amplifying apparatus and wireless communication apparatus |
US7123898B2 (en) * | 2001-10-10 | 2006-10-17 | Peregrine Semiconductor Corporation | Switch circuit and method of switching radio frequency signals |
US20060281418A1 (en) * | 2005-06-10 | 2006-12-14 | Huang Chun-Wen P | Device and methods for high isolation and interference suppression switch-filter |
US7414474B2 (en) * | 2005-09-07 | 2008-08-19 | Flying Mole Corporation | Operational amplifier |
US20080272824A1 (en) * | 2007-05-03 | 2008-11-06 | Chang-Tsung Fu | CMOS RF switch for high-performance radio systems |
US7558334B2 (en) * | 2006-09-01 | 2009-07-07 | Panasonic Corporation | Enhanced hybrid class-S modulator |
US20090289714A1 (en) * | 2008-05-23 | 2009-11-26 | Griffith Zachary M | Operational amplifier |
US20100001351A1 (en) * | 2006-09-21 | 2010-01-07 | Nanyang Technological University | Triple well transmit-receive switch transistor |
US7692473B2 (en) * | 2005-12-28 | 2010-04-06 | Panasonic Corporation | Switch circuits with the ability to control latch-up due to a parasitic element |
Family Cites Families (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4342001A (en) * | 1980-03-17 | 1982-07-27 | Rca Corporation | Differential amplifier having a low-pass characteristic |
US4435652A (en) * | 1981-05-26 | 1984-03-06 | Honeywell, Inc. | Threshold voltage control network for integrated circuit field-effect trransistors |
US5079456A (en) * | 1990-11-05 | 1992-01-07 | Motorola, Inc. | Current monitoring and/or regulation for sense FET's |
DE69217147T2 (en) * | 1991-09-04 | 1997-06-05 | Nec Corp | Radio transceiver |
US5268312A (en) * | 1992-10-22 | 1993-12-07 | Motorola, Inc. | Method of forming isolated wells in the fabrication of BiCMOS devices |
DE69529869T2 (en) * | 1994-08-30 | 2004-02-05 | Matsushita Electric Industrial Co., Ltd., Kadoma | Send / receive switch for radio communication device |
US5568044A (en) * | 1994-09-27 | 1996-10-22 | Micrel, Inc. | Voltage regulator that operates in either PWM or PFM mode |
US5659885A (en) * | 1994-10-20 | 1997-08-19 | National Semiconductor Corporation | Radio frequency switch including voltage multiplier |
WO1998058382A1 (en) * | 1997-06-16 | 1998-12-23 | Hitachi, Ltd. | Semiconductor integrated circuit device |
KR19990025790A (en) * | 1997-09-18 | 1999-04-06 | 이계철 | Multiple Feedback Loop Ring Oscillator and its Delay Cells |
US6229342B1 (en) * | 1998-03-30 | 2001-05-08 | Micron Technology, Inc. | Circuits and method for body contacted and backgated transistors |
US6172566B1 (en) * | 1999-02-17 | 2001-01-09 | Kabushiki Kaisha Toshiba | Low noise amplifier |
US6144254A (en) * | 1999-06-04 | 2000-11-07 | Infineon Technologies Corporation | Low-noise amplifier with switched gain and method |
EP1111773B1 (en) * | 1999-06-29 | 2004-09-22 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor circuit |
US6175274B1 (en) * | 1999-07-26 | 2001-01-16 | Nokia Mobile Phones Limited | Switched gain low noise amplifier |
US6211729B1 (en) * | 1999-09-07 | 2001-04-03 | Agilent Technologies, Inc. | Amplifier circuit with a switch bypass |
US6118338A (en) * | 1999-11-23 | 2000-09-12 | Agilent Technologies | Low noise amplifier circuit with an isolating switch topology |
US6515534B2 (en) * | 1999-12-30 | 2003-02-04 | Intel Corporation | Enhanced conductivity body biased PMOS driver |
IT1319841B1 (en) * | 2000-02-15 | 2003-11-03 | St Microelectronics Srl | HIGH EFFICIENCY BIDIRECTIONAL SURVOLATOR DEVICE. |
US6392487B1 (en) * | 2000-08-02 | 2002-05-21 | Rf Micro Devices, Inc | Variable gain amplifier |
US6586993B2 (en) * | 2000-11-08 | 2003-07-01 | Research In Motion Limited | Impedance matching low noise amplifier having a bypass switch |
US6522195B2 (en) * | 2000-12-07 | 2003-02-18 | Motorola, Inc. | Low noise amplifier having bypass circuitry |
JP4220694B2 (en) | 2001-03-27 | 2009-02-04 | パナソニック株式会社 | High frequency variable gain amplifier |
JP2002344266A (en) * | 2001-05-18 | 2002-11-29 | Matsushita Electric Ind Co Ltd | Variable gain amplifier |
GB2378593B (en) * | 2001-08-03 | 2003-09-17 | Zarlink Semiconductor Ltd | A frequency doubler circuit arrangement |
US6469350B1 (en) | 2001-10-26 | 2002-10-22 | International Business Machines Corporation | Active well schemes for SOI technology |
US6900699B1 (en) * | 2001-11-14 | 2005-05-31 | Berkana Wireless, Inc. | Phase synchronous multiple LC tank oscillator |
US6707344B2 (en) | 2002-01-08 | 2004-03-16 | Maxim Integrated Products, Inc. | High efficiency, low noise frequency tripler and method |
US6882829B2 (en) * | 2002-04-02 | 2005-04-19 | Texas Instruments Incorporated | Integrated circuit incorporating RF antenna switch and power amplifier |
US7057495B2 (en) * | 2002-10-17 | 2006-06-06 | Paksense, Llc | Perishable product electronic label including time and temperature measurement |
JP4091576B2 (en) * | 2004-03-24 | 2008-05-28 | 株式会社東芝 | Semiconductor integrated circuit and frequency modulation device |
JP4143054B2 (en) * | 2004-08-19 | 2008-09-03 | 株式会社東芝 | Voltage generation circuit |
US7205830B2 (en) | 2005-01-04 | 2007-04-17 | International Business Machines Corporation | Analog MOS circuits having reduced voltage stress |
KR100804546B1 (en) | 2005-08-26 | 2008-02-20 | 인티그런트 테크놀로지즈(주) | Linearity improved differential amplifier circuit |
US7904036B2 (en) * | 2005-12-02 | 2011-03-08 | Telefonaktiebolaget Lm Ericsson (Publ) | Modulation method and apparatus |
US7962114B2 (en) * | 2007-01-12 | 2011-06-14 | International Business Machines Corporation | Drain-pumped sub-harmonic mixer for millimeter wave applications |
KR20080071302A (en) * | 2007-01-30 | 2008-08-04 | 삼성전자주식회사 | Apparatus and method for sequential bias of high power amplifier |
US7843248B1 (en) * | 2007-11-01 | 2010-11-30 | Intersil Americas Inc. | Analog switch with overcurrent detection |
-
2008
- 2008-05-20 US US12/123,735 patent/US8228112B2/en active Active
- 2008-05-27 US US12/127,379 patent/US7629850B2/en not_active Expired - Fee Related
- 2008-05-27 US US12/127,389 patent/US7825741B2/en active Active
-
2012
- 2012-04-13 US US13/446,115 patent/US8466736B1/en active Active
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4714894A (en) * | 1985-03-25 | 1987-12-22 | Zdzislaw Gulczynski | Operational amplifier |
US4849651A (en) * | 1988-02-24 | 1989-07-18 | Hughes Aircraft Company | Two-state, bilateral, single-pole, double-throw, half-bridge power-switching apparatus and power supply means for such electronic power switching apparatus |
US5546043A (en) * | 1992-05-07 | 1996-08-13 | Siemens Nixdorf Informationssysteme Aktiengesellschaft | Circuit arrangement for driving an MOS field-effect transistor |
US20060176112A1 (en) * | 2001-10-05 | 2006-08-10 | Toshifumi Nakatani | Variable gain amplifying apparatus and wireless communication apparatus |
US7123898B2 (en) * | 2001-10-10 | 2006-10-17 | Peregrine Semiconductor Corporation | Switch circuit and method of switching radio frequency signals |
US6720734B2 (en) * | 2002-08-08 | 2004-04-13 | Datex-Ohmeda, Inc. | Oximeter with nulled op-amp current feedback |
US20060119451A1 (en) * | 2004-12-08 | 2006-06-08 | Airoha Technology Corp. | Switching circuits |
US20060281418A1 (en) * | 2005-06-10 | 2006-12-14 | Huang Chun-Wen P | Device and methods for high isolation and interference suppression switch-filter |
US7414474B2 (en) * | 2005-09-07 | 2008-08-19 | Flying Mole Corporation | Operational amplifier |
US7692473B2 (en) * | 2005-12-28 | 2010-04-06 | Panasonic Corporation | Switch circuits with the ability to control latch-up due to a parasitic element |
US7558334B2 (en) * | 2006-09-01 | 2009-07-07 | Panasonic Corporation | Enhanced hybrid class-S modulator |
US20100001351A1 (en) * | 2006-09-21 | 2010-01-07 | Nanyang Technological University | Triple well transmit-receive switch transistor |
US20080272824A1 (en) * | 2007-05-03 | 2008-11-06 | Chang-Tsung Fu | CMOS RF switch for high-performance radio systems |
US20090289714A1 (en) * | 2008-05-23 | 2009-11-26 | Griffith Zachary M | Operational amplifier |
Also Published As
Publication number | Publication date |
---|---|
US20090102542A1 (en) | 2009-04-23 |
US8228112B2 (en) | 2012-07-24 |
US20090051394A1 (en) | 2009-02-26 |
US7629850B2 (en) | 2009-12-08 |
US7825741B2 (en) | 2010-11-02 |
US8466736B1 (en) | 2013-06-18 |
US20090015335A1 (en) | 2009-01-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8466736B1 (en) | Switch with reduced insertion loss | |
US8288829B2 (en) | Triple well transmit-receive switch transistor | |
US7053718B2 (en) | Stacked RF power amplifier | |
EP2460271B1 (en) | Switches with bias resistors for even voltage distribution | |
US8103221B2 (en) | High-isolation transmit/receive switch on CMOS for millimeter-wave applications | |
US10735044B2 (en) | Lossless switch for radio frequency front-end module | |
US9900004B2 (en) | Radio frequency switching circuit with distributed switches | |
Li et al. | 15-GHz fully integrated nMOS switches in a 0.13-/spl mu/m CMOS process | |
US9831869B2 (en) | Radio frequency switching circuit with distributed switches | |
US8279019B2 (en) | Millimeter-wave switches and attenuators | |
US20090029654A1 (en) | Using radio frequency transmit/receive switches in radio frequency communications | |
CN110098812B (en) | Dual-band low-noise amplifier applied to GNSS | |
Ahn et al. | A high-power CMOS switch using a novel adaptive voltage swing distribution method in multistack FETs | |
US10749501B2 (en) | High power silicon on insulator switch | |
Madan et al. | Fully integrated switch-LNA front-end IC design in CMOS: A systematic approach for WLAN | |
US8130033B2 (en) | Switching low noise amplifier | |
Kuo et al. | Comparison of shunt and series/shunt nMOS single-pole double-throw switches for X-band phased array T/R modules | |
US8039880B2 (en) | High performance microwave switching devices and circuits | |
CN114362735A (en) | Radio frequency switch circuit and radio frequency switch device | |
Schmiedeke et al. | A fully integrated high IP1dB CMOS SPDT switch using stacked transistors for 2.4 GHz TDD transceiver applications | |
EP3945676B1 (en) | High isolation radio frequency multiplexer | |
Ahn et al. | A novel multi-stack device structure and its analysis for high power CMOS switch design | |
WO2008133620A1 (en) | High power t/r switch using stacked transistors | |
Fan et al. | A high-isolation ku-band SPDT switch in 0.35 μm SiGe BiCMOS technology |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION, DELAWARE Free format text: SECURITY AGREEMENT;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049490/0001 Effective date: 20181127 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:054633/0001 Effective date: 20201022 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:054636/0001 Effective date: 20201117 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001 Effective date: 20201117 |