US20130009320A1 - Semiconductor package and method of manufacturing the same - Google Patents
Semiconductor package and method of manufacturing the same Download PDFInfo
- Publication number
- US20130009320A1 US20130009320A1 US13/200,335 US201113200335A US2013009320A1 US 20130009320 A1 US20130009320 A1 US 20130009320A1 US 201113200335 A US201113200335 A US 201113200335A US 2013009320 A1 US2013009320 A1 US 2013009320A1
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- substrate
- semiconductor
- forming
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- semiconductor package
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/061—Lamination of previously made multilayered subassemblies
Abstract
There are provided a semiconductor package including an antenna formed integrally therewith, and a method of manufacturing the same. The semiconductor package includes: a semiconductor chip; a sealing part sealing the semiconductor chip; a substrate part formed on at least one surface of the sealing part; and an antenna part formed on the sealing part or the substrate part and electrically connected to the semiconductor chip.
Description
- This application claims the priority of Korean Patent Application No. 10-2011-0067437 filed on Jul. 7, 2011, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package including an antenna formed integrally therewith, and a method of manufacturing the same.
- 2. Description of the Related Art
- As a frequency resource for a next generation information communication service, a frequency in the millimeter wave band, a super high frequency band of 30 GHz or more, has been actively studied.
- This frequency in the millimeter wave band has advantages in that a large amount of information may be transferred at high speed using wideband characteristics and that the frequency may be re-used, that is, a band having the same frequency may be used without interference in an adjacent geographical area due to significant electrical wave attenuation in the air. Therefore, many researchers have been interested in the frequency in the millimeter wave band.
- As a result, the development of an information communication service and system using the frequency in the millimeter wave as well as research into, and development of, various components required for the information communication service and system have been conducted.
- In this millimeter wave band, an electrical connection distance between an antenna and a semiconductor chip is very important. That is, when a distance between the antenna and the semiconductor chip increases, loss increases. Therefore, an antenna in the millimeter wave band (particularly, the 60 GHz band) may be electrically connected to the semiconductor chip to be close thereto.
- To this end, according to the related art, an antenna is disposed at a position significantly adjacent to a semiconductor package in which a semiconductor chip is embedded, and the antenna and the semiconductor package are electrically connected to each other at the shortest possible distance.
- In the case of the related art, after the semiconductor package and the antenna are separately manufactured, they are mounted on a substrate and electrical connections are made. Therefore, a manufacturing process is complicated.
- Accordingly, the demand for a structure in which an antenna and a semiconductor package are disposed at a closer distance to one other has increased. In addition, the necessity for a manufacturing method capable of simplifying a process has increased.
- An aspect of the present invention provides a semiconductor package capable of being easily manufactured while minimizing an electrical connection distance between an antenna and a semiconductor chip.
- Another aspect of the present invention provides a method of manufacturing a semiconductor package through a simplified semiconductor manufacturing process.
- Another aspect of the present invention provides a method of manufacturing a semiconductor package capable of producing a compact and thin semiconductor package through a semiconductor manufacturing process.
- According to an aspect of the present invention, there is provided a semiconductor package including: a semiconductor chip; a sealing part sealing the semiconductor chip; a substrate part formed on at least one surface of the sealing part; and an antenna part formed on the sealing part or the substrate part and electrically connected to the semiconductor chip.
- The semiconductor package may further include a via connection part penetrating through the sealing part, and the antenna part and the semiconductor chip may be electrically connected to each other through the via connection part.
- The substrate part may include an upper substrate formed on an upper surface of the sealing part, and a lower substrate formed on a lower surface of the sealing part.
- The antenna part may be formed on an outer surface of the upper substrate.
- The upper substrate may be a multi-layer substrate, and the antenna part may include a plurality of radiators formed on several layers of the upper substrate.
- The antenna part may be formed on an outer surface of the sealing part.
- The antenna part may be formed in a groove formed in the outer surface of the sealing part.
- The substrate part may have fine circuit patterns formed in an inner portion thereof through a semiconductor manufacturing process.
- The semiconductor chip may transceive a high frequency in a millimeter wave band through the antenna part.
- According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor package, the method including: disposing a plurality of semiconductor chips; forming a sealing part sealing the plurality of semiconductor chips; forming a substrate part on at least one surface of the sealing part; and forming an antenna part on the sealing part or the substrate part.
- The disposing of the plurality of semiconductor chips may include arranging semiconductor chips sorted into good products on a carrier.
- The disposing of the plurality of semiconductor chips may include attaching the semiconductor chips to an adhesive layer formed on the carrier.
- The forming of the sealing part may include forming the sealing part using an epoxy mold compound (EMC).
- The method may further include, after the forming of the sealing part, forming a via connection part penetrating through the sealing part.
- The forming of the antenna part may include electrically connecting the antenna part and the semiconductor chips through the via connection part.
- The forming of the substrate part may include forming a multi-layer substrate part on each of upper and lower surfaces of the sealing part.
- The forming of the antenna part may include forming a plurality of radiators on several layers of the substrate part.
- The forming of the antenna part may include forming a groove in an outer surface of the sealing part and forming the antenna part therein.
- The forming of the substrate part may include repeatedly forming fine circuit patterns and insulating layers through a semiconductor manufacturing process.
- The above and other aspects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
-
FIG. 1 is a perspective view schematically showing a semiconductor package according to an embodiment of the present invention; -
FIG. 2 is a cross-sectional view taken along line A-A′ of the semiconductor package shown inFIG. 1 ; -
FIGS. 3A through 3I are views describing a method of manufacturing a semiconductor package according to an embodiment of the present invention; -
FIG. 4 is a flowchart showing a method of manufacturing a semiconductor package according to an embodiment of the present invention; and -
FIGS. 5 and 6 are cross-sectional views schematically showing a semiconductor package according to other embodiments of the present invention. - Prior to a detailed description of the present invention, the terms or words, which are used in the specification and claims to be described below, should not be construed as having typical or dictionary meanings. The terms or words should be construed in conformity with the technical idea of the present invention on the basis of the principle that the inventor(s) can appropriately define terms in order to describe his or her invention in the best way. Embodiments described in the specification and structures illustrated in drawings are merely exemplary embodiments of the present invention. Thus, it is intended that the present invention covers the modifications and variations of this invention, provided they fall within the scope of their equivalents at the time of filing this application.
- Exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals will be used throughout to designate the same or like elements in the accompanying drawings. Moreover, detailed descriptions related to well-known functions or configurations will be ruled out in order not to unnecessarily obscure subject matters of the present invention.
- In the drawings, the shapes and dimensions of some elements may be exaggerated, omitted or schematically illustrated. Also, the size of each element does not entirely reflect an actual size.
- Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
-
FIG. 1 is a perspective view schematically showing a semiconductor package according to an embodiment of the present invention, andFIG. 2 is a cross-sectional view taken along line A-A′ of the semiconductor package shown inFIG. 1 . - As shown in
FIGS. 1 and 2 , asemiconductor package 100 according to the present embodiment includes asemiconductor chip 10, a sealingpart 20 sealing thesemiconductor chip 10, asubstrate part 30 disposed on both surfaces of the sealingpart 20, and anantenna part 40. - The
semiconductor chip 10 includes a plurality ofconnection pads 12 for connecting to the outside and is electrically connected to thesubstrate part 30 and the antenna part 40 (to be described below) through theconnection pads 12. Theconnection pads 12 may have the form of a solder bump. However, the present invention is not limited thereto but may be variously applied. For example, theconnection pads 12 may have the form of a pad for wire bonding. - This
semiconductor chip 10 may perform wireless communications with the outside through theantenna part 40. - The sealing
part 20 encloses theentire semiconductor chip 10 such that thesemiconductor chip 10 is embedded therein, thereby sealing thesemiconductor chip 10. That is, the sealingpart 20 encloses an outer portion of thesemiconductor chip 10 and fixes thesemiconductor chip 10 to thesubstrate part 30, thereby securely protecting thesemiconductor chip 10 from external impacts. - As a method of forming the sealing
part 20, a molding method may be used. In this case, an epoxy mold compound (EMC) may be used as a material of the sealingpart 20. However, the present invention is not limited thereto. That is, various methods such as a printing method, a spin coating method, a jetting method, and the like, may be used for forming the sealingpart 20 as necessary. - The
substrate part 30 may be formed on at least one surface of the sealingpart 20 having thesemiconductor chip 10 embedded therein. The present embodiment describes a case in which thesubstrate part 30 includes each of upper andlower substrates part 20 by way of example. As thesubstrate part 30, various kinds of substrates (for example, a silicon substrate, a ceramic substrate, a printed circuit board (PCB), a flexible substrate, a circuit pattern layer by a semiconductor circuit process, and the like) known in the art may be used. -
Electrode patterns 32 electrically connected to thesemiconductor chip 10 andcircuit patterns 36 electrically connecting theelectrode patterns 32 to each other may be formed on one surface of thesubstrate part 30, that is, a bonding surface between thesubstrate part 30 and the sealingpart 20. - In addition, the
substrate part 30 according to the present embodiment may be a multi-layer substrate configured of a plurality of layers. Thecircuit patterns 36 for forming an electrical connection may be formed between the respective layers. Thesubstrate part 30 may haveexternal electrodes 38 formed on an outer surface thereof, and theexternal electrodes 38 electrically connect thesemiconductor package 100 to the outside. - In addition, the
substrate part 30 according to the present embodiment may include theexternal electrodes 38, theelectrode patterns 32 andconductive vias 34 electrically connecting thecircuit patterns 36 to each other. - Here, the
substrate part 30 according to the present embodiment may be formed through a semiconductor manufacturing process. Therefore, theexternal electrode 38, theelectrode pattern 32, thecircuit pattern 36, the conductive via 34, and the like, formed in thesubstrate part 30 may be formed as fine circuit patterns by the semiconductor manufacturing process. - The
antenna part 40 is formed by disposing a radiator on the outer surface of thesubstrate part 30, that is, a top portion. The form of the radiator may be varied, having a liner, polygonal, circular, or other shape, and may be a dipole or monopole form. - The
antenna part 40 according to the present embodiment may be formed to have a single radiator or be formed by complexly disposing a plurality of radiators on several layers as necessary.FIG. 2 shows a case in which the radiators are formed in parallel with each other on the outer surface of thesubstrate part 30 and an inner portion of thesubstrate part 30. - In addition, the
antenna part 40 may be electrically connected to thesemiconductor chip 10 through thecircuit pattern 36, the via 34, a viaconnection part 25, and the like. - Meanwhile, although the present embodiment describes a case in which the
antenna part 40 is formed in theupper substrate 30 a by way of example, the present invention is not limited thereto. That is, theantenna part 40 may also be disposed on an outer surface of thelower substrate 30 b, that is, a bottom surface of thelower substrate 30 b in order to minimize an electrical connection distance between theantenna part 40 and thesemiconductor chip 10. - In the case of the
semiconductor package 100 configured as described above, theantenna part 40 is formed on the outer surface of thesubstrate part 30 and an electrical connection distance between theantenna part 40 and thesemiconductor chip 10 is significantly short, whereby radiation characteristics and electrical loss of theantenna part 40 may be improved. - Next, a method of manufacturing a semiconductor package according to an embodiment of the present invention will be described.
-
FIGS. 3A through 3I are views describing a method of manufacturing a semiconductor package according to an embodiment of the present invention; andFIG. 4 is a flowchart showing a method of manufacturing a semiconductor package according to an embodiment of the present invention. - With reference to
FIGS. 3A through 4 , a method of manufacturing a semiconductor package according to an embodiment of the present invention in initiated in preparing thesemiconductor chip 10 in operation S10. - A plurality of semiconductor chips formed on a wafer may be cut into individual chips through a known semiconductor manufacturing process and then the individual chips may be sorted into a good product or a bad product.
- Then, as shown in
FIGS. 3A and 3B , the plurality ofsemiconductor chips 10 are disposed in operation S11. Here,FIG. 3B shows a cross-sectional view taken along line B-B′ ofFIG. 3A . - The semiconductor chips 10 may be disposed such that they are uniformly arranged on a
carrier 60 having various shapes. - The
carrier 60 includes anadhesive layer 70 formed on one surface thereof, and the semiconductor chips 10 are mounted on theadhesive layer 70. Here, the semiconductor chips 10 are mounted such that active areas thereof having theconnection pads 12 formed therein may be attached to theadhesive layer 70 of thecarrier 60. - The
adhesive layer 70 may have adhesion changed by light or heat. As an example, adhesive tape may be used. However, the present invention is not limited thereto but may be variously applied. Theadhesive layer 70 may be formed by applying an adhesive resin, or the like, to one surface of thecarrier 60. - The
carrier 60 may be formed of a flat, hard wafer disk. However, this configuration in which thecarrier 60 uses the wafer was deduced because the method of manufacturing thesemiconductor package 100 according to the present embodiment utilizes a semiconductor manufacturing process using a wafer. Therefore, thecarrier 60 according to the present embodiment is not limited to having a circular shape but may be variously shaped according to embodiments of the semiconductor manufacturing process. AlthoughFIG. 3A shows a good chip carrier having the circular shape, thecarrier 60 may have various forms including a rectangular substrate. - After the plurality of
semiconductor chips 10 are mounted on thecarrier 60, the sealingpart 20 is formed in operation S12 as shown inFIG. 3C . - The sealing
part 20 according to the present embodiment covers theentire carrier 60. That is, the sealingpart 20 fills spaces between theindividual semiconductor chips 10. Therefore, when the forming of the sealingpart 20 is completed, all of the semiconductor chips 10 are formed integrally with each other by the sealingpart 20. - After the
carrier 60 on which the semiconductor chips 10 are mounted is disposed within a mold (not shown), the sealingpart 20 according to the present embodiment may be formed by injecting a mold resin into the mold and hardening it. - Next, as shown in
FIG. 3D , one surface of the sealingpart 20 is ground using agrinder 50 in operation S13. Therefore, an unnecessary portion of the sealingpart 20 is removed, whereby the thickness of thesemiconductor package 100 may be reduced. - In addition, in the
semiconductor package 100 according to the present embodiment, a distance between theantenna part 40 and the semiconductor chips 10, permittivity according to the distance, and the like, may be adjusted through the grinding of the sealingpart 20. Therefore, characteristics of theantenna part 40, that is, signal matching characteristics may be optimally adjusted through this operation S13. - Accordingly, the unnecessary portion of the sealing
part 20 may be removed corresponding to optimal signal matching. - Meanwhile, when the adjustment of a thickness of the sealing
part 20 or signal matching is not required to be performed, this operation may be omitted. - Thereafter, as shown in
FIG. 3E , the removing of theadhesive layer 70 is performed in operation S14. This may be easily undertaken by applying heat to theadhesive layer 70 or irradiating theadhesive layer 70 with light to weaken the adhesion thereof. Theadhesive layer 70, attached to the other surface of the sealingpart 20, is removed, such that theconnection pads 12 of the semiconductor chips 10 that have been attached to theadhesive layer 70 are exposed to the outside on the other surface of the sealingpart 20. - Meanwhile, a lower surface of the sealing
part 20 in which the adhesive layer is removed may be continuously supported by thecarrier 60. However, hereinafter, for convenience of description, thecarrier 60 may be omitted in the drawings. - Then, at least one
substrate part 30 may be formed on any one surface of the sealingpart 20. The present embodiment describes a case in which thelower substrate 30 b is first formed in operation S15 by way of example as shown inFIG. 3F . - The sealing
part 20 is disposed in a form in which upper and lower surfaces thereof are inverted. That is, the sealingpart 20 is mounted on the carrier such that theconnection pad 12 of thesemiconductor chip 10 is exposed upwardly. - The
lower substrate 30 b may be formed by repeatedly performing a process of forming thecircuit patterns 36, theelectrode patterns 32, or the like, on the upper surface of the sealingpart 20, on which theconnection pad 12 is exposed, and forming an insulatinglayer 31 thereon again. At this time, theelectrode patterns 32 or thecircuit patterns 36 may be formed to be electrically connected to theconnection pads 12 exposed on the sealingpart 20. - In addition, the
vias 34 penetrating through the insulatinglayers 31 may be formed as necessary to thereby electrically connect the respective insulatinglayers 31, and theexternal electrodes 38 for connection to the outside may be formed on an outer surface of the insulatinglayer 31. - Here, as a method of forming the
circuit pattern 36, the insulatinglayer 31, the via 34, or the like, a semiconductor manufacturing process known in the art, or the like, may be used. Therefore, a detailed description thereof will be omitted. - When the
substrate part 30 is formed using the semiconductor manufacturing process as in the present embodiment, fine circuit patterns may be formed on thesubstrate part 30. In addition, the substrate part may have a significantly reduced thickness as compared to a general printed circuit board (PCB). Therefore, thesemiconductor chip 100 according to the present embodiment may be a chip scale package (CSP). - After the
lower substrate 30 b is formed, the viaconnection part 25 penetrating through the sealingpart 20 is formed in operation S16 as shown inFIG. 3G . At this time, the viaconnection part 25 is formed at a position corresponding to that of thecircuit pattern 36 formed on thelower substrate 30 b. Therefore, the viaconnection part 25 may be electrically connected to thesemiconductor chip 10 through thecircuit pattern 36. - The via
connection part 25 may be formed by drilling a throughhole 23 in the sealingpart 20, so that thecircuit pattern 36 of thelower substrate 30 b is exposed, filling the throughhole 23 with a conductive material (for example, copper, solder, or the like) and hardening the conductive material. The throughhole 23 may be formed using a method such as laser drilling. However, the throughhole 23 is not limited to being formed using laser drilling, but may also be formed using other methods as required. - Meanwhile, the present embodiment describes a case in which the via
connection part 25 is formed after the forming of thelower substrate 30 b by way of example. However, the present invention is not limited thereto. That is, after the sealingpart 20 is formed in operation S12 or S13, the viaconnection part 25 is first formed in the sealingpart 20 before the forming of thelower substrate 30 b. - Next, as shown in
FIG. 3H , theupper substrate 30 a is formed on one surface of the sealingpart 20 in operation S17. Theupper substrate 30 a may be formed to have a shape similar to that of the above-mentionedlower substrate 30 b through the same process as that of forming thelower substrate 30 b. - First, the sealing
part 20 is reinverted such that theconnection pad 12 of thesemiconductor chip 10 is directed downwardly. Then, theupper substrate 30 a may be formed by repeatedly performing a process of forming thecircuit patterns 36, theelectrode patterns 32, or the like, on the upper surface of the sealingpart 20 and forming the insulatinglayer 31 thereon again. - In this operation, the
antenna part 40 may be formed on theupper substrate 30 a. - The
antenna part 40 may have the form of thecircuit pattern 36 in a process of forming thecircuit pattern 36 of theupper substrate 30 a. In addition, theantenna part 40 may be electrically connected to thesemiconductor chip 10 through the via 34 formed in theupper substrate 30 a, the viaconnection part 25 formed in the sealingpart 20, or the like. - Since the
antenna part 40 as well as thesubstrate part 30 may be formed during the process of forming thesubstrate part 30 as described above, a manufacturing process may be facilitated as compared to the case of the related art in which theantenna part 40 is separately manufactured and then coupled to thesubstrate part 30. - Further, in the
antenna part 40 according to the present embodiment, at least one radiator may have the form of thecircuit pattern 36 in the inner portion of theupper substrate 30 a as well as on the outer surface of theupper substrate 30 a in order to secure radiation characteristics and impedance bandwidth required for wireless communications. - After the
upper substrate 30 a is formed, theindividual semiconductor packages 100 are formed in operation S18 as shown inFIG. 3I . The semiconductor chips 10 are separated by being cut therebetween using acutting blade 80, a laser beam, or the like, such that the semiconductor chips 10 formed integrally by the sealingpart 20 are individually separated. As a result, theindividual semiconductor packages 100 as shown inFIG. 1 are formed. - With the semiconductor package and the method of manufacturing the same according to the present embodiment configured as described above, only good semiconductor chips are sorted from the
individual semiconductor chips 10 and are rearranged to manufacture the semiconductor package, whereby reliability may be secured. - In addition, the
substrate part 30 formed on both surfaces (that is, upper and lower surfaces) of thesemiconductor package 100 is utilized, whereby the semiconductor package may be miniaturized and system in package may be implemented. - Further, the sealing of the
semiconductor chip 10 is used to thereby protect thesemiconductor chip 10 from the outside, whereby the semiconductor chips 10 having various forms such as a flip chip, a chip using a wire bonding scheme, or the like, may be utilized. - Furthermore, in the
semiconductor package 100 according to the present embodiment, theantenna part 40 and thesemiconductor chip 10 are disposed adjacent to each other to be formed integrally, whereby an electrical connection distance between thesemiconductor chip 10 and theantenna part 40 may be minimized. Therefore, when thesemiconductor package 100 according to the present embodiment is used in the millimeter wave band (particularly, 60 GHz band), loss generated between theantenna part 40 and thesemiconductor chip 10 may be minimized. - In addition, the method of manufacturing a semiconductor package according to the present embodiment forms the
antenna part 40 during the process of forming thesubstrate part 30, whereby the number of manufacturing processes and a manufacturing costs may be reduced as compared to the case of the related art in which the antenna part is separately manufactured and then coupled to the substrate part. - Further, the method of manufacturing a semiconductor package according to the present embodiment uses a semiconductor manufacturing process. Therefore, the semiconductor manufacturing equipment according to the related art may be utilized, whereby a requirement for investment in new equipment for manufacturing the semiconductor package may be minimized. In addition, fine circuit patterns are formed on a substrate through the semiconductor manufacturing process, whereby the
semiconductor package 100 may be miniaturized and thinned. Further, a general semiconductor manufacturing process is utilized, whereby the semiconductor package may be easily manufactured. - In addition, a sealing technology having high reliability is used, whereby reliability for packaging of the
semiconductor chip 10 may be secured. - Furthermore, the sealing
part 20 is ground to adjust a thickness thereof and theantenna part 40 is then formed, whereby characteristics of theantenna part 40 may be adjusted. Therefore, the signal matching of theantenna part 40 may be performed during a manufacturing process. - Meanwhile, although the present embodiment describes the
substrate part 30 as being formed on both surfaces with respect to asingle semiconductor chip 10, the present invention is not limited thereto. In the case in which a plurality ofsemiconductor chips 10 are embedded such as the case in which the semiconductor chips 10 are stacked, or the like, a ratio of a system in package may be increased. - The semiconductor package and the method of manufacturing the same according to the present invention may be variously applied.
-
FIGS. 5 and 6 are cross-sectional views schematically showing a semiconductor package according to other embodiments of the present invention. - First, referring to
FIG. 5 , asemiconductor package 200 according to the present embodiment is different from thesemiconductor package 100 according to the above-mentioned embodiment in terms of a configuration in which a plurality ofsemiconductor chips semiconductor chip 10 is electrically connected to thesubstrate part 30 through a wire bonding scheme, and a configuration in which theantenna part 40 is directly formed on the sealingpart 20 rather than theupper substrate 30 a (SeeFIG. 2 ). - Particularly, in the
semiconductor package 200 according to the present embodiment, after the thickness of the sealingpart 20 may be adjusted using a grinder, or the like, and agroove 27 may be formed using a laser beam, or the like, a radiator of theantenna part 40 may be then formed to have a circuit pattern form in thegroove 27. - Meanwhile, when a depth of the
groove 27 is variously formed using the laser beam, or the like, and theantenna part 40 is then formed in an inner portion of thegroove 27 as shown inFIG. 5 , the radiator of theantenna part 40 may have various thicknesses. - The above-mentioned configuration may be realized by adding the forming of the
groove 27 in one surface of the sealingpart 20. The forming of thegroove 27 may be undertaken after operation S13 of grinding one surface of the sealingpart 20 as described above or may be performed without operation S13. - As described above, the
semiconductor package 200 according to the present embodiment may utilize the semiconductor chips 10 having various shapes, and thesubstrate part 30 having various shapes. - In the case in which the
antenna part 40 is formed as described above, the depth of thegroove 27 in which theantenna part 40 is formed is adjusted, whereby characteristics of theantenna part 40 may be adjusted. - However, the present invention is not limited thereto. For example, the
antenna part 40 may also be formed without forming thegroove 27 in the sealingpart 20. In this case, the number of manufacturing processes may be reduced. - Referring to
FIG. 6 , asemiconductor package 300 according to the present embodiment is different from the semiconductor package 100 (SeeFIG. 2 ) according to the above-mentioned embodiment only in that an active area of thesemiconductor chip 10 in which theconnection pad 12 is formed is disposed to face theupper substrate 30 a. In the case in which thesemiconductor package 300 is configured as described above, an electrical distance between thesemiconductor chip 10 and theantenna part 40 is shorter than that of the above-mentionedsemiconductor package 100 shown inFIG. 2 . - In addition, the via
connection part 25 that has been used to electrically connect thesemiconductor chip 10 and theantenna part 40 to each other is not used, whereby electrical loss may be further reduced. - The semiconductor package and the method of manufacturing the same according to the present invention as described above are not limited to the above-mentioned embodiments but may be variously applied. For example, although the above-mentioned embodiments describe a case in which the substrate part is formed through the semiconductor manufacturing process by way of example, various methods may be applied thereto. For example, the substrate part may also be formed using a general method of manufacturing a printed circuit board.
- In addition, although the above-mentioned embodiments describe a case in which the semiconductor package is manufactured by disposing the semiconductor chips on the carrier by way of example, the present invention is not limited thereto.
- That is, a separate substrate (hereinafter, referred to as a support substrate) rather than the carrier may also be used. A detailed description thereof will be provided below.
- The semiconductor chips may be mounted on the support substrate, on which electrode patterns are formed, instead of the carrier. In this case, the separate adhesive layer 70 (See
FIG. 3B ) is not used unlike in the case of the above-mentioned embodiment, and the respective semiconductor chips may be mounted on the support substrate while having separate connection pads directly bonded to the electrode patterns formed on the support substrate. - In addition, a support substrate on which circuit patterns or electrode patterns are not formed may also be formed. In this case, the semiconductor chips are mounted on and fixed to one surface of the support substrate, through holes are formed in the support substrate at positions corresponding to positions at which the connection pads of the semiconductor chips are disposed, and circuit patterns formed on the other surface of the support substrate are electrically connected to the connection pads through the through holes.
- Therefore, when the support substrate is used as described above, the process of removing the adhesive layer in the above-mentioned embodiment may be omitted, and the support substrate may be directly formed as the substrate part. In addition, the substrate part may be formed as a multi-layer substrate by repeatedly forming new insulating layers and circuit patterns on the outer surface of the support substrate as necessary.
- As set forth above, with the semiconductor package and the method of manufacturing the same according to the embodiments of the present invention, only good semiconductor chips are sorted among the individual semiconductor chips and then rearranged to manufacture the semiconductor package, whereby reliability of a product may be secured.
- In addition, a scheme of sealing the semiconductor chip to thereby protect the semiconductor chip from the outside is used, whereby all of semiconductor chips having various forms such as a form of a flip chip, a form of a chip using a wire bonding scheme, or the like, may be utilized.
- Further, the antenna part and the semiconductor chip are disposed at a position adjacent to each other to be formed integrally with each other, whereby an electrical connection distance between the semiconductor chip and the antenna part may be minimized. Therefore, when the semiconductor package is used in the millimeter wave band (particularly, 60 GHz band), loss generated between the antenna part and the semiconductor chip may be minimized.
- Furthermore, the method of manufacturing a semiconductor package according to the present embodiment forms the antenna part as well as the substrate part during the process of forming the substrate part, whereby the number of manufacturing processes and a manufacturing cost may be reduced as compared to the case of the related art in which the antenna is separately manufactured and then coupled to the substrate part.
- Further, the semiconductor manufacturing equipment according to the related art is utilized, whereby new equipment investment for manufacturing the semiconductor package may be minimized. In addition, fine circuit patterns are formed on a substrate through the semiconductor manufacturing process, whereby the semiconductor package may be miniaturized and thinned.
- Furthermore, the sealing part is grinded to adjust a thickness of the sealing part, whereby characteristics of the antenna part may be adjusted. Therefore, signal matching of the antenna part may be performed during a manufacturing process.
- While the present invention has been shown and described in connection with the embodiments, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (19)
1. A semiconductor package comprising:
a semiconductor chip;
a sealing part sealing the semiconductor chip;
a substrate part formed on at least one surface of the sealing part; and
an antenna part formed on the sealing part or the substrate part and electrically connected to the semiconductor chip.
2. The semiconductor package of claim 1 , further comprising a via connection part penetrating through the sealing part,
wherein the antenna part and the semiconductor chip are electrically connected to each other through the via connection part.
3. The semiconductor package of claim 1 , wherein the substrate part includes:
an upper substrate formed on an upper surface of the sealing part; and
a lower substrate formed on a lower surface of the sealing part.
4. The semiconductor package of claim 3 , wherein the antenna part is formed on an outer surface of the upper substrate.
5. The semiconductor package of claim 4 , wherein the upper substrate is a multi-layer substrate, and
the antenna part includes a plurality of radiators formed on several layers of the upper substrate.
6. The semiconductor package of claim 1 , wherein the antenna part is formed on an outer surface of the sealing part.
7. The semiconductor package of claim 6 , wherein the antenna part is formed in a groove formed in the outer surface of the sealing part.
8. The semiconductor package of claim 1 , wherein the substrate part has fine circuit patterns formed in an inner portion thereof through a semiconductor manufacturing process.
9. The semiconductor package of claim 1 , wherein the semiconductor chip transceives a high frequency in a millimeter wave band through the antenna part.
10. A method of manufacturing a semiconductor package, the method comprising:
disposing a plurality of semiconductor chips;
forming a sealing part sealing the plurality of semiconductor chips;
forming a substrate part on at least one surface of the sealing part; and
forming an antenna part on the sealing part or the substrate part.
11. The method of claim 10 , wherein the disposing of the plurality of semiconductor chips includes arranging semiconductor chips sorted into good products on a carrier.
12. The method of claim 11 , wherein the disposing of the plurality of semiconductor chips includes attaching the semiconductor chips to an adhesive layer formed on the carrier.
13. The method of claim 10 , wherein the forming of the sealing part includes forming the sealing part using an epoxy mold compound (EMC).
14. The method of claim 10 , further comprising, after the forming of the sealing part, forming a via connection part penetrating through the sealing part.
15. The method of claim 14 , wherein the forming of the antenna part includes electrically connecting the antenna part and the semiconductor chips through the via connection part.
16. The method of claim 10 , wherein the forming of the substrate part includes forming a multi-layer substrate part on each of upper and lower surfaces of the sealing part.
17. The method of claim 16 , wherein the forming of the antenna part includes forming a plurality of radiators on several layers of the substrate part.
18. The method of claim 10 , wherein the forming of the antenna part includes forming a groove in an outer surface of the sealing part and forming the antenna part therein.
19. The method of claim 10 , wherein the forming of the substrate part includes repeatedly forming fine circuit patterns and insulating layers through a semiconductor manufacturing process.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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US13/935,148 US9496219B2 (en) | 2011-07-07 | 2013-07-03 | Semiconductor package including an antenna formed in a groove within a sealing element |
US15/277,156 US20170018513A1 (en) | 2011-07-07 | 2016-09-27 | Semiconductor package including an antenna formed in a groove within a sealing element |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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KR10-2011-0067437 | 2011-07-07 | ||
KR1020110067437A KR101434003B1 (en) | 2011-07-07 | 2011-07-07 | Semiconductor package and manufacturing method thereof |
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US13/935,148 Division US9496219B2 (en) | 2011-07-07 | 2013-07-03 | Semiconductor package including an antenna formed in a groove within a sealing element |
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US20130009320A1 true US20130009320A1 (en) | 2013-01-10 |
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US13/775,337 Abandoned US20130217181A1 (en) | 2011-07-07 | 2013-02-25 | Method of manufacturing semiconductor package |
US13/935,148 Active US9496219B2 (en) | 2011-07-07 | 2013-07-03 | Semiconductor package including an antenna formed in a groove within a sealing element |
US15/277,156 Abandoned US20170018513A1 (en) | 2011-07-07 | 2016-09-27 | Semiconductor package including an antenna formed in a groove within a sealing element |
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Application Number | Title | Priority Date | Filing Date |
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US13/775,337 Abandoned US20130217181A1 (en) | 2011-07-07 | 2013-02-25 | Method of manufacturing semiconductor package |
US13/935,148 Active US9496219B2 (en) | 2011-07-07 | 2013-07-03 | Semiconductor package including an antenna formed in a groove within a sealing element |
US15/277,156 Abandoned US20170018513A1 (en) | 2011-07-07 | 2016-09-27 | Semiconductor package including an antenna formed in a groove within a sealing element |
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Also Published As
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US20130292809A1 (en) | 2013-11-07 |
KR101434003B1 (en) | 2014-08-27 |
US20130217181A1 (en) | 2013-08-22 |
US9496219B2 (en) | 2016-11-15 |
US20170018513A1 (en) | 2017-01-19 |
KR20130005811A (en) | 2013-01-16 |
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