US20120267779A1 - Semiconductor package - Google Patents

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Publication number
US20120267779A1
US20120267779A1 US13/430,439 US201213430439A US2012267779A1 US 20120267779 A1 US20120267779 A1 US 20120267779A1 US 201213430439 A US201213430439 A US 201213430439A US 2012267779 A1 US2012267779 A1 US 2012267779A1
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United States
Prior art keywords
conductive
semiconductor package
conductive bump
semiconductor
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US13/430,439
Inventor
Tzu-Hung Lin
Wen-Sung Hsu
Tai-Yu Chen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by MediaTek Inc filed Critical MediaTek Inc
Priority to US13/430,439 priority Critical patent/US20120267779A1/en
Assigned to MEDIATEK INC. reassignment MEDIATEK INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, TAI-YU, HSU, WEN-SUNG, LIN, TZU-HUNG
Priority to CN2012101209335A priority patent/CN102760712A/en
Priority to TW101114477A priority patent/TWI543313B/en
Publication of US20120267779A1 publication Critical patent/US20120267779A1/en
Priority to US15/189,369 priority patent/US10109608B2/en
Abandoned legal-status Critical Current

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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/07—Polyamine or polyimide
    • H01L2924/07025—Polyimide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Definitions

  • the present invention relates to a semiconductor package, and in particular, to a conductive bump design for a semiconductor package.
  • I/O connections For a semiconductor chip package design, an increased amount of input/output (I/O) connections for multi-functional chips is required. The impact of this will be pressure on printed circuit board (PCB) fabricators to minimize linewidth and space or to develop direct chip attach (DCA) semiconductors.
  • PCB printed circuit board
  • DCA direct chip attach
  • the increased amount of input/output connections of a multi-functional chip package may induce thermal electrical problems, for example, problems with heat dissipation, cross talk, signal propagation delay, electromagnetic interference for RF circuits, etc.
  • the thermal electrical problems may affect the reliability and quality of products.
  • a semiconductor package is provided.
  • An exemplary embodiment of a semiconductor package comprises a semiconductor die having a central area and a peripheral area surrounding the central area.
  • a first conductive bump is disposed on the semiconductor die in the central area.
  • a second conductive bump is disposed on the semiconductor die in the peripheral area, wherein an area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.
  • FIG. 1 a shows a cross section view of one exemplary embodiment of a semiconductor package of the invention.
  • FIG. 1 b shows a schematic view of a layout of conductive bumps of one exemplary embodiment of a semiconductor package of the invention.
  • FIG. 2 a shows a cross section view of another exemplary embodiment of a semiconductor package of the invention.
  • FIG. 2 b shows a schematic view of a layout of conductive bumps of another exemplary embodiment of a semiconductor package of the invention.
  • FIG. 3 a shows a cross section view of yet another exemplary embodiment of a semiconductor package of the invention.
  • FIG. 3 b shows a schematic view of a layout of conductive bumps of yet another exemplary embodiment of a semiconductor package of the invention.
  • FIG. 4 a shows a cross section view of still yet another exemplary embodiment of a semiconductor package of the invention.
  • FIG. 4 b shows a schematic view of a layout of conductive bumps of still yet another exemplary embodiment of a semiconductor package of the invention.
  • FIG. 1 a shows a cross section view of one exemplary embodiment of a semiconductor package 500 a of the invention.
  • a semiconductor package 500 a is a flip chip package using copper pillars connecting to a semiconductor die and a substrate.
  • one exemplary embodiment of a semiconductor package 500 a comprises a semiconductor die 310 having a central area 302 and a peripheral area 304 surrounding the central area 310 .
  • the metal pads 202 and 204 belong to the uppermost metal layer of the interconnection structure (not shown) of the semiconductor die 310 .
  • the metal pads 204 arranged in the central area 302 are used to transmit ground or power signals of the semiconductor die 310
  • the metal pads 202 arranged in the peripheral area 304 are used to transmit signals of the semiconductor die 310 . Therefore, the metal pads 204 may serve as ground or power pads, and the metal pads 202 may serve as signal pads.
  • a minimum pitch of the metal pads 204 in the central area 302 may be designed larger than a minimum pitch designed for the metal pads 202 in the peripheral area 304 , which also serves as the minimum pitch for the metal pads of the design rule of the semiconductor package 500 a.
  • a first passivation layer 206 is conformably formed covering the metal pads 202 and 204 by a deposition and patterning processes.
  • the first passivation layer 206 may comprise oxide, nitride, or oxynitride.
  • the first passivation layer 206 has openings on the metal pads 202 and 204 , so that a portion of the metal pads 202 and 204 are respectively exposed from the openings.
  • a second passivation layer 208 is formed by a coating patterning and curing process.
  • the second passivation layer 208 with openings therethrough may comprise polyimide for providing reliable insulation when the semiconductor die 310 is subjected to various types of environmental stresses.
  • a portion of the metal pads 202 and 204 are respectively exposed from the openings of the second passivation layer 208 .
  • the metal pads 204 are arranged in the central area 302
  • the metal pads 202 are arranged in the peripheral area 304 .
  • under bump metallurgy (UBM) layer patterns 210 a and 210 b are formed on the passivation layer 208 by a deposition method such as a sputtering or plating method and a subsequent anisotropic etching process.
  • the anisotropic etching process is performed after forming conductive pillars.
  • the UBM layer patterns 210 a and 210 b line sidewalls and bottom surfaces of the openings of the passivation layer 208 .
  • the UBM layer patterns 210 a are arranged in the central area 302
  • the UBM layer patterns 210 b are arranged in the peripheral area 304 .
  • the UBM layer patterns 210 a and 210 b extend over a top surface of the passivation layer 208 .
  • the UBM layer patterns 210 a and 210 b are composed of a Ti layer and a Cu layer on the Ti layer.
  • the UBM layer patterns 210 a arranged in the central area 302 are designed in a shape different from that of the UBM layer patterns 210 b arranged in the peripheral area 304 from the top view.
  • the UBM layer patterns 210 a arranged in the central area 302 are designed in a circular shape and the UBM layer patterns 210 b arranged in the peripheral area 304 are designed in a rectangular shape from the top view.
  • the conductive pillars 212 a and 212 b are respectively formed on the UBM layer patterns 210 a and 210 b, filling the openings of the passivation layer 208 .
  • the conductive pillars 212 a are arranged in the central area 302
  • the conductive pillars 212 b are arranged in the peripheral area 304 . Formation positions of the conductive pillars 212 a and 212 b are defined by a dry film photoresist or liquid photoresist patterns (not shown).
  • the conductive pillars 212 a and 212 b are used as a solder joint for subsequent conductive bumps, which are used to transmit input/output (I/O), ground or power signals of the semiconductor die 310 , disposed thereon. Therefore, the conductive pillars 212 a and 212 b may help to increase the mechanical strength of the bump structure. In one embodiment, the conductive pillars 212 a and 212 b may be formed of copper, so that deformation may be prevented during a subsequent solder re-flow process.
  • conductive buffer layers 214 a and 214 b are formed on the conductive pillars 212 a and 212 b by an electroplating method.
  • the conductive buffer layers 214 a are arranged in the central area 302
  • the conductive buffer layers 214 b are arranged in the peripheral area 304 .
  • the conductive buffer layer 240 is an optional element serving as a seed layer, an adhesion layer and a barrier layer for a subsequent conductive bump formed thereon.
  • the conductive buffer layers 214 a and 214 b may comprise Ni.
  • conductive bumps 216 a and 216 b are respectively formed on the conductive buffer layers 214 a and 214 b by electroplating a solder with a patterned photoresist layer or by a screen printing process and a subsequent solder re-flow process.
  • the conductive bumps 216 a are arranged in the central area 302
  • the conductive bumps 216 b are arranged in the peripheral area 304 .
  • the conductive bumps 216 a electrically connect to the metal pads 204 , which are used to transmit ground or power signals of the semiconductor die 310
  • the conductive bumps 216 b electrically connect to the metal pads 202 , which are used to transmit signals of the semiconductor die 310
  • the conductive pillars 212 a / 212 b, the overlying conductive bumps 216 a / 216 b and the conductive buffer layers 214 a / 214 b (optional) therebetween collectively form bump structures.
  • the semiconductor die 310 and the bump structures collectively form a semiconductor package 500 a.
  • FIG. 1 b shows a schematic view of a layout 600 a of conductive bumps 216 a and 216 b of one exemplary embodiment of the semiconductor package 500 a of the invention.
  • an area A 1 of each of the conductive bumps 216 a arranged in the central area 302 is designed to be larger than an area A 2 of the conductive bumps 216 b arranged in the peripheral area 304 to increase thermal conductivity and reduce electrical resistively, thereby improving thermal and electrical properties of the semiconductor package 500 .
  • FIGS. 1 b shows a schematic view of a layout 600 a of conductive bumps 216 a and 216 b of one exemplary embodiment of the semiconductor package 500 a of the invention.
  • an area A 1 of each of the conductive bumps 216 a arranged in the central area 302 is designed to be larger than an area A 2 of the conductive bumps 216 b arranged in the peripheral area 304 to increase thermal conductivity and reduce electrical resistively, thereby improving thermal and electrical properties of the semiconductor package 500
  • an area ratio A 1 /A 2 of each of the conductive bumps 216 a to each of the conductive bumps 216 b from a top view is larger than 1, and less than or equal to 3.
  • the area ratio A 1 /A 2 of each of the conductive bumps 216 a to each of the conductive bumps 216 b from a top view is substantially equal to 1.5.
  • the conductive bumps 216 a arranged in the central area 302 are designed in a shape different from that of the conductive bumps 216 b arranged in the peripheral area 304 from the top view.
  • the conductive bumps 216 a are designed in a circular shape and the conductive bumps 216 b are designed in an oblong shape from the top view.
  • the conductive pillars 212 a arranged in the central area 302 are designed in a shape substantially the same at that of the conductive bumps 216 a.
  • the conductive pillars 212 b arranged in the peripheral area 304 are designed in a shape substantially the same at that of the conductive bumps 216 b from the top view.
  • the conductive pillars 212 a are designed in a circular shape and the conductive pillars 212 b are designed in an oblong shape from the top view.
  • an area of each of the conductive pillars 212 a arranged in the central area 302 is designed substantially the same at that of the area A 1 of each the conductive bumps 216 a.
  • An area of each of the conductive pillars 212 b arranged in the peripheral area 304 is designed substantially the same at that of the area A 2 of each of the conductive bumps 216 b from the top view. Therefore, in one embodiment as shown in FIGS. 1 and 2 , an area ratio A 1 /A 2 of each of the conductive pillars 212 a to each of the conductive pillars 212 b from a top view is larger than 1, and less than or equal to 3. In this embodiment, the area ratio A 1 /A 2 of each of the conductive pillars 212 a to each of the conductive pillars 212 b from a top view is substantially equal to 1.5.
  • the semiconductor package 500 a can be bonded to a substrate 300 , for example, a print circuit board (PCB), as shown in FIG. 1 a .
  • a substrate 300 for example, a print circuit board (PCB), as shown in FIG. 1 a .
  • an underfill material 224 may optionally fill a space between the semiconductor package 500 a and the substrate 300 .
  • the substrate 300 has conductive traces 230 a and 230 b disposed thereon. In this embodiment, the conductive traces 230 a are arranged in the central area 302 , and the conductive traces 230 b are arranged in the peripheral area 304 .
  • the substrate 200 may be formed of by semiconductor materials such as silicon, or organic materials such as bismaleimide triacine, (BT), polyimide or ajinomoto build-up film (ABF).
  • the conductive traces 230 a arranged in the central area 302 may be designed as ground/power trace segments
  • the second conductive traces 230 b arranged in the peripheral area 304 may be designed as signal trace segments for routing.
  • the conductive traces 230 a and 230 b are used for input/output (I/O) connections of a semiconductor die 310 mounted directly onto the substrate 200 . Therefore, each of the conductive traces 230 a and 230 b has a portion serving as a pad region of the substrate 200 .
  • 1 b also shows a relationship between the conductive traces 230 a / 230 b and the conductive bumps 216 a / 216 b of one exemplary embodiment of the semiconductor package 500 of the invention. Terminal portions of the conductive traces 230 a overlap with the conductive bumps 216 a in the central area 302 , and terminal portions of the conductive traces 230 b overlap with the conductive bumps 216 b in the peripheral area 304 .
  • FIG. 2 a shows a cross section view of another exemplary embodiment of a semiconductor package 500 b of the invention.
  • FIG. 2 b shows a schematic view of a layout 600 b of conductive bumps of another exemplary embodiment of a semiconductor package 500 b of the invention. Elements of this embodiment which are the same as those previously described in FIGS. 1 a and 1 b , are not repeated for brevity. Differences between the semiconductor packages 500 a and 500 b (the layouts 600 a and 600 b ) are that the metal pads 204 of the semiconductor package 500 b for power/ground connections are arranged in the peripheral area 304 . Also, the metal pads 202 of the semiconductor package 500 b for power/ground connections are arranged in the central area 302 .
  • the metal pads 202 and 204 can be arranged both in the the central area 302 and the peripheral area 304 . Also, the metal pads 202 and 204 can be alternatively arranged in the central area 302 or the peripheral area 304 .
  • FIG. 3 a shows a cross section view of yet another exemplary embodiment of a semiconductor package 500 c of the invention.
  • FIG. 3 b shows a schematic view of a layout 600 c of conductive bumps of yet another exemplary embodiment of a semiconductor package 500 c of the invention. Elements of this embodiment which are the same as those previously described in FIGS. 1 a and 1 b , are not repeated for brevity.
  • the metal pads adjacent to any one of the metal pads 202 are the metal pads 204 .
  • the metal pads adjacent to any one of the metal pads 204 are the metal pads 202 .
  • the metal pads 202 and 204 can be arranged both in the central area 302 and the peripheral area 304 . Also, the metal pads 202 and 204 can be randomly arranged in the central area 302 or the peripheral area 304 .
  • FIG. 4 a shows a cross section view of still yet another exemplary embodiment of a semiconductor package 500 d of the invention.
  • FIG. 4 b shows a schematic view of a layout 600 d of conductive bumps of still yet another exemplary embodiment of a semiconductor package 500 d of the invention. Elements of this embodiment which are the same as those previously described in FIGS. 1 a and 1 b , are not repeated for brevity.
  • any one of the metal pads 202 can be adjacent to the metal pads 202 or 204 .
  • any one of the metal pads 204 can be adjacent to the metal pads 202 or 204 .
  • Exemplary embodiments provide a semiconductor package.
  • the semiconductor package is designed to arrange conductive bumps with two different areas (sizes) in one semiconductor package. Because the power/ground connections of the semiconductor chip 301 has a number much less than the signal connections, a minimum pitch of the metal pads 204 for power/ground connections may be designed larger than a minimum pitch designed for the metal pads 202 for signal connections.
  • An area A 1 of each of the conductive bumps 216 a connecting the metal pads 204 is designed to be larger than an area A 2 of the conductive bumps 216 b connecting the metal pads 202 to increase thermal conductivity and reduce electrical resistively, thereby improving thermal and electrical properties of the semiconductor package 500 . In one embodiment as shown in FIGS.
  • an area ratio A 1 /A 2 of each of the conductive bumps 216 a to each of the conductive bumps 216 b from a top view is larger than 1, and less than or equal to 3.
  • the area ratio A 1 /A 2 of each of the conductive bumps 216 a to each of the conductive bumps 216 b from a top view is substantially equal to 1.5.
  • the conductive bumps 216 a arranged in the central area 302 are designed in a shape different from that of the conductive bumps 216 b arranged in the peripheral area 304 from the top view.

Abstract

The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application claims the benefit of U.S. Provisional Application No. 61/498,791 filed Apr. 25, 2011, the entirety of which is incorporated by reference herein.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a semiconductor package, and in particular, to a conductive bump design for a semiconductor package.
  • 2. Description of the Related Art
  • For a semiconductor chip package design, an increased amount of input/output (I/O) connections for multi-functional chips is required. The impact of this will be pressure on printed circuit board (PCB) fabricators to minimize linewidth and space or to develop direct chip attach (DCA) semiconductors. However, the increased amount of input/output connections of a multi-functional chip package may induce thermal electrical problems, for example, problems with heat dissipation, cross talk, signal propagation delay, electromagnetic interference for RF circuits, etc. The thermal electrical problems may affect the reliability and quality of products.
  • Thus, a novel semiconductor package with better thermal and electrical properties is desirable.
    • BRIEF SUMMARY OF INVENTION
  • A semiconductor package is provided. An exemplary embodiment of a semiconductor package comprises a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area, wherein an area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.
  • A detailed description is given in the following embodiments with reference to the accompanying drawings.
    • BRIEF DESCRIPTION OF DRAWINGS
  • The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
  • FIG. 1 a shows a cross section view of one exemplary embodiment of a semiconductor package of the invention.
  • FIG. 1 b shows a schematic view of a layout of conductive bumps of one exemplary embodiment of a semiconductor package of the invention.
  • FIG. 2 a shows a cross section view of another exemplary embodiment of a semiconductor package of the invention.
  • FIG. 2 b shows a schematic view of a layout of conductive bumps of another exemplary embodiment of a semiconductor package of the invention.
  • FIG. 3 a shows a cross section view of yet another exemplary embodiment of a semiconductor package of the invention.
  • FIG. 3 b shows a schematic view of a layout of conductive bumps of yet another exemplary embodiment of a semiconductor package of the invention.
  • FIG. 4 a shows a cross section view of still yet another exemplary embodiment of a semiconductor package of the invention.
  • FIG. 4 b shows a schematic view of a layout of conductive bumps of still yet another exemplary embodiment of a semiconductor package of the invention.
    •  DETAILED DESCRIPTION OF INVENTION
  • The following description is a mode for carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. Wherever possible, the same reference numbers are used in the drawings and the descriptions to refer the same or like parts.
  • The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn to scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual dimensions to practice the invention.
  • FIG. 1 a shows a cross section view of one exemplary embodiment of a semiconductor package 500 a of the invention. One exemplary embodiment of a semiconductor package 500 a is a flip chip package using copper pillars connecting to a semiconductor die and a substrate. As shown in FIG. 1 a, one exemplary embodiment of a semiconductor package 500 a comprises a semiconductor die 310 having a central area 302 and a peripheral area 304 surrounding the central area 310. The metal pads 202 and 204 belong to the uppermost metal layer of the interconnection structure (not shown) of the semiconductor die 310. In this embodiment, the metal pads 204 arranged in the central area 302 are used to transmit ground or power signals of the semiconductor die 310, and the metal pads 202 arranged in the peripheral area 304 are used to transmit signals of the semiconductor die 310. Therefore, the metal pads 204 may serve as ground or power pads, and the metal pads 202 may serve as signal pads. In one embodiment, a minimum pitch of the metal pads 204 in the central area 302 may be designed larger than a minimum pitch designed for the metal pads 202 in the peripheral area 304, which also serves as the minimum pitch for the metal pads of the design rule of the semiconductor package 500 a.
  • As shown in FIG. 1 a, a first passivation layer 206 is conformably formed covering the metal pads 202 and 204 by a deposition and patterning processes. In one embodiment, the first passivation layer 206 may comprise oxide, nitride, or oxynitride. The first passivation layer 206 has openings on the metal pads 202 and 204, so that a portion of the metal pads 202 and 204 are respectively exposed from the openings. Also, a second passivation layer 208 is formed by a coating patterning and curing process. In one embodiment, the second passivation layer 208 with openings therethrough may comprise polyimide for providing reliable insulation when the semiconductor die 310 is subjected to various types of environmental stresses. A portion of the metal pads 202 and 204 are respectively exposed from the openings of the second passivation layer 208. In this embodiment, the metal pads 204 are arranged in the central area 302, and the metal pads 202 are arranged in the peripheral area 304.
  • As shown in FIG. 1 a, under bump metallurgy (UBM) layer patterns 210 a and 210 b are formed on the passivation layer 208 by a deposition method such as a sputtering or plating method and a subsequent anisotropic etching process. The anisotropic etching process is performed after forming conductive pillars. Meanwhile, the UBM layer patterns 210 a and 210 b line sidewalls and bottom surfaces of the openings of the passivation layer 208. In this embodiment, the UBM layer patterns 210 a are arranged in the central area 302, and the UBM layer patterns 210 b are arranged in the peripheral area 304. Also, the UBM layer patterns 210 a and 210 b extend over a top surface of the passivation layer 208. In one embodiment, the UBM layer patterns 210 a and 210 b are composed of a Ti layer and a Cu layer on the Ti layer. In one embodiment, the UBM layer patterns 210 a arranged in the central area 302 are designed in a shape different from that of the UBM layer patterns 210 b arranged in the peripheral area 304 from the top view. For example, the UBM layer patterns 210 a arranged in the central area 302 are designed in a circular shape and the UBM layer patterns 210 b arranged in the peripheral area 304 are designed in a rectangular shape from the top view.
  • As shown in FIG. 1 a, the conductive pillars 212 a and 212 b are respectively formed on the UBM layer patterns 210 a and 210 b, filling the openings of the passivation layer 208. In this embodiment, the conductive pillars 212 a are arranged in the central area 302, and the conductive pillars 212 b are arranged in the peripheral area 304. Formation positions of the conductive pillars 212 a and 212 b are defined by a dry film photoresist or liquid photoresist patterns (not shown). In one embodiment, the conductive pillars 212 a and 212 b are used as a solder joint for subsequent conductive bumps, which are used to transmit input/output (I/O), ground or power signals of the semiconductor die 310, disposed thereon. Therefore, the conductive pillars 212 a and 212 b may help to increase the mechanical strength of the bump structure. In one embodiment, the conductive pillars 212 a and 212 b may be formed of copper, so that deformation may be prevented during a subsequent solder re-flow process.
  • As shown in FIG. 1 a, conductive buffer layers 214 a and 214 b are formed on the conductive pillars 212 a and 212 b by an electroplating method. In this embodiment, the conductive buffer layers 214 a are arranged in the central area 302, and the conductive buffer layers 214 b are arranged in the peripheral area 304. In one embodiment, the conductive buffer layer 240 is an optional element serving as a seed layer, an adhesion layer and a barrier layer for a subsequent conductive bump formed thereon. In one embodiment, the conductive buffer layers 214 a and 214 b may comprise Ni.
  • As shown in FIG. 1 a, conductive bumps 216 a and 216 b are respectively formed on the conductive buffer layers 214 a and 214 b by electroplating a solder with a patterned photoresist layer or by a screen printing process and a subsequent solder re-flow process. In this embodiment, the conductive bumps 216 a are arranged in the central area 302, and the conductive bumps 216 b are arranged in the peripheral area 304. In one embodiment, the conductive bumps 216 a electrically connect to the metal pads 204, which are used to transmit ground or power signals of the semiconductor die 310, and the conductive bumps 216 b electrically connect to the metal pads 202, which are used to transmit signals of the semiconductor die 310. In one embodiment of the invention, the conductive pillars 212 a/212 b, the overlying conductive bumps 216 a/216 b and the conductive buffer layers 214 a/214 b (optional) therebetween, collectively form bump structures. Additionally, the semiconductor die 310 and the bump structures collectively form a semiconductor package 500 a.
  • FIG. 1 b shows a schematic view of a layout 600 a of conductive bumps 216 a and 216 b of one exemplary embodiment of the semiconductor package 500 a of the invention. As shown in FIGS. 1 a and 1 b, it is noted that an area A1 of each of the conductive bumps 216 a arranged in the central area 302 is designed to be larger than an area A2 of the conductive bumps 216 b arranged in the peripheral area 304 to increase thermal conductivity and reduce electrical resistively, thereby improving thermal and electrical properties of the semiconductor package 500. In one embodiment as shown in FIGS. 1 and 2, an area ratio A1/A2 of each of the conductive bumps 216 a to each of the conductive bumps 216 b from a top view is larger than 1, and less than or equal to 3. In this embodiment, the area ratio A1/A2 of each of the conductive bumps 216 a to each of the conductive bumps 216 b from a top view is substantially equal to 1.5. In one embodiment, the conductive bumps 216 a arranged in the central area 302 are designed in a shape different from that of the conductive bumps 216 b arranged in the peripheral area 304 from the top view. For example, the conductive bumps 216 a are designed in a circular shape and the conductive bumps 216 b are designed in an oblong shape from the top view. Further, the conductive pillars 212 a arranged in the central area 302 are designed in a shape substantially the same at that of the conductive bumps 216 a. The conductive pillars 212 b arranged in the peripheral area 304 are designed in a shape substantially the same at that of the conductive bumps 216 b from the top view. Accordingly, the conductive pillars 212 a are designed in a circular shape and the conductive pillars 212 b are designed in an oblong shape from the top view. Moreover, an area of each of the conductive pillars 212 a arranged in the central area 302 is designed substantially the same at that of the area A1 of each the conductive bumps 216 a. An area of each of the conductive pillars 212 b arranged in the peripheral area 304 is designed substantially the same at that of the area A2 of each of the conductive bumps 216 b from the top view. Therefore, in one embodiment as shown in FIGS. 1 and 2, an area ratio A1/A2 of each of the conductive pillars 212 a to each of the conductive pillars 212 b from a top view is larger than 1, and less than or equal to 3. In this embodiment, the area ratio A1/A2 of each of the conductive pillars 212 a to each of the conductive pillars 212 b from a top view is substantially equal to 1.5.
  • Additionally, the semiconductor package 500 a can be bonded to a substrate 300, for example, a print circuit board (PCB), as shown in FIG. 1 a. In one embodiment, an underfill material 224 may optionally fill a space between the semiconductor package 500 a and the substrate 300. In one embodiment, the substrate 300 has conductive traces 230 a and 230 b disposed thereon. In this embodiment, the conductive traces 230 a are arranged in the central area 302, and the conductive traces 230 b are arranged in the peripheral area 304. In one embodiment, the substrate 200 may be formed of by semiconductor materials such as silicon, or organic materials such as bismaleimide triacine, (BT), polyimide or ajinomoto build-up film (ABF). In one embodiment, the conductive traces 230 a arranged in the central area 302 may be designed as ground/power trace segments, and the second conductive traces 230 b arranged in the peripheral area 304 may be designed as signal trace segments for routing. Also, the conductive traces 230 a and 230 b are used for input/output (I/O) connections of a semiconductor die 310 mounted directly onto the substrate 200. Therefore, each of the conductive traces 230 a and 230 b has a portion serving as a pad region of the substrate 200. FIG. 1 b also shows a relationship between the conductive traces 230 a/230 b and the conductive bumps 216 a/216 b of one exemplary embodiment of the semiconductor package 500 of the invention. Terminal portions of the conductive traces 230 a overlap with the conductive bumps 216 a in the central area 302, and terminal portions of the conductive traces 230 b overlap with the conductive bumps 216 b in the peripheral area 304.
  • In another embodiment, positions of the metal pads 202 and 204 can be exchanged. FIG. 2 a shows a cross section view of another exemplary embodiment of a semiconductor package 500 b of the invention. FIG. 2 b shows a schematic view of a layout 600 b of conductive bumps of another exemplary embodiment of a semiconductor package 500 b of the invention. Elements of this embodiment which are the same as those previously described in FIGS. 1 a and 1 b, are not repeated for brevity. Differences between the semiconductor packages 500 a and 500 b (the layouts 600 a and 600 b) are that the metal pads 204 of the semiconductor package 500 b for power/ground connections are arranged in the peripheral area 304. Also, the metal pads 202 of the semiconductor package 500 b for power/ground connections are arranged in the central area 302.
  • In yet another embodiment, the metal pads 202 and 204 can be arranged both in the the central area 302 and the peripheral area 304. Also, the metal pads 202 and 204 can be alternatively arranged in the central area 302 or the peripheral area 304. FIG. 3 a shows a cross section view of yet another exemplary embodiment of a semiconductor package 500 c of the invention. FIG. 3 b shows a schematic view of a layout 600 c of conductive bumps of yet another exemplary embodiment of a semiconductor package 500 c of the invention. Elements of this embodiment which are the same as those previously described in FIGS. 1 a and 1 b, are not repeated for brevity. As shown in FIGS. 3 a and 3 b, the metal pads adjacent to any one of the metal pads 202 are the metal pads 204. Also, the metal pads adjacent to any one of the metal pads 204 are the metal pads 202.
  • In still yet another embodiment, the metal pads 202 and 204 can be arranged both in the central area 302 and the peripheral area 304. Also, the metal pads 202 and 204 can be randomly arranged in the central area 302 or the peripheral area 304. FIG. 4 a shows a cross section view of still yet another exemplary embodiment of a semiconductor package 500 d of the invention. FIG. 4 b shows a schematic view of a layout 600 d of conductive bumps of still yet another exemplary embodiment of a semiconductor package 500 d of the invention. Elements of this embodiment which are the same as those previously described in FIGS. 1 a and 1 b, are not repeated for brevity. As shown in FIGS. 4 a and 4 b, any one of the metal pads 202 can be adjacent to the metal pads 202 or 204. Also, any one of the metal pads 204 can be adjacent to the metal pads 202 or 204.
  • Exemplary embodiments provide a semiconductor package. The semiconductor package is designed to arrange conductive bumps with two different areas (sizes) in one semiconductor package. Because the power/ground connections of the semiconductor chip 301 has a number much less than the signal connections, a minimum pitch of the metal pads 204 for power/ground connections may be designed larger than a minimum pitch designed for the metal pads 202 for signal connections. An area A1 of each of the conductive bumps 216 a connecting the metal pads 204 is designed to be larger than an area A2 of the conductive bumps 216 b connecting the metal pads 202 to increase thermal conductivity and reduce electrical resistively, thereby improving thermal and electrical properties of the semiconductor package 500. In one embodiment as shown in FIGS. 1 a and 1 b, an area ratio A1/A2 of each of the conductive bumps 216 a to each of the conductive bumps 216 b from a top view is larger than 1, and less than or equal to 3. In this embodiment, the area ratio A1/A2 of each of the conductive bumps 216 a to each of the conductive bumps 216 b from a top view is substantially equal to 1.5. In one embodiment, the conductive bumps 216 a arranged in the central area 302 are designed in a shape different from that of the conductive bumps 216 b arranged in the peripheral area 304 from the top view.
  • While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (18)

1. A semiconductor package, comprising:
a semiconductor die; and
a first conductive bump and a second conductive bump respectively disposed on the semiconductor die, wherein an area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.
2. The semiconductor package as claimed in claim 1, wherein the semiconductor die has a central area and a peripheral area surrounding the central area, and wherein the first conductive bump is disposed on the semiconductor die in the central area, and the second conductive bump is disposed on the semiconductor die in the peripheral area.
3. The semiconductor package as claimed in claim 1, wherein the semiconductor die has a central area and a peripheral area surrounding the central area, and wherein the first conductive bump is disposed on the semiconductor die in the peripheral area, and the second conductive bump is disposed on the semiconductor die in the central area.
4. The semiconductor package as claimed in claim 1, wherein the first conductive bump and the second conductive bump are alternatively disposed on the semiconductor die.
5. The semiconductor package as claimed in claim 1, wherein the first conductive bump and the second conductive bump are randomly disposed on the semiconductor die.
6. The semiconductor package as claimed in claim 1, wherein the first conductive bump is a circular shape from the top view.
7. The semiconductor package as claimed in claim 1, wherein the second conductive bump is an oblong shape from the top view.
8. The semiconductor package as claimed in claim 1, wherein the first conductive bump connects to a power pad or ground pad of the semiconductor die.
9. The semiconductor package as claimed in claim 1, wherein the second conductive bump connects to a signal pad of the semiconductor die.
10. The semiconductor package as claimed in claim 1, further comprising:
a first under bump metallurgy layer pattern disposed between the semiconductor die and the first conductive bump; and
a second under bump metallurgy layer pattern disposed between the semiconductor die and the second conductive bump.
11. The semiconductor package as claimed in claim 10, wherein the first under bump metallurgy layer pattern is a circular shape from the top view.
12. The semiconductor package as claimed in claim 10, wherein the second under bump metallurgy layer pattern is a rectangular shape from the top view.
13. The semiconductor package as claimed in claim 10, further comprising:
a first conductive pillar connecting to and between the first under bump metallurgy layer pattern and the first conductive bump; and
a second conductive pillar connecting to and between the second under bump metallurgy layer pattern and the second conductive bump.
14. The semiconductor package as claimed in claim 13, wherein the first conductive pillar is a circular shape.
15. The semiconductor package as claimed in claim 13, wherein the second conductive pillar is an oblong shape from the top view.
16. The semiconductor package as claimed in claim 13, wherein an area ratio the first conductive pillar to the second conductive pillar from a top view is larger than 1, and less than or equal to 3.
17. The semiconductor package as claimed in claim 1, further comprising a substrate having a plurality of conductive traces thereon, wherein the first conductive bump and the second conductive bump are bonded onto the conductive traces, respectively.
18. The semiconductor package as claimed in claim 1, further comprising:
a solder resistance layer disposed on the substrate, away from an overlap region between the substrate and the semiconductor die; and
an underfill material filling a gap between the substrate and the semiconductor
US13/430,439 2011-04-25 2012-03-26 Semiconductor package Abandoned US20120267779A1 (en)

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TW101114477A TWI543313B (en) 2011-04-25 2012-04-24 Semiconductor package
US15/189,369 US10109608B2 (en) 2011-04-25 2016-06-22 Semiconductor package

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Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140117998A1 (en) * 2012-11-01 2014-05-01 Samsung Display Co., Ltd. Display device and bonding test system
US20140374900A1 (en) * 2013-06-21 2014-12-25 Heungkyu Kwon Semiconductor package and method of fabricating the same
US20150262950A1 (en) * 2014-03-14 2015-09-17 Lsi Corporation Method for Fabricating Equal Height Metal Pillars of Different Diameters
US9177899B2 (en) 2012-07-31 2015-11-03 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
US20160126161A1 (en) * 2014-10-31 2016-05-05 Mediatek Inc. Semiconductor package
US20160358877A1 (en) * 2012-07-31 2016-12-08 Mediatek Inc. Semiconductor package using flip-chip technology
US20170162545A1 (en) * 2015-12-07 2017-06-08 Samsung Electronics Co., Ltd. Stacked semiconductor device and a method of manufacturing the same
US20180211743A1 (en) * 2014-04-18 2018-07-26 Canon Kabushiki Kaisha Printed circuit board
US10109608B2 (en) 2011-04-25 2018-10-23 Mediatek Inc. Semiconductor package
US20180342476A1 (en) * 2017-05-23 2018-11-29 Micron Technology, Inc. Semiconductor device assembly with surface-mount die support structures
US20180342475A1 (en) * 2017-05-23 2018-11-29 Micron Technology, Inc. Semiconductor device assembly with die support structures
WO2019066902A1 (en) * 2017-09-29 2019-04-04 Intel Corporation Pillar array plate
US10366968B2 (en) * 2016-09-30 2019-07-30 Intel IP Corporation Interconnect structure for a microelectronic device
US10573615B2 (en) 2012-07-31 2020-02-25 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
US10658282B2 (en) * 2018-08-03 2020-05-19 Unimicron Technology Corp. Package substrate structure and bonding method thereof
US20200198962A1 (en) * 2015-09-29 2020-06-25 Tronic's Microsystems Device for Attaching Two Elements Such as a Chip, an Interposer and a Support
US20210408354A1 (en) * 2020-06-29 2021-12-30 Nec Corporation Quantum device

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101563911B1 (en) * 2013-10-24 2015-10-28 앰코 테크놀로지 코리아 주식회사 Semiconductor package
US9806046B2 (en) * 2014-03-13 2017-10-31 Taiwan Semiconductor Manufacturing Co., Ltd Semiconductor device structure and manufacturing method
US20190198474A1 (en) 2017-04-27 2019-06-27 International Business Machines Corporation Multiple sized bump bonds
US11444048B2 (en) * 2017-10-05 2022-09-13 Texas Instruments Incorporated Shaped interconnect bumps in semiconductor devices
KR20220036598A (en) * 2020-09-16 2022-03-23 삼성전자주식회사 Semiconductor pacakge device
US11823887B2 (en) 2021-03-19 2023-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same

Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3871015A (en) * 1969-08-14 1975-03-11 Ibm Flip chip module with non-uniform connector joints
US4545610A (en) * 1983-11-25 1985-10-08 International Business Machines Corporation Method for forming elongated solder connections between a semiconductor device and a supporting substrate
US5569960A (en) * 1994-05-16 1996-10-29 Hitachi, Ltd. Electronic component, electronic component assembly and electronic component unit
US5989937A (en) * 1994-02-04 1999-11-23 Lsi Logic Corporation Method for compensating for bottom warpage of a BGA integrated circuit
US6053394A (en) * 1998-01-13 2000-04-25 International Business Machines Corporation Column grid array substrate attachment with heat sink stress relief
US6107685A (en) * 1998-09-25 2000-08-22 Sony Corporation Semiconductor part and fabrication method thereof, and structure and method for mounting semiconductor part
US6534875B1 (en) * 1998-09-25 2003-03-18 Sony Corporation Semiconductor part for component mounting, mounting structure and mounting method
US6541857B2 (en) * 1999-10-25 2003-04-01 International Business Machines Corporation Method of forming BGA interconnections having mixed solder profiles
US20030114024A1 (en) * 2001-12-18 2003-06-19 Kabushiki Kaisha Toshiba Printed wiring board having plurality of conductive patterns passing through adjacent pads, circuit component mounted on printed wiring board and circuit module containing wiring board with circuit component mounted thereon
US6624004B2 (en) * 2001-04-20 2003-09-23 Advanced Semiconductor Engineering, Inc. Flip chip interconnected structure and a fabrication method thereof
US6674162B2 (en) * 2000-03-30 2004-01-06 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof
US6734566B2 (en) * 2000-02-21 2004-05-11 Nec Electronics Corporation Recyclable flip-chip semiconductor device
US6750549B1 (en) * 2002-12-31 2004-06-15 Intel Corporation Variable pad diameter on the land side for improving the co-planarity of ball grid array packages
US6940176B2 (en) * 2002-05-21 2005-09-06 United Microelectronics Corp. Solder pads for improving reliability of a package
US20090057887A1 (en) * 2007-08-29 2009-03-05 Ati Technologies Ulc Wafer level packaging of semiconductor chips
US7541217B1 (en) * 2008-02-05 2009-06-02 Industrial Technology Research Institute Stacked chip structure and fabrication method thereof
US7902679B2 (en) * 2001-03-05 2011-03-08 Megica Corporation Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
US7906835B2 (en) * 2007-08-13 2011-03-15 Broadcom Corporation Oblong peripheral solder ball pads on a printed circuit board for mounting a ball grid array package
US8337735B2 (en) * 2008-04-29 2012-12-25 Ultratech, Inc. Solder mold plates used in packaging process and method of manufacturing solder mold plates

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4005472A (en) * 1975-05-19 1977-01-25 National Semiconductor Corporation Method for gold plating of metallic layers on semiconductive devices
US4188438A (en) * 1975-06-02 1980-02-12 National Semiconductor Corporation Antioxidant coating of copper parts for thermal compression gang bonding of semiconductive devices
JPS56150830A (en) * 1980-04-25 1981-11-21 Hitachi Ltd Semiconductor device
JP2593965B2 (en) * 1991-01-29 1997-03-26 三菱電機株式会社 Semiconductor device
JPH10209210A (en) * 1997-01-20 1998-08-07 Sharp Corp Semiconductor device, its manufacture, and its inspection method
US6642136B1 (en) * 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US6077726A (en) * 1998-07-30 2000-06-20 Motorola, Inc. Method and apparatus for stress relief in solder bump formation on a semiconductor device
JP3577419B2 (en) * 1998-12-17 2004-10-13 新光電気工業株式会社 Semiconductor device and manufacturing method thereof
US6451127B1 (en) * 1999-06-01 2002-09-17 Motorola, Inc. Conductive paste and semiconductor component having conductive bumps made from the conductive paste
JP3968554B2 (en) * 2000-05-01 2007-08-29 セイコーエプソン株式会社 Bump forming method and semiconductor device manufacturing method
WO2002062117A1 (en) * 2001-01-31 2002-08-08 The Furukawa Electric Co., Ltd. Method for jointing electronic parts
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US6740577B2 (en) * 2002-05-21 2004-05-25 St Assembly Test Services Pte Ltd Method of forming a small pitch torch bump for mounting high-performance flip-flop devices
DE60226732D1 (en) * 2002-09-30 2008-07-03 Umicore Ag & Co Kg Catalyst coated ionomer membrane with protective film and membrane electrode assembly made therefrom
US6888255B2 (en) * 2003-05-30 2005-05-03 Texas Instruments Incorporated Built-up bump pad structure and method for same
TWI233682B (en) 2003-08-22 2005-06-01 Advanced Semiconductor Eng Flip-chip package, semiconductor chip with bumps, and method for manufacturing semiconductor chip with bumps
US8026128B2 (en) * 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
JP4928945B2 (en) * 2003-11-10 2012-05-09 スタッツ・チップパック・インコーポレイテッド Bump-on-lead flip chip interconnect
US7098540B1 (en) * 2003-12-04 2006-08-29 National Semiconductor Corporation Electrical interconnect with minimal parasitic capacitance
US7394161B2 (en) * 2003-12-08 2008-07-01 Megica Corporation Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto
JP4451214B2 (en) 2004-05-21 2010-04-14 シャープ株式会社 Semiconductor device
JP4130668B2 (en) * 2004-08-05 2008-08-06 富士通株式会社 Substrate processing method
TWI259572B (en) 2004-09-07 2006-08-01 Siliconware Precision Industries Co Ltd Bump structure of semiconductor package and fabrication method thereof
KR20070107154A (en) * 2005-03-25 2007-11-06 스태츠 칩팩, 엘티디. Flip chip interconnection having narrow interconnection sites on the substrate
JP2006303452A (en) * 2005-03-25 2006-11-02 Sanyo Electric Co Ltd Semiconductor device and its manufacturing method
US20060255473A1 (en) * 2005-05-16 2006-11-16 Stats Chippac Ltd. Flip chip interconnect solder mask
US7622309B2 (en) * 2005-06-28 2009-11-24 Freescale Semiconductor, Inc. Mechanical integrity evaluation of low-k devices with bump shear
US20070102815A1 (en) * 2005-11-08 2007-05-10 Kaufmann Matthew V Bumping process with self-aligned A1-cap and the elimination of 2nd passivation layer
US20080048321A1 (en) * 2006-08-24 2008-02-28 Ati Technologies Inc. Flip chip semiconductor assembly with variable volume solder bumps
US7713782B2 (en) * 2006-09-22 2010-05-11 Stats Chippac, Inc. Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud-bumps
US8349721B2 (en) * 2008-03-19 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding
US8736050B2 (en) * 2009-09-03 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Front side copper post joint structure for temporary bond in TSV application
US8659172B2 (en) * 2008-12-31 2014-02-25 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material with solder mask patch
US8354750B2 (en) * 2010-02-01 2013-01-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stress buffer structures in a mounting structure of a semiconductor device
US20120267779A1 (en) 2011-04-25 2012-10-25 Mediatek Inc. Semiconductor package
US9646923B2 (en) * 2012-04-17 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices

Patent Citations (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3871015A (en) * 1969-08-14 1975-03-11 Ibm Flip chip module with non-uniform connector joints
US4545610A (en) * 1983-11-25 1985-10-08 International Business Machines Corporation Method for forming elongated solder connections between a semiconductor device and a supporting substrate
US5989937A (en) * 1994-02-04 1999-11-23 Lsi Logic Corporation Method for compensating for bottom warpage of a BGA integrated circuit
US5569960A (en) * 1994-05-16 1996-10-29 Hitachi, Ltd. Electronic component, electronic component assembly and electronic component unit
US6053394A (en) * 1998-01-13 2000-04-25 International Business Machines Corporation Column grid array substrate attachment with heat sink stress relief
US6107685A (en) * 1998-09-25 2000-08-22 Sony Corporation Semiconductor part and fabrication method thereof, and structure and method for mounting semiconductor part
US6534875B1 (en) * 1998-09-25 2003-03-18 Sony Corporation Semiconductor part for component mounting, mounting structure and mounting method
US6541857B2 (en) * 1999-10-25 2003-04-01 International Business Machines Corporation Method of forming BGA interconnections having mixed solder profiles
US6734566B2 (en) * 2000-02-21 2004-05-11 Nec Electronics Corporation Recyclable flip-chip semiconductor device
US6674162B2 (en) * 2000-03-30 2004-01-06 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof
US7902679B2 (en) * 2001-03-05 2011-03-08 Megica Corporation Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
US6624004B2 (en) * 2001-04-20 2003-09-23 Advanced Semiconductor Engineering, Inc. Flip chip interconnected structure and a fabrication method thereof
US20030114024A1 (en) * 2001-12-18 2003-06-19 Kabushiki Kaisha Toshiba Printed wiring board having plurality of conductive patterns passing through adjacent pads, circuit component mounted on printed wiring board and circuit module containing wiring board with circuit component mounted thereon
US6940176B2 (en) * 2002-05-21 2005-09-06 United Microelectronics Corp. Solder pads for improving reliability of a package
US6750549B1 (en) * 2002-12-31 2004-06-15 Intel Corporation Variable pad diameter on the land side for improving the co-planarity of ball grid array packages
US7906835B2 (en) * 2007-08-13 2011-03-15 Broadcom Corporation Oblong peripheral solder ball pads on a printed circuit board for mounting a ball grid array package
US20090057887A1 (en) * 2007-08-29 2009-03-05 Ati Technologies Ulc Wafer level packaging of semiconductor chips
US8344505B2 (en) * 2007-08-29 2013-01-01 Ati Technologies Ulc Wafer level packaging of semiconductor chips
US7541217B1 (en) * 2008-02-05 2009-06-02 Industrial Technology Research Institute Stacked chip structure and fabrication method thereof
US8337735B2 (en) * 2008-04-29 2012-12-25 Ultratech, Inc. Solder mold plates used in packaging process and method of manufacturing solder mold plates

Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10109608B2 (en) 2011-04-25 2018-10-23 Mediatek Inc. Semiconductor package
US10573615B2 (en) 2012-07-31 2020-02-25 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
US9177899B2 (en) 2012-07-31 2015-11-03 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
US10580747B2 (en) 2012-07-31 2020-03-03 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
US20160358877A1 (en) * 2012-07-31 2016-12-08 Mediatek Inc. Semiconductor package using flip-chip technology
US10573616B2 (en) 2012-07-31 2020-02-25 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
US11469201B2 (en) 2012-07-31 2022-10-11 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
US10991669B2 (en) * 2012-07-31 2021-04-27 Mediatek Inc. Semiconductor package using flip-chip technology
US9460646B2 (en) * 2012-11-01 2016-10-04 Samsung Display Co., Ltd. Display device and bonding test system
US20140117998A1 (en) * 2012-11-01 2014-05-01 Samsung Display Co., Ltd. Display device and bonding test system
US20140374900A1 (en) * 2013-06-21 2014-12-25 Heungkyu Kwon Semiconductor package and method of fabricating the same
US20150262950A1 (en) * 2014-03-14 2015-09-17 Lsi Corporation Method for Fabricating Equal Height Metal Pillars of Different Diameters
US9324557B2 (en) * 2014-03-14 2016-04-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Method for fabricating equal height metal pillars of different diameters
US20180211743A1 (en) * 2014-04-18 2018-07-26 Canon Kabushiki Kaisha Printed circuit board
US10679766B2 (en) * 2014-04-18 2020-06-09 Canon Kabushiki Kaisha Printed circuit board
US10109566B2 (en) 2014-10-31 2018-10-23 Mediatek Inc. Semiconductor package
US9679830B2 (en) * 2014-10-31 2017-06-13 Mediatek Inc. Semiconductor package
US20160126161A1 (en) * 2014-10-31 2016-05-05 Mediatek Inc. Semiconductor package
US20200198962A1 (en) * 2015-09-29 2020-06-25 Tronic's Microsystems Device for Attaching Two Elements Such as a Chip, an Interposer and a Support
US20170162545A1 (en) * 2015-12-07 2017-06-08 Samsung Electronics Co., Ltd. Stacked semiconductor device and a method of manufacturing the same
US10366968B2 (en) * 2016-09-30 2019-07-30 Intel IP Corporation Interconnect structure for a microelectronic device
US20190333886A1 (en) * 2016-09-30 2019-10-31 Intel IP Corporation Interconnect structure for a microelectronic device
US20180342475A1 (en) * 2017-05-23 2018-11-29 Micron Technology, Inc. Semiconductor device assembly with die support structures
US10923447B2 (en) * 2017-05-23 2021-02-16 Micron Technology, Inc. Semiconductor device assembly with die support structures
US10950568B2 (en) * 2017-05-23 2021-03-16 Micron Technology, Inc. Semiconductor device assembly with surface-mount die support structures
US20180342476A1 (en) * 2017-05-23 2018-11-29 Micron Technology, Inc. Semiconductor device assembly with surface-mount die support structures
WO2019066902A1 (en) * 2017-09-29 2019-04-04 Intel Corporation Pillar array plate
US10658282B2 (en) * 2018-08-03 2020-05-19 Unimicron Technology Corp. Package substrate structure and bonding method thereof
US20210408354A1 (en) * 2020-06-29 2021-12-30 Nec Corporation Quantum device

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CN102760712A (en) 2012-10-31

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