US20120193788A1 - Stacked semiconductor chips packaging - Google Patents
Stacked semiconductor chips packaging Download PDFInfo
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- US20120193788A1 US20120193788A1 US13/017,946 US201113017946A US2012193788A1 US 20120193788 A1 US20120193788 A1 US 20120193788A1 US 201113017946 A US201113017946 A US 201113017946A US 2012193788 A1 US2012193788 A1 US 2012193788A1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Various methods and apparatus for joining stacked substrates to a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes coupling plural substrates to form a stack. At least one of the plural substrates is a semiconductor chip. Plural conductive vias are formed in a first of the plural substrates. Each of the plural conductive vias includes a first end positioned in the first substrate and a second end projecting out of the first substrate.
Description
- 1. Field of the Invention
- This invention relates generally to semiconductor processing, and more particularly to methods and apparatus for stacking multiple semiconductor devices and packaging the same.
- 2. Description of the Related Art
- Some time ago semiconductor chip designers began stacking multiple semiconductor dice (aka “dies”) vertically in order to obtain more functionality without an attendant increase in required package substrate or circuit board area. A variety of techniques have been used to electrically connect adjacent dice in such stacked arrangements. One technique has involved the use of wire bonds leading from contact pads on one die to corresponding contact pads on an adjacent die. Another technique that has been introduced more recently involves the use of so-called thru-silicon-vias (TSV). A typical TSV is a conductive via that extends nearly or perhaps entirely through a semiconductor chip, depending on the presence or absence of any intervening conductor pads at one or the other of the principal surfaces of the chip.
- Most semiconductor chips are eventually mounted to some form of circuit board or enclosure. Typical examples include semiconductor chip package substrates, circuit cards, motherboards and other types of packaging closures. A technical challenge associated with most mounting schemes is the establishment of electrical interfaces between the semiconductor die or dice and the receiving circuit board. The fabrication of these electoral interfaces may be particularly challenging in a stacked dice arrangement. This follows from the fact that the multiple semiconductor chips may, by definition, include a significantly higher number of input outputs than a single semiconductor device.
- One conventional technique for establishing electrical interconnects between a stacked dice arrangement and a circuit board involves the use of wire bond interconnects. Plural wire bonds are connected to conductor pads on one or more of the dice in the stacked dice arrangement and also to corresponding conductor pads on the circuit board or some other device on the circuit board. Another conventional arrangement for connecting a stacked dice arrangement to a circuit board involves the use of some form of control collapse bump arrangement wherein the plural solder joints are established between a lowermost of the stacked dice and the circuit board. This typically entails the formation of a solder bump on the lowermost die and a corresponding solder bump on the circuit board followed by a solder reflow process.
- A more recent innovation involves the use of copper pillars that project outwardly from the lowermost die of a stacked dice arrangement and interconnect electrically with a circuit board. This conventional arrangement utilizes a low profile solder paste placed in plural low-profile openings in a solder mask on the circuit board. The lower ends of each of the copper pillars is fitted with a small solder cap. To establish the requisite connections, the die is positioned so that the solder caps of the copper pillars are in proximity or in contact with the low profile solder paste portions and a reflow process is performed. Expenses in the form of material and labor costs are associated with the conventional copper pillar process.
- The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
- In accordance with one aspect of the present invention, a method of manufacturing is provided that includes coupling plural substrates to form a stack. At least one of the plural substrates is a semiconductor chip. Plural conductive vias are formed in a first of the plural substrates. Each of the plural conductive vias includes a first end positioned in the first substrate and a second end projecting out of the first substrate.
- In accordance with another aspect of the present invention, a method of manufacturing is provided that includes providing a circuit board that includes an outermost surface and plural conductor pads. A solder structure is formed on each of the plural conductor pads. Each of the solder structures includes a portion projecting beyond the outermost surface. The solder structures are coupled to corresponding conductive vias of a stack of substrates. At least one of the substrates is a semiconductor chip.
- In accordance with another aspect of the present invention, an apparatus is provided that has a stack including plural substrates. At least one of the plural substrates is a semiconductor chip. Plural conductive vias are coupled to a principal surface of a first of the plural substrates. Each of the plural conductive vias includes a first end positioned in the first substrate and a second end projecting away from the principal surface of the first substrate.
- The foregoing and other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:
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FIG. 1 is a pictorial view of an exemplary embodiment of a semiconductor chip device that includes a stack of four substrates mounted on a circuit board; -
FIG. 2 is a sectional view ofFIG. 1 taken at section 2-2; -
FIG. 3 is a sectional view of the exemplary stack of substrates prior to mounting to an exemplary circuit board; -
FIG. 4 is a sectional view likeFIG. 3 but of an alternate exemplary circuit board; -
FIG. 5 is a sectional view of one of the substrates undergoing masking; -
FIG. 6 is a sectional view of the substrate undergoing via hole formation; -
FIG. 7 is a sectional view of the substrate undergoing via formation; -
FIG. 8 is a sectional view of the substrate after mask removal; -
FIG. 9 is a sectional view likeFIG. 7 but depicting an alternate exemplary via formation in the substrate; -
FIG. 10 is a sectional view likeFIG. 9 but depicting the vias after mask removal; -
FIG. 11 is a sectional of an exemplary circuit board undergoing solder structure placement; -
FIG. 12 is a sectional view of an exemplary circuit undergoing an alternate exemplary solder structure formation masking; -
FIG. 13 is a sectional view likeFIG. 12 depicting solder plating; -
FIG. 14 is a sectional view likeFIG. 13 depicting the solder structures following mask removal; and -
FIG. 15 is a sectional view of a conventional semiconductor chip-to-package substrate mounting utilizing copper pillars. - Various embodiments of a semiconductor chip device that includes two or more stacked substrates are described herein. One example includes multiple substrates that may be semiconductor chips stacked and mounted on a circuit board. The lowermost of the substrates includes conductive vias that project beyond the chip and metallurgically bond with vertically projecting solder structures, such as solder pillars. The combination of the projecting vias and projecting solder structures provides sufficient solder volume to wet during reflow without the requirement to separately plate the vias with solder. Additional details will now be described.
- In the drawings described below, reference numerals are generally repeated where identical elements appear in more than one figure. Turning now to the drawings, and in particular to
FIG. 1 , therein is shown a pictorial view of an exemplary embodiment of asemiconductor chip device 10 that includes astack 13 of foursubstrates circuit board 35. Theexemplary stack 13 is depicted with foursubstrates stack 13 may consist of two or more semiconductor substrates. Thesubstrates substrates substrates substrates - The
circuit board 35 may be a semiconductor chip package substrate, a circuit card, or virtually any other type of printed circuit board. A monolithic structure could be used for thecircuit board 35, although a more typical configuration will utilize a build-up design. In this regard, thecircuit board 35 may consist of a central core upon which one or more build-up layers are formed and below which an additional one or more build-up layers are formed. The core itself may consist of a stack of one or more layers. If implemented as a semiconductor chip package substrate, the number of layers in thecircuit board 35 can vary from four to sixteen or more, although less than four may be used. So-called “coreless” designs may be used as well. The layers of thecircuit board 35 may consist of an insulating material, such as various well-known epoxies, interspersed with metal interconnects. A multi-layer configuration other than buildup could be used. Optionally, thecircuit board 35 may be composed of well-known ceramics or other materials suitable for package substrates or other printed circuit boards. Thecircuit board 35 is provided with a number of conductor traces and vias and other structures (not visible) in order to provide power, ground and signals transfers between thesemiconductor chip 110 and another device, such as another circuit board for example. Thecircuit board 35 may be electrically connected to another device (not shown) by way of an input/output array such as theball grid array 50 provided on theunder surface 55 of thecircuit board 35. - Electrical pathways between the
substrates circuit board 35 as well as between any of thesubstrates FIG. 1 but will be depicted in subsequent figures and described accordingly. These interconnect structures may be fabricated inside thesubstrates - An
underfill material layer 45 is dispensed between thesubstrate 15 and thecircuit board 35 to alleviate issues of differential coefficient of thermal expansion. Theunderfill 45 may be formed from well-known polymeric materials, such as epoxies or others, with or without some form of filler, such as fiberglass or others. Only a portion of theunderfill 45 is visible around the periphery of thesubstrate 15. - Attention is now turned to
FIG. 2 , which is a sectional view ofFIG. 1 taken at section 2-2. As noted above, thestack 13 ofsubstrates substrate 30 may be provided with plural conducting structures orvias 60 that may interface withcorresponding conductor pads 65 of thesubstrate 25. Thesubstrate 25 includes, in turn,plural vias 70 connected to some or all of theconductor pads 65. Thesubstrate 20 may include similarlyplural conductor pads 75 tied to some or all of thevias 70 of thechip 25 as well asvias 80 connected toconductor pads 85. To interface thestack 13 electrically with thecircuit board 35, thelowermost substrate 15 may be provided with pluralconductive vias 90 that project beyond aprincipal surface 95 thereof and interface withcorresponding solder structures 100 of thecircuit board 35. For simplicity of illustration, only fourvias 90 andsolder structures 100 are depicted. However, the skilled artisan will appreciate that the populations of such structures may number in the hundreds of thousands depending upon the complexity of thestack 13 and thecircuit board 35. Theprincipal surface 95 of thesubstrate 15 may actually be the facing surface of apolymeric layer 105 composed of materials such as polyimide or other polymeric materials that are suitable to provide compliant protection for any delicate circuit structures in the vicinity of thepolymeric layer 105. Thelayer 105 could also be a redistribution layer, in which a polymer or oxide material is used as insulating material. - The conductor structures in the
various substrates vias 60, may be formed by fabricating plural holes or trenches in thesubstrate 30 and thereafter depositing or by plating, chemical vapor deposition, physical deposition, e-beam deposition or other techniques. A variety of conductor materials may be used, such as copper, gold, platinum, palladium, aluminum, titanium, refractory metals, refractory metal compounds, alloys of these or the like. Hole or trench formation may be by chemical etching, laser drilling or other material removal techniques. Higher aspect ratio openings will generally require more anisotropic techniques, such as laser drilling or plasma etching. The various pads, such as thepad pads - The
substrates stack 13 in a variety of ways. Exemplary techniques include copper-to-copper direct bonding, silicon dioxide-to-silicon diffusion bonding, the application of an adhesive or other techniques. The copper-to-copper and silicon dioxide-to-silicon diffusion bonding involve pressing two substrates together so that corresponding conductor structures are touching or nearly, such as thevias 90 and thepads 85, and heating the combination to initiate the bonding. If an adhesive is contemplated, materials such as benzocyclobutene or the like may be applied to one or both of the facing substrates and a thermal cure performed. The stacking may be performed on so-called die-to-die, die-to-wafer or even wafer-to-wafer bases. If die-to-wafer or wafer-to-wafer is used, singulation will follow the joining operation. Wafer-to-wafer joining may be more attractive where the dice to be joined are roughly the same size. Ohmic contact between the conductor structures of a given substrate, such as thesubstrate 20 and the next adjoiningsubstrate chip 15, could also be established with solder. - Still referring to
FIG. 2 , thesolder structures 100 of thecircuit board 35 are positioned inrespective openings 110 in asolder mask 115. Thesolder structures 100 are formed in ohmic contact withcorresponding conductor pads 120 that may, in turn, be connected to plural traces or other interconnect structures in thecircuit board 35 that are not visible. If thecircuit board 35 is fabricated as a device that will be mounted to another circuit board or other device, then, as noted above, theplural solder balls 50 may be positioned inrespective openings 125 in anothersolder mask 130 formed on thelower surface 135 of thecircuit board 35. Thesolder balls 50 are formed in ohmic contact withcorresponding conductor pads 140 that may electrically interface with variousother conductor pads 120 by way of the aforementioned, but not visible interconnect structures. Thesolder structures 100 andballs 50 may be composed of various solders, such as lead-based or lead-free solders. An exemplary lead-based solder may have a composition at or near eutectic proportions, such as about 63% Sn and 37% Pb. Lead-free examples include tin-silver (about 97.3% Sn 2.7% Ag), tin-copper (about 99% Sn 1% Cu), tin-silver-copper (about 96.5% Sn 3% Ag 0.5% Cu) or the like. The solder masks 115 and 130 may be composed of a variety of materials suitable for solder mask fabrication, such as, for example, PSR-4000 AUS703 manufactured by Taiyo Ink Mfg. Co., Ltd. or SR7000 manufactured by Hitachi Chemical Co., Ltd. Theunderfill 45 may be positioned in agap 145 between thesubstrate 15 and thecircuit board 35 following the connection of the vias 90 to thesolder structures 100. - To establish metallurgical bonds between the vias 90 and the
solder structures 100, thestack 13 is put into the orientation depicted inFIG. 2 and positioned so that thevias 90 and thesolder structures 100 are either in physical contact or in very close proximity. Thereafter, a reflow process is performed to liquefy at least the upper portions ofsolder structures 100 so that wetting between solder and the metal of thevias 90 occurs. The parameters for a suitable reflow process will depend on the compositions of thevias 90 and thesolder structures 100. In an exemplary embodiment utilizingcopper vias 90 and tin-silver solder structures 100, heating to about 220 to 240 C for about 10 to 60 seconds may be suitable. It should be understood thatFIG. 2 depicts thesolder structures 100 following reflow. - The
solder structures 100 are advantageously fabricated to project beyond a principal or outermost surface of thecircuit board 35, which in this case is anoutermost surface 147 of thesolder mask 115. This arrangement gives the solder structures sufficient volume to readily wet to thevias 90 without the necessity of fitting the vias 90 with solder caps. A variety of techniques may be used to form thesolder structures 100 with the desired height projection. In this regard, attention is now turned toFIG. 3 , which is a sectional view likeFIG. 2 , but which illustrates thecircuit board 35 and thestack 13 prior to the metallurgical bonding of the vias 90 to thesolder structures 100. For simplicity of illustration, only a few of the elements labeled and discussed inFIG. 2 are labeled separately inFIG. 3 . Here, thesolder structures 100 are fabricated as solder pillars that project above thesolder mask 115. Thesolder structures 100, shaped in this illustration as pillars, may be round, oval or rectangular or some other shape when viewed from above and may be fabricated using techniques to be described in more detail below. Again, to establish the requisite metallurgical bonds, thestack 13 is positioned so thatvias 90 are in contact or in close proximity with thesolder structures 100 and the aforementioned reflow processes performed. - Optionally, and as depicted in
FIG. 4 , the solder structures, now numbered 100′, may be initially fabricated as solder bumps or balls and thestack 13 positioned proximate thecircuit board 35 so that thevias 90 may wet to thesolder structures 100′ in a reflow process. Again, thesolder structures 100′ project beyond the principal or outermost surface of thecircuit board 35, which in this case is theoutermost surface 147 of thesolder mask 115. Techniques to fabricate thesolder structures 100′ as bumps or balls will be described in more detail below. - An exemplary process flow for fabricating the
vias 90 depicted inFIGS. 2 , 3 and 4 may be understood by referring now toFIGS. 5 , 6, 7 and 8 and initially toFIG. 5 , which is a sectional view of thesubstrate 15 after application of thepolymeric layer 105 but prior to the fabrication of the aforementioned vias. At this stage, thesubstrate 15 could be singulated or part of a wafer. Thesubstrate 15 could also be bonded to another die, substrate or wafer if desired. Amask 150 may be applied to thepolymer layer 105 and patterned using well-known lithographic techniques to establish a series ofopenings 155. Theopenings 155 represent locations where a subsequent material removal process will establish bores, trenches or other openings in thesubstrate 15 where the vias will be formed. Next and as shown inFIG. 6 , a material removal process may be performed to establishplural openings 160 that extend through thesubstrate 15. The material removal to establish theopening 160 may be performed by chemical etch with or without plasma enhancement, laser drilling or other material removal techniques. The material removal process first penetrates thepolymer layer 105 and then thesubstrate 15. Themask 150 is left in place following the material removal process to establish theopening 160. - Next and as depicted in
FIG. 7 , thevias 90 may be formed in theopenings 160 of thesubstrate 15. Because an ultimate goal is to establish the vias 90 with ends that project beyond thepolymer layer 105, themask 150 is left in place during the via formation. A variety of processes may be used to establish thevias 90. In an exemplary embodiment, a plating process is used to deposit copper or an alloy thereof into theopenings 155 in themask 150 and ultimately theopenings 160 of thesemiconductor chip 15. If desired, the plating process may be performed in multiple steps with a first step used to establish a thin seed layer and a subsequent bulk plating process. With thevias 90 formed, themask 150 may be removed as shown inFIG. 8 . The mask removal may be by way of ashing, solvent stripping, combinations of the two or other mask removal techniques. At this stage, thevias 90 include ends 165 positioned in thesubstrate 15 and opposite ends 167 that project out of thesubstrate 15 and in this case beyond thepolymer layer 105. Thesubstrate 15 is ready to be joined to theother substrates stack 13, and thestack 13 to thecircuit board 35 depicted inFIG. 2 . - An alternate exemplary process for fabricating the vias now numbered 90′, may be understood by referring now to
FIGS. 9 and 10 . Unlike the previous exemplary process for forming the vias 90 depicted inFIGS. 5 , 6, 7 and 8, where a single material deposition process is utilized to establish the vias, this alternative illustrative process may use a multi-step material deposition process. As shown inFIG. 9 , which is a sectional view likeFIG. 7 , vias 90′ may be established in thesubstrate 15 using the techniques described above in conjunction withFIGS. 5 , 6, 7 and 8 generally with a few exceptions. In this regard, themask 150 depicted inFIGS. 5 , 6 and 7 may be removed following the formation ofopenings 160 in thesubstrate 15. With the mask removed, thevias 90′ may be formed by the aforementioned material deposition techniques such as plating or otherwise but without the mask present so that extensions that project beyond thepolymer layer 105 are not established. However, at this stage a mask 170 may be formed on thepolymer layer 105 and suitably patterned lithographically withopenings 175 that are positioned at the vias 90′ and a subsequent material deposition process may be used to establish viaextensions 180 that are in ohmic contact with the vias 90′. Thereafter, and as depicted inFIG. 10 , the mask 170 may be removed using the aforementioned mask removal techniques to leave theprojections 180 of the vias 90′ extending beyond thepolymer layer 100. At this stage, thesubstrate 15 may be joined to theother substrates stack 13, and thestack 13 to thecircuit board 35 depicted inFIG. 2 . - An exemplary process for fabricating the solder structures as solder bumps such as those depicted in
FIG. 4 may be understood by referring now toFIG. 11 , which is a sectional view of the circuit board following the application and patterning of thesolder mask 115 with therespective openings 110. Theopenings 110 may be fabricated using lithographic patterning techniques suitable for solder masks. In this regard, if thesolder mask 115 is composed of photosensitive materials then well-known lithographic exposure and developing techniques may be used to establish theopenings 110. Optionally, if thesolder mask 115 is composed of some sort of hard mask material then appropriate lithographic and material removal techniques may be applied. Following the formation of theopenings 110, plural solder balls or bumps 100′ may be placed in theopenings 110 and in ohmic contact with theunderlying pads 120. Thebumps 100′ could be positioned by way of pick and place, jet nozzle disposal or even a printing process in which thesolder mask 115 would be purely optional. - An alternate exemplary process flow for establishing the solder structures as pillars, like the
pillars 100 depicted inFIG. 3 , may be understood by referring now toFIGS. 12 , 13 and 14 and initially toFIG. 12 , which is a sectional view of thecircuit board 35 following the fabrication of theconductor pads 120. Here, amask 185 composed of photoresist or other suitable mask materials may be formed on asurface 190 of thecircuit board 35 and patterned withplural openings 195 that are positioned over the correspondingconductor pads 120. Next and as depicted inFIG. 13 , with themask 185 in place, a plating process may be used to establish thesolder pillars 100 in therespective openings 195. Again, a technical goal is to fabricate themask 185 with a sufficient height so that the subsequently formedsolder pillars 100 project significantly beyond theupper surface 190 of thecircuit board 35. Other deposition techniques could be used, such as sputtering, e-beam deposition or others. Themask 185 could be composed of well-known solder mask materials that are photo sensitive and patternable using well known lithography techniques. Next and as shown inFIG. 14 , themask 185 may be removed to leave thesolder pillars 100 projecting above thecircuit board 35. Of course it may be desirable to provide some sort of insulating layer on thesurface 190 of thecircuit board 35 such as the soldermask material layer 115 depicted inFIG. 2 subsequent to the formation of thepillars 100. In this regard, thesolder mask 115 could be applied and lithographically patterned to expose thepillars 100. - It may be useful at this point to contrast an exemplary conventional multiple chip stack-to-circuit board joining process and structure. Attention is now turned to
FIG. 15 , which is a sectional view depicting a conventionalsingle semiconductor chip 205 positioned above acircuit board 210. Thesemiconductor chip 205 is provided withplural vias 220 that project beyond apolymer layer 225. Thevias 220, however, are provided with corresponding solder caps 230 that are designed to metallurgically bond with corresponding solder pacedstructures 235 positioned inopenings 240 in asolder mask 245 of thecircuit board 210. The solder caps 230 are also necessary to provide enough solder volume to effectively establish metallurgical bonds with the low profilesolder pace structures 235 of thecircuit board 210 which are of course unlike the vertically projectingsolder pillars 100 orbumps 100′ described in the illustrative embodiments herein. The fabrication processes required to place the solder caps 230 on therespective vias 220 represents a cost center both in terms of materials and processing time. - While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.
Claims (18)
1. A method of manufacturing, comprising:
coupling plural substrates to form a stack, wherein at least one of the plural substrates is a semiconductor chip; and
forming plural conductive vias in a first of the plural substrates, each of the plural conductive vias including a first end positioned in the first substrate and a second end projecting out of the first substrate.
2. The method of claim 1 , wherein a second of the plural substrates comprises a semiconductor chip.
3. The method of claim 1 , wherein a second of the plural substrates comprises an interposer.
4. The method of claim 1 , wherein the forming of the plural conductive vias comprises forming plural openings in the first substrate and forming at least the first ends of the plural conductors in the openings by plating.
5. The method of claim 1 , comprising positioning the second ends of the plural conductive vias proximate solder structures of a circuit board and reflowing the solder structures to wet the second ends.
6. The method of claim 5 , wherein the circuit board comprises a principal surface and the solder structures project beyond the principal surface.
7. A method of manufacturing, comprising:
providing a circuit board that includes an outermost surface and plural conductor pads;
forming a solder structure on each of the plural conductor pads, each of the solder structures including a portion projecting beyond the outermost surface; and
coupling the solder structures to corresponding conductive vias of a stack of substrates, wherein at least one of the substrates is a semiconductor chip.
8. The method of claim 7 , wherein the forming the solder structures comprises applying a mask to the circuit board, forming plural openings in the mask leading to the plural conductor pads, and forming the solder structures in the plural openings that project beyond an outermost surface of the mask.
9. The method of claim 7 , wherein the solder structures comprises pillars.
10. The method of claim 7 , wherein the solder structures comprises balls.
11. An apparatus, comprising:
a stack including plural substrates, wherein at least one of the plural substrates is a semiconductor chip; and
plural conductive vias coupled to a principal surface of a first of the plural substrates, each of the plural conductive vias including a first end positioned in the first substrate and a second end projecting away from the principal surface of the first substrate.
12. The apparatus of claim 11 , wherein a second of the plural substrates comprises an interposer.
13. The apparatus of claim 11 , comprising a circuit board including plural solder structures coupled to the second ends of the plural conductive vias.
14. The apparatus of claim 13 , wherein the circuit board comprises a principal surface and the solder structures project beyond the principal surface.
15. The apparatus of claim 14 , wherein the solder structures comprise solder pillars.
16. The apparatus of claim 14 , wherein the solder structures comprise solder balls.
17. A semiconductor device comprising:
a semiconductor chip comprising plural conductive vias coupled to a surface of the semiconductor chip, each of the plural conductive vias including a first end positioned in the semiconductor chip and a second end projecting away from the surface of the semiconductor chip, the plural conductive vias arranged to align in a stack configuration with a substrate.
18. The semiconductor device of claim 17 wherein the substrate comprises an interposer comprised of plural conductive vias aligned to stack with corresponding plural conductive vias in the semiconductor chip when in a stacked configuration.
Priority Applications (4)
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US13/017,946 US20120193788A1 (en) | 2011-01-31 | 2011-01-31 | Stacked semiconductor chips packaging |
TW101101890A TW201240064A (en) | 2011-01-31 | 2012-01-18 | Stacked semiconductor chips packaging |
PCT/US2012/023243 WO2012106292A1 (en) | 2011-01-31 | 2012-01-31 | Stacked semiconductor chips packaging |
US14/737,716 US9449907B2 (en) | 2011-01-31 | 2015-06-12 | Stacked semiconductor chips packaging |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US13/017,946 US20120193788A1 (en) | 2011-01-31 | 2011-01-31 | Stacked semiconductor chips packaging |
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US14/737,716 Continuation US9449907B2 (en) | 2011-01-31 | 2015-06-12 | Stacked semiconductor chips packaging |
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Also Published As
Publication number | Publication date |
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US20150279773A1 (en) | 2015-10-01 |
US9449907B2 (en) | 2016-09-20 |
WO2012106292A1 (en) | 2012-08-09 |
TW201240064A (en) | 2012-10-01 |
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