US20110315946A1 - Nonvolatile memory device - Google Patents
Nonvolatile memory device Download PDFInfo
- Publication number
- US20110315946A1 US20110315946A1 US13/224,940 US201113224940A US2011315946A1 US 20110315946 A1 US20110315946 A1 US 20110315946A1 US 201113224940 A US201113224940 A US 201113224940A US 2011315946 A1 US2011315946 A1 US 2011315946A1
- Authority
- US
- United States
- Prior art keywords
- metal
- pattern
- phase change
- layer
- upper electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
- H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
- H10N70/8413—Electrodes adapted for resistive heating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8825—Selenides, e.g. GeSe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/50—Resistive cell structure aspects
- G11C2213/51—Structure including a barrier layer preventing or limiting migration, diffusion of ions or charges or formation of electrolytes near an electrode
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/72—Array wherein the access device being a diode
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/79—Array wherein the access device being a transistor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Semiconductor Memories (AREA)
Abstract
A nonvolatile memory device, including a lower electrode on a semiconductor substrate, a phase change material pattern on the lower electrode, an adhesion pattern on the phase change material pattern and an upper electrode on the adhesion pattern, wherein the adhesion pattern includes a conductor including nitrogen.
Description
- This is a divisional application based on pending application Ser. No. 12/379,277, filed Feb. 18, 2009, the entire contents of which is hereby incorporated by reference.
- 1. Technical Field
- Embodiments relate to a nonvolatile memory device and a method of manufacturing the same.
- 2. Description of the Related Art
- Nonvolatile memory devices include semiconductor memory devices that maintain stored data even when the power supply is interrupted. Phase-change random access memory (PRAM) can store data according to a resistance state of a phase-change material pattern. A memory cell storing binary data of a PRAM may include a switching device, a lower electrode, a phase change material pattern, and an upper electrode. The switching device may be formed on a semiconductor substrate and the lower electrode, the phase change material pattern, and the upper electrode may be formed on the switching device. Chalcogenide of GeSeTe (GST) system may be used as the phase change material pattern. The lower electrode may heat the phase change material pattern. A portion of the phase change material pattern, or all of the phase change material pattern, may be converted from a crystalline state to an amorphous state, or from an amorphous state to a crystalline state. This conversion depends on the degree of heating of the phase change material pattern by the lower electrode, and a resistive value of the phase change material pattern.
- Specifically, a PRAM may apply a set pulse and a reset pulse to store binary data. The set pulse is needed to convert the phase change material pattern to a crystalline state. The set pulse applies a temperature higher than a temperature required to change the phase change material pattern to a crystalline state to the phase change material pattern for several nanoseconds through the lower electrode.
- The reset pulse is needed to convert the phase change material pattern to an amorphous state. The reset pulse applies a temperature higher than a temperature required to change the phase change material pattern to the amorphous state to the phase change material pattern for several tens of nanoseconds through the lower electrode.
- Conventionally, a temperature of the phase change material pattern affected by the reset pulse is higher than a temperature of the phase change material pattern affected by the set pulse. Since temperature rise is effected by Joule heating caused by an electrical current, the current flowing through the phase change material pattern when the set pulse is applied is smaller (for a corresponding lower temperature) than a current flowing through the phase change material pattern when the reset pulse is applied (when the temperature should be higher).
- Binary data may be stored and read depending on a resistance state of the phase change material pattern. The amorphous state material may have a resistivity higher than that of the crystalline state material, and thus the phase change material pattern may have a higher resistance for a given pattern size and shape when the material is in the amorphous state. The crystalline state is referred to as a set state and the amorphous state is referred to as a reset state.
- When reading data, the reading operation can maintain a high speed when a resistance (hereinafter, referred to as a set resistance) of the phase change material pattern in the crystalline state (i.e., the set state) is small. When storing data, the storing operation can maintain a high speed when a reset current for changing the phase change material pattern to an amorphous state (i.e., the reset state) is small. Thus, in a PRAM, a reset current should be reduced for a fast memory operation and a set resistance should be reduced for a fast writing operation.
- A phase change material pattern used in a PRAM is mainly material of GST system. When a voltage is applied to the phase change layer, the phase change layer shows a negative resistance characteristics and a resistance of the phase change material pattern is abruptly reduced. A PRAM is a memory device for storing binary data. A PRAM easily discriminates binary data because a ratio of a resistance according to a state of a binary data. A PRAM may not require a high voltage.
- Embodiments are therefore directed to a nonvolatile memory device and a method of manufacturing the same, which substantially overcome one or more of the problems due to the limitations and disadvantages of the prior art.
- It is therefore a feature of an embodiment to provide a nonvolatile memory device including an adhesion pattern material that prevents lifting.
- It is therefore another feature of an embodiment to provide a nonvolatile memory device having a lower reset current for a fast memory operation.
- It is therefore another feature of an embodiment to provide a nonvolatile memory device having a lower set resistance for a fast reading operation.
- At least one of the above and other features and advantages may be realized by providing a nonvolatile memory device, including a lower electrode on a semiconductor substrate, a phase change material pattern on the lower electrode, an adhesion pattern on the phase change material pattern, and an upper electrode on the adhesion pattern, wherein the adhesion pattern includes a conductor including nitrogen.
- The adhesion pattern and the upper electrode may each independently include a metal nitride layer or a metal oxynitride layer, and a ratio of metal to nitrogen in the metal nitride or oxynitride layer in the adhesion pattern may be different from a ratio of metal to nitrogen in the metal nitride or oxynitride layer in the upper electrode.
- The adhesion pattern may include a metal nitride layer, and a ratio of metal to nitrogen in the metal nitride layer may be about 1:0.95 to about 1:1.03.
- The metal of the metal nitride layer may include at least one of titanium, tantalum, molybdenum, and tungsten.
- The upper electrode may include at least one of metal, metal nitride, and metal oxynitride.
- The upper electrode may include a metal including at least one of Ti, Ta, Mo, W, TiW, TiSi, and TaSi.
- The upper electrode may include a metal nitride including at least one of TiN, TaN, WN, MoN, NbN, TiSiN, TiAIN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, TaSiN, and TaAlN.
- The upper electrode may include a metal oxynitride including at least one of TiON, TiAION, WON, and TaON.
- The phase change material pattern may include at least one of Ge—Sb—Te, Sb—Te, As—Sb—Te, and Sb—Se.
- The phase change material pattern may further include at least one metal.
- The lower electrode may include at least one of metal nitride, metal, metal oxynitride, silicide, and conductive carbon.
- The lower electrode may include at least one of Ti, Ta, Mo, W, TiN, TaN, WN, MoN, NbN, TiSiN, TiAIN, ZrSiN, WSiN, WBN, ZrAIN, MoSiN, TaSiN, TaAIN, TiW, TiSi, TaSi, TiON, TiAION, WON, and TaON.
- At least one of the above and other features and advantages may also be realized by providing a method of manufacturing a nonvolatile memory device, including forming a lower electrode on a semiconductor substrate, forming a phase change material pattern on the lower electrode, forming an adhesion pattern on the phase change material pattern, and forming an upper electrode on the adhesion pattern, wherein the adhesion pattern includes a conductor including nitrogen.
- The adhesion pattern and the upper electrode may each independently include a metal nitride layer or a metal oxynitride layer, and a ratio of metal to nitrogen in the metal nitride or oxynitride layer in the adhesion pattern may be different from a ratio of metal to nitrogen in the metal nitride or oxynitride layer in the upper electrode.
- The adhesion pattern and the upper electrode may be formed in a sputtering device using argon and nitrogen plasma on a metal target, and the adhesion pattern may include a metal nitride layer formed under a partial pressure of nitrogen that results in a total pressure in the sputtering device, measured as the partial pressure of nitrogen increases, being different than a total pressure in the sputtering device under the same partial pressure of nitrogen, measured as the partial pressure of nitrogen decreases.
- The adhesion pattern may include a metal nitride layer, and a ratio of metal to nitrogen in the metal nitride layer may be about 1:0.95 to about 1:1.03.
- The metal of the metal nitride layer may include at least one of titanium, tantalum, molybdenum, and tungsten.
- The upper electrode may include at least one of metal, metal nitride, and metal oxynitride.
- The upper electrode may include a metal including at least one of Ti, Ta, Mo, W, TiW, TiSi, and TaSi.
- The upper electrode may include a metal nitride including at least one of TiN, TaN, WN, MoN, NbN, TiSiN, TiAIN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, TaSiN, and TaAlN.
- The upper electrode may include a metal oxynitride including at least one of TiON, TiAlON, WON, and TaON.
- The phase change material pattern may include at least one of Ge—Sb—Te, Sb—Te, As—Sb—Te, and Sb—Se.
- The phase change material pattern may further include at least one metal layer.
- The lower electrode may include at least one of metal nitride, metal, metal oxynitride, silicide, and conductive carbon.
- The above and other features and advantages will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:
-
FIG. 1 illustrates a cross-sectional view of a nonvolatile memory device according to an embodiment; -
FIG. 2 illustrates a graph of a generic curve of a sputter device forming an adhesion pattern according to an embodiment; -
FIG. 3 illustrates a graph of the distribution of a reset current when using an adhesion pattern according to an embodiment; -
FIGS. 4 through 6 illustrate cross-sectional views of a nonvolatile memory device according to an embodiment; -
FIG. 7 illustrates a block diagram of a memory cell array including a nonvolatile memory device according to an embodiment; -
FIG. 8 illustrates a layout of a memory cell array including a nonvolatile memory device according to an embodiment; -
FIG. 9 illustrates a cross-sectional view along the line I-I′ ofFIG. 8 ; -
FIGS. 10A through 10D illustrate cross-sectional views of a method of forming a nonvolatile memory device according to an embodiment; -
FIG. 11 illustrates a block diagram of a memory cell array including a nonvolatile memory device according to an embodiment; -
FIG. 12 illustrates a layout of a memory cell array including a nonvolatile memory device according to an embodiment; -
FIG. 13 illustrates a cross-sectional view of a nonvolatile memory device according to an embodiment; and -
FIG. 14 illustrates a block diagram of a system according to an embodiment. - Korean Patent Application No. 10-2008-0014940, filed on Feb. 19, 2008, in the Korean Intellectual Property Office, and entitled: “Nonvolatile Memory Devices and Methods of Forming the Same,” is incorporated by reference herein in its entirety.
- Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
- In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.
- As used herein, the expressions “at least one,” “one or more,” and “and/or” are open-ended expressions that are both conjunctive and disjunctive in operation. For example, each of the expressions “at least one of A, B, and C,” “at least one of A, B, or C,” “one or more of A, B, and C,” “one or more of A, B, or C” and “A, B, and/or C” includes the following meanings: A alone; B alone; C alone; both A and B together; both A and C together; both B and C together; and all three of A, B, and C together. Further, these expressions are open-ended, unless expressly designated to the contrary by their combination with the term “consisting of.” For example, the expression “at least one of A, B, and C” may also include an nth member, where n is greater than 3, whereas the expression “at least one selected from the group consisting of A, B, and C” does not.
- As used herein, the expression “or” is not an “exclusive or” unless it is used in conjunction with the term “either.” For example, the expression “A, B, or C” includes A alone; B alone; C alone; both A and B together; both A and C together; both B and C together; and all three of A, B, and C together, whereas the expression “either A, B, or C” means one of A alone, B alone, and C alone, and does not mean any of both A and B together; both A and C together; both B and C together; and all three of A, B, and C together.
- As used herein, the terms “a” and “an” are open terms that may be used in conjunction with singular items or with plural items. For example, the term “a metal nitride” may represent a single compound, e.g., titanium nitride, or multiple compounds in combination, e.g., titanium nitride mixed with tungsten nitride.
- It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element, or intervening elements may be present. When an element is referred to as being “directly connected” or “directly coupled” to another element, there may be no intervening elements present.
- It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first region/layer could be termed a second region/layer, and, similarly, a second region/layer could be termed a first region/layer without departing from the teachings of the disclosure.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. It will be understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
- Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present application, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
-
FIG. 1 illustrates a cross-sectional view of a nonvolatile memory device according to an embodiment. Referring toFIG. 1 , a lower insulatinglayer 112 may be disposed on asemiconductor substrate 100 of a nonvolatile memory device. The lowerinsulating layer 112 may include, e.g., a silicon oxide layer. Alower electrode 110 may be disposed in afirst contact hole 110 a that penetrates the lower insulatinglayer 112. A phasechange material pattern 120 and anupper electrode 140 may be sequentially stacked on thelower electrode 110. The phasechange material pattern 120 and theupper electrode 140 may have an aligned sidewall. Theupper electrode 140 may be connected to abit line 160 through a bitline contact plug 150. An upper insulating layer may be disposed between the lower insulatinglayer 112 and thebit line 160. - An
adhesion pattern 130 may be disposed between the phasechange material pattern 120 and theupper electrode 140. Theadhesion pattern 130 may advantageously improve adhesion between theupper electrode 140 and the phasechange material pattern 120. - The
lower electrode 110 may be in contact with at least a portion of a bottom surface of the phasechange material pattern 120. A bottom surface of thelower electrode 110 may be electrically connected to source/drain regions in thesemiconductor substrate 100. Thelower electrode 110 may include a material in which resistivity increases in proportion to a rise in temperature, and may heat a region in contact with the phasechange material pattern 120. - Titanium may be included in the
adhesion pattern 130 to advantageously increase adhesion between theupper electrode 140 and the phasechange material pattern 120. The titanium, however, may diffuse into the phasechange material pattern 120. The diffusion of titanium into the phasechange material pattern 120 may cause a reset current of the phasechange material pattern 120 to undesirably increase. Such an increase in the reset current may be detrimental to data write speeds, i.e., may slow down data writing. - If the thickness of the titanium is decreased, or the titanium is removed, an undesirable lifting phenomenon may occur, due to a reduction in adhesion in the interface between the phase
change material pattern 120 and theupper electrode 140. Further, if a thickness of the titanium is decreased or the titanium is removed, the reset current may also undesirably increase due to parasitic resistance between the phasechange material pattern 120 and theupper electrode 140. - To overcome problems of the lifting and/or the increase of the reset current, a material which will be used as a new adhesion pattern is needed. If resistances of the
adhesion pattern 130 and theupper electrode 140 are small, the set resistance may be reduced, thereby beneficially increasing the speed of a reading operation. Thus, resistivities of theadhesion pattern 130 and theupper electrode 140 should be decreased in order to advantageously reduce the set resistance. - Specifically, the
adhesive pattern 130 and theupper electrode 140 may include, e.g., a metal nitride layer or a metal oxynitride layer. The ratio of metal to nitrogen in the metal nitride layer or the metal oxynitride layer may be lower in theadhesion pattern 130 than in theupper electrode 140. As a result, a reset current of a PRAM may be beneficially reduced by more than about 50%, compared with a conventional PRAM. For example, theadhesion pattern 130 may include a metal nitride layer including metal and nitrogen. The ratio of metal to nitrogen in the metal nitride layer may be about 1:0.95 to about 1:1.03. The metal of the metal nitride layer of theadhesion pattern 130 may include at least one of titanium, tantalum, molybdenum, and tungsten. - The
upper electrode 140 may include at least one of a metal layer, a metal nitride layer, and a metal oxynitride layer. Where theupper electrode 140 includes a metal layer, the metal layer may include at least one of, e.g., Ti, Ta, Mo, W, TiW, TiSi, and TaSi. Where theupper electrode 140 includes the metal nitride layer, the metal nitride layer may include at least one of, e.g., TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, ZrSiN, WSiN, WBN, ZrAIN, MoSiN, TaSiN, and TaAlN. Where theupper electrode 140 includes the metal oxynitride layer, the metal oxynitride layer may include at least one of, e.g., TION, TiAION, WON, and TaON. - The phase
change material pattern 120 may include at least one of Ge—Sb—Te, Sb—Te, As—Sb—Te, and Sb—Se. In an implementation, the phasechange material pattern 120 may include Ge2SbTe5 as the Ge—Sb—Te material. In implementation, the phasechange material pattern 120 may include at least one of an As—Sb-metal compound, an As—Ge—Te-metal compound, a metal-Sb—Te-metal compound, a 5A group element-Sb—Te-metal compound, a 6A group element-Sb—Te-metal compound, a 5A group element-Sb—Se-metal compound, and a 6A group element-Sb—Se-metal compound. The 5A group element may include, e.g., nitrogen (N) or phosphorus (P), and the 6A group element may include, e.g., oxygen (O) or sulfur (S). A composition ratio of the compounds may vary. - The
lower electrode 110 may serve to heat the phasechange material pattern 120. Thelower electrode 110 may include at least one of metal, metal nitride, metal oxynitride, silicide, and conductive carbon. Wherelower electrode 110 includes metal, the metal may include at least one of, e.g., Ti, Ta, Mo, W, TiW, TiSi, and TaSi. Where thelower electrode 110 includes metal nitride, the metal nitride may include at least one of, e.g., TiN, TaN, WN, MoN, NbN, TiSiN, TiAIN, ZrSiN, WSiN, WBN, ZrAIN, MoSiN, TaSiN, and TaAIN. Where thelower electrode 110 includes metal oxynitride, the metal oxynitride may include at least one of, e.g., TiON, TiAION, WON, and TaON. - The diameter of the lower electrode may be smaller than that of the phase
change material pattern 120. The lower diameter of thelower electrode 110 may decrease a cross-section of a resistance, thereby increasing resistive value. Thus, when the resistivity is high, the temperature may be greatly increased with a low power. The ability to achieve a high temperature with low power, i.e., low current, may help enable faster data write speeds by decreasing the reset current. - The
semiconductor substrate 100 may include a lower structure (not shown). - The lower structure may include, e.g., a diode or transistor. The
semiconductor substrate 100 may include at least one of a silicon substrate, a germanium substrate, and a SOI substrate. - The lower
insulating layer 112 and the upper insulatinglayer 122 may include at least one of a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer. The lowerinsulating layer 112 may include an impurity. The lowerinsulating layer 112 may be formed using at least one of a chemical vapor deposition (CVD) method, a spin coating method, and a plasma chemical vapor deposition (PCVD) method. A top surface of the lower insulatinglayer 112 and/or a top surface of the upper insulatinglayer 122 may be planarized. The lowerinsulating layer 112 and the upper insulatinglayer 122 may have a multilayer structure. Thus, each of the layers may include a different material. -
FIG. 2 illustrates a graph of a curve in a sputter device forming an adhesion pattern according to an embodiment. Referring toFIG. 2 , the graph represents a change of pressure of the sputtering device according to a ratio of argon (Ar) to nitrogen (N2), when the target of the sputter device is titanium (Ti) and the total gas flow rate is fixed. The pumping speed of the sputter device may be uniform. - As shown in
FIG. 2 , if the partial pressure of nitrogen is increased relative to argon, a pressure of the sputtering device is reduced, because titanium of the sputter target combines with nitrogen to increase the amount of titanium nitride formed. - Referring to
FIG. 2 , a region may exist where the pressure of the sputtering device, measured while increasing the partial pressure of nitrogen, is different from the pressure of the sputtering device, measured while decreasing the partial pressure of nitrogen. The region in which the measured pressures are different is referred to as a hysteresis region. At the upper and lower bounds of the hysteresis region, the boundary where the pressures divides when the partial pressure of nitrogen is low is a first region (A1), and the boundary where the measured pressure divides when the partial pressure of nitrogen is high is a second region (A2). - When the partial pressure of nitrogen is less than A1, the material deposited on the
semiconductor substrate 100 is TiN, rich in Ti, i.e., including abundant Ti. When the partial pressure of nitrogen is greater than A2, the material deposited on thesemiconductor substrate 100 is TiN rich in N, i.e., including abundant N. When the partial pressure of nitrogen equals A1, the material deposited on thesemiconductor substrate 100 is TiNx, and when the partial pressure of nitrogen equals A2, the material deposited on thesemiconductor substrate 100 is TiNy. - When the partial pressure of nitrogen is in the region between A1 and A2, the material deposited on the
semiconductor substrate 100 is TiNZ. Here, x may be smaller than y. Also, z may be about x to about y. - If the
adhesion pattern 130 were to be formed of only titanium (Ti), an undesirable lifting phenomenon, where theadhesion pattern 130 is lifted, may occur during an annealing process performed after formation of theadhesion pattern 130. However, if theadhesion pattern 130 includes TiNy, i.e., formed with a partial pressure of nitrogen at the A2 position, the lifting problem may be prevented. Moreover, if theadhesion pattern 130 is formed of TiNy, an undesirable phenomenon where Ti diffuses into the phasechange material pattern 120 may be considerably reduced, leading to high data write speeds. Moreover, in contrast to nitrogen-rich materials (i.e., TiN including abundant N formed by a partial pressure of nitrogen greater than A2) a resistivity of the TiNy may be lower than the resistivity of TiN including abundant N. Thus, as compared to a nitrogen-rich adhesion pattern 130 formed with a partial pressure of nitrogen greater than A2, the set resistance using anadhesion pattern 130 of TiNy may be reduced, enabling high data read speeds. The value “y” in TiNy may be 0.95≦y≦1.03. - With respect to the
upper electrode 140 formed on theadhesion pattern 130, forming TiN including abundant N is a simple process because a continuous process may be performed using the same equipment. TiN including abundant N used as theupper electrode 140 may include a material formed at a region exceeding the A2 position inFIG. 2 . - As described above, the
adhesion pattern 130 may be formed using a partial pressure of nitrogen corresponding to a point A2 at the upper bound of the hysteresis region. However, embodiments are not limited to a nitrogen partial pressure A2, For example, according to other embodiments, theadhesion pattern 130 may include TiNz, formed using a partial pressure of nitrogen that is within the hysteresis region. - According to an embodiment, the
adhesion pattern 130 may include TiNy. Theupper electrode 140 may include at least one of a metal layer, a metal nitride layer, and a metal oxynitride layer. Where theupper electrode 140 includes a metal layer, the metal layer may include at least one of, e.g., Ti, Ta, Mo, W, TiW, TiSi, and TaSi. Where theupper electrode 140 includes the metal nitride layer, the metal nitride layer may include at least one of, e.g., TiN, TaN, WN, MoN, NbN, TiSiN, TiAIN, ZrSiN, WSiN, WBN, ZrAIN, MoSiN, TaSiN, and TaAIN. Where theupper electrode 140 includes the metal oxynitride layer, the metal oxynitride layer may include at least one of, e.g., TiON, TiAlON, WON, and TaON. - According to an embodiment, the
adhesion pattern 130 may include a different metal nitride or oxynitride layer. Theupper electrode 140 formed on theadhesion pattern 130 may include a metal nitride layer and a metal oxynitride layer having a different composition ratio from that of theunderlying adhesion pattern 130. For example, the nitrogen ratio, i.e., the fraction of nitrogen, in theadhesion pattern 130 may be less than that in theupper electrode 140. -
FIG. 3 illustrates a graph of a cumulative distribution of the reset current when using an adhesion pattern according to an embodiment. Referring toFIG. 3 , the graph shows a beneficial reduction of the reset current of about 50%, compared with the conventional art. The x axis represents a reset current and the y axis represents a cumulative distribution. The reset current may be different according to a first phase change and a second phase change. The reset current may saturate according to the number of phase change operations. According to an embodiment, in the case of a second phase change, the reset current may be desirably reduced by about 50% compared with a conventional adhesion pattern of Ti. Theadhesion pattern 130 may include TiNy formed in the A2 region. -
FIGS. 4 through 6 illustrate cross-sectional views of a nonvolatile memory device according to an embodiment. Referring toFIG. 4 , a lower insulatinglayer 112 may be disposed on asemiconductor substrate 100 of a nonvolatile memory device. The lowerinsulating layer 112 may include, e.g., a silicon oxide layer. A phasechange material pattern 120 and anupper electrode 140 may be sequentially stacked on the lower insulatinglayer 112. The phasechange material pattern 120 and theupper electrode 140 may have an aligned sidewall. Anadhesion pattern 130 may be disposed between the phasechange material pattern 120 and theupper electrode 140. Theadhesion pattern 130 may advantageously improve adhesion between theupper electrode 140 and the phasechange material pattern 120, preventing a lifting problem from occurring. - A
lower electrode 110 may be disposed in afirst contact hole 110 a that penetrates the lower insulatinglayer 112. Thelower electrode 110 may be in contact with at least a portion of a bottom surface of the phasechange material pattern 120. A bottom surface of thelower electrode 110 may be electrically connected to a source/drain of a transistor formed in thesemiconductor substrate 100. - The
lower electrode 110 may include a material in which resistivity increases in proportion to temperature, and may heat a region that is in contact with the phasechange material pattern 120. - The
upper electrode 140 may be connected to abit line 160, through a bitline contact plug 150. An upper insulatinglayer 122 may be disposed between the lower insulating 112 and thebit line 160. Aprotection layer 132 may be disposed on sides of the phasechange material pattern 120, theadhesion pattern 130, and theupper electrode 140. Theprotection layer 132 may cover a top surface of theupper electrode 140. The bitline contact plug 150 may penetrate theprotection layer 132, so that the bitline contact plug 150 may be connected to theupper electrode 140. Theprotection layer 132 may include, e.g., a silicon nitride layer or a silicon oxynitride layer. -
FIG. 5 illustrates a cross-sectional view of a nonvolatile memory device according to an embodiment. Referring toFIG. 5 , a lower insulatinglayer 112 may be disposed on asemiconductor substrate 100 of a nonvolatile memory device. The lowerinsulating layer 112 may include, e.g., an oxide layer. A phasechange material pattern 120, alower adhesion pattern 134, anupper electrode 140, and anupper adhesion pattern 136 may be sequentially stacked on the lower insulatinglayer 112. The phasechange material pattern 120, thelower adhesion pattern 134, theupper electrode 140, and theupper adhesion pattern 136 may have an aligned sidewall. Thelower adhesion pattern 134 may beneficially improve adhesion between theupper electrode 140 and the phasechange material pattern 120, preventing a lifting problem from occurring. Theupper adhesion pattern 136 and thelower adhesion pattern 134 may include the same material. - A
lower electrode 110 may be disposed in afirst contact hole 110 a that penetrates the lower insulatinglayer 112. Thelower electrode 110 may be in contact with at least a portion of a bottom surface of the phasechange material pattern 120. A bottom surface of thelower electrode 110 may be electrically connected to a source/drain of a transistor formed in thesemiconductor substrate 100. Thelower electrode 110 may include a material in which resistivity increases in proportion to temperature, and may heat a region which is in contact with the phasechange material pattern 120. - The
upper adhesion pattern 136 may be connected to abit line 160, through a bitline contact plug 150. An upper insulatinglayer 122 may be disposed between the lower insulating 112 and thebit line 160. Aprotection layer 132 may be disposed on sides of the phasechange material pattern 120, thelower adhesion pattern 134, theupper electrode 140, and theupper adhesion pattern 136. Theprotection layer 132 may cover a top surface of theupper adhesion pattern 136. The bitline contact plug 150 may penetrate theprotection layer 132, so that the bitline contact plug 150 may be connected to theupper adhesion pattern 136. Theprotection layer 132 may include, e.g., a silicon nitride layer or a silicon oxynitride layer. - The
lower adhesion pattern 134 may include a conductor including nitrogen. Specifically, thelower adhesion pattern 134 may include TiNy formed in the A2 region as shown inFIG. 2 . Thelower adhesion pattern 134 and theupper electrode 140 may include, e.g., a metal nitride layer or a metal oxynitride layer. A ratio of metal to nitrogen in the metal nitride layer or the metal oxynitride layer may be different in thelower adhesion pattern 134 and theupper electrode 140. Thelower adhesion pattern 134 may include a metal nitride layer including metal and nitrogen, and a ratio of metal to nitrogen may be about 1:0.95 to about 1:1.03. The metal of the lower adhesion pattern may include at least one of titanium, tantalum, molybdenum, and tungsten. Theupper adhesion pattern 136 may include the same material as thelower adhesion pattern 134. -
FIG. 6 illustrates a cross-sectional view of a nonvolatile memory device according to an embodiment. Referring toFIG. 6 , a lower insulatinglayer 212 may be disposed on asemiconductor substrate 200 of a nonvolatile memory device. The lowerinsulating layer 212 may include, e.g., an oxide layer. A phasechange material pattern 220, anupper electrode 240, and anadhesion pattern 230 may be sequentially stacked on the lower insulatinglayer 212. The phasechange material pattern 220, theupper electrode 240, and theadhesion pattern 230 may have an aligned sidewall. Theadhesion pattern 230 may be disposed between the phasechange material pattern 220 and theupper electrode 240. Thelower adhesion pattern 230 may beneficially improve adhesion between theupper electrode 240 and the phasechange material pattern 220, preventing a lifting problem from occurring. Alower electrode 210 may be disposed in afirst contact hole 210 a that penetrates the lower insulatinglayer 212. Thelower electrode 210 may be in contact with at least a portion of a bottom surface of the phasechange material pattern 220. A bottom surface of thelower electrode 210 may be electrically connected to a source/drain of a transistor formed in thesemiconductor substrate 200. Thelower electrode 210 may include a material in which resistivity increases in proportion to temperature, and may heat a region that is in contact with the phasechange material pattern 220. Theupper electrode 240 may be directly connected to abit line 260. An upper insulatinglayer 222 may be disposed between the lower insulatinglayer 212 and thebit line 260. Aprotection layer 232 may be disposed on sides of the phasechange material pattern 220, theadhesion pattern 230, and theupper electrode 240. Theprotection layer 232 may include, e.g., a silicon nitride layer. -
FIG. 7 illustrates a block diagram of a memory cell array including a nonvolatile memory device according to an embodiment. Referring toFIG. 7 , a nonvolatile memory device according to an embodiment may include a memory cell array region (CA) and a peripheral circuit region (PA). In the memory cell array region (CA), a plurality of word lines may extend in an x direction and a plurality of bit lines may extend in a y direction, crossing the x axis. A memory cell may be disposed at a region where a word line (WL) crosses a bit line (BL). An x-decoder and a y-decoder may be disposed at the peripheral circuit region (PA). The plurality of word lines may be connected to the x-decoder and the plurality of bit lines may be connected to the y-decoder. The x-decoder may select a specific word line (WL) and the y-decoder may select a specific bit line (BL). The memory cell may include a phase change resistor (Rp) and a switching device (TA) electrically connected to the phase change resistor (Rp). The switching device (TA) may include a MOS transistor. - The memory cell may include a lower electrode, a phase change material pattern, an adhesion layer, and an upper electrode. The lower electrode, which may apply heat to the phase change material pattern, may be disposed between the phase change material pattern and the switching device. The phase change resistor (Rp) may be electrically connected to the bit line. The switching device (TA) may include a gate electrode, a source, and a drain. The gate electrode may be connected to the word line and the drain may be connected to the phase change resistor (Rp). The source may be connected to a common source line (CSL).
- Data may be stored in a selected memory cell by turning on a switching device (TA) of the selected memory cell, and forcing a recording current to the selected memory cell through a bit line (BL) connected to the selected memory cell. The recording current may include a reset current or a set current. The resistance state of the phase change material pattern of the selected memory cell may vary.
- For reading operations, a switching device of the selected memory cell may be turned on and a reading voltage may be applied to a bit line connected to the selected memory cell. Data stored in the phase change material pattern may be decoded by detecting a current flowing in the phase change material pattern.
-
FIG. 8 illustrates a layout of a memory cell array including a nonvolatile memory device according to an embodiment.FIG. 9 illustrates a cross-sectional view taken by the line I-I′ ofFIG. 8 . - Referring to
FIGS. 8 and 9 , adevice isolation layer 301 may be formed in asemiconductor substrate 300, to define anactive region 302. Theactive region 302 may include a region where a switching device may be disposed. Theactive region 302 may have, e.g., an elliptical shape or a rectangular shape, when viewed from a top plan view. A major axis of theactive region 302 may be disposed in parallel to a y axis. Theactive region 302 may be disposed to have a uniform distance in the x direction and in the y direction. The structure of theactive region 302 may vary. Twoword lines 306 may be disposed to cross oneactive region 302. A pair of switching devices may be disposed on oneactive region 302. Theword line 306 may include agate insulating layer 306 a and a gateconductive pattern 306 b, which are sequentially stacked on thesemiconductor substrate 300. Thegate insulating layer 306 a may include, e.g., a silicon oxide layer. The gateconductive pattern 306 b may include at least one of polysilicon, metal silicide, and metal. Aspacer 305 may be disposed on a sidewall of theword line 306. An impurity region may be formed in thesemiconductor substrate 300 at each side of theword line 306. The impurity region may form a source/drain of the switching device. Acommon source region 304 may be formed in thesemiconductor substrate 300, between a pair of the word lines 306. Afirst drain region 303 a and asecond drain region 303 b may be formed in thesemiconductor substrate 300 at outer sides of a pair of the word lines 306, respectively. - A first insulating
interlayer 309 may be formed on thesemiconductor substrate 300 including theword line 306. The first insulatinginterlayer 309 may include, e.g., a silicon oxide layer. Afirst contact plug 308 a may penetrate the first insulatinginterlayer 309, so that thefirst contact plug 308 a may be connected to thefirst drain 303 a andsecond drain 303 b. Thefirst contact plug 308 a may include conductive material. Alanding pad 308 b may be formed on a top surface of thefirst contact plug 308 a. A second contact plug 307 a may penetrate the first insulatinginterlayer 309, so that the second contact plug 307 a may be connected to thecommon source region 304. The first and second contact plugs 308 a and 307 a may include at least one of polysilicon, metal silicide, and metal. Acommon source line 307 b (CSL) may be formed on the second contact plug 307 a. Thecommon source line 307 b may extend in the same direction as theword line 306. Thecommon source line 307 b and thelanding pad 308 b may be concurrently formed. Thecommon source line 307 b and thelanding pad 308 b may each include at least one of polysilicon, metal silicide, and metal. - A lower insulating
interlayer 312 may be formed on thecommon source line 307 b and thelanding pad 308 b. A top surface of the lower insulatinginterlayer 312 may be planarized. Alower electrode 310 may penetrate the lower insulatinginterlayer 312, so that thelower electrode 310 may be connected to thelanding pad 308 b. A top surface of thelower electrode 310 may substantially coplanar with a top surface of the lower insulatinginterlayer 312. - A phase
change material pattern 320, anadhesion pattern 330, and anupper electrode 340 may be sequentially stacked on thelower electrode 310. Side surfaces of the phasechange material pattern 320, theadhesion pattern 330, and theupper electrode 340 may be aligned. - A bit
line contact plug 350 may be disposed on theupper electrode 340. Abit line 360 may extend in the y direction on the bitline contact plug 350. An upper insulatinginterlayer 322 may be disposed between thebit line 360 and the lower insulatinginterlayer 312. - The
adhesion pattern 330 and theupper electrode 340 may each independently include, e.g., a metal nitride layer or a metal oxynitride layer. However, a ratio of metal to nitrogen in the metal nitride layer or the metal oxynitride layer may be different in theadhesion pattern 330 and theupper electrode 340, respectively. Thus, the reset current of a PRAM according to an embodiment may be advantageously reduced by 50%, compared with a PRAM device not including theadhesion pattern 330 andupper electrode 340 of an embodiment. Theadhesion pattern 330 may include a metal nitride layer. The ratio of metal to nitrogen may be about 1:0.95 to about 1:1.03. The metal of theadhesion pattern 330 may include at least one of titanium, tantalum, molybdenum, and tungsten. -
FIGS. 10A through 10D illustrate cross-sectional views of a method of forming a nonvolatile memory device according to an embodiment. Referring toFIG. 10A , adevice isolation layer 301 may be formed in asemiconductor substrate 300, to define anactive region 302. Thedevice isolation layer 302 may be formed using, e.g., a shallow trench isolation process. Agate insulating layer 306 a may be formed on thesemiconductor substrate 300 including thedevice isolation layer 302. Thegate insulating layer 306 a may include, e.g., a silicon oxide layer. A gate conductive layer (not shown) may be formed on thegate insulating layer 306 a. Thegate insulating layer 306 a may include at least one of polysilicon, metal silicide, and metal. A first hard mask may be formed on the gate conductive layer. A photoresist pattern (not shown) may be formed on the gate conductive layer. The gate conductive layer may be etched using the photoresist pattern as an etching mask to form a gateconductive pattern 306 b. Thegate insulating layer 306 a disposed on both sides of the gateconductive pattern 306 b may be removed by, e.g., a wet etching process. - A
word line 306 may include the gateconductive pattern 306 b and thegate insulating layer 306 a. Aspacer 305 may be formed on a sidewall of theword line 306 using, e.g., an anisotropic etching process. Thespacer 305 may include, e.g., a silicon nitride layer. An ion implantation process may be performed on thesemiconductor substrate 300 including thespacer 305, to form impurity regions in thesemiconductor substrate 300 at each side of theword line 306. In the case of a NMOS, the impurity region may include an N-type, and in the case of a PMOS, the impurity region may include a P-type. Acommon source region 304 may be formed in thesemiconductor substrate 300 between a pair of the word lines 306. Afirst drain region 303 a and asecond drain region 303 b may be formed in thesemiconductor substrate 300 at outer sides of a pair of the word lines 306, respectively. - Referring to
FIG. 10B , a first insulatinginterlayer 309 may be formed on thesemiconductor substrate 300 including the impurity regions. The insulating interlayer may include, e.g., a silicon oxide layer. A top surface of the first insulatinginterlayer 309 may be planarized. A photoresist pattern may be formed on the first insulatinginterlayer 309. The first insulatinginterlayer 309 may be etched through to the impurity region, using the photoresist pattern as etching mask, to form a contact hole. The contact hole may include afirst contact hole 318 a formed on the first andsecond drain regions second contact hole 317 a formed on thecommon source region 304. The first and second contact holes 318 a and 317 a may be filled with conductive material. A planarization process may be performed to form afirst contact plug 308 a and a second contact plug 307 a. The planarization process may include, e.g., an etch-back process or a chemical mechanical polishing process. A top surface of thefirst contact plug 308 a may be substantially coplanar with a top surface of the first insulatinginterlayer 309. A common source conductive layer may be formed on the first insulatinginterlayer 309, and a photoresist pattern may be formed on the common source conductive layer. The common source conductive layer may be etched, using the photoresist pattern as an etching mask, to form alanding pad 308 b on thefirst contact plug 308 a, and acommon source line 307 b on the second contact plug 307 a. Thecommon source line 307 b may extend in the same direction as the word line. The common source conductive layer may include at least one of polysilicon, metal silicide, and metal. - Referring to
FIG. 10C , a lower insulatinglayer 312 may be formed on thesemiconductor substrate 300 including thecommon source line 307 b. The lowerinsulating layer 312 may include, e.g., a silicon oxide layer. A top surface of the lower insulatinglayer 312 may be planarized. A photoresist pattern may be formed on the lower insulatinglayer 312. The lowerinsulating layer 312 may be etched, using the photoresist pattern as an etching mask, to form a lowerelectrode contact hole 310 a. The lowerelectrode contact hole 310 a may expose at least a portion of thelanding pad 308 b. - A lower electrode layer (not shown) may be deposited on the
semiconductor substrate 300 including the lowerelectrode contact hole 310 a. A planarization process may be performed on thesemiconductor substrate 300 including the lower electrode layer, to form alower electrode 310 filling the lowerelectrode contact hole 310 a. - Referring to
FIG. 10D , a phase change material layer (not shown), an adhesion layer (not shown), and an upper electrode layer (not shown) may be sequentially stacked on thesemiconductor substrate 300 including thelower electrode 310. The upper electrode layer and the adhesion layer may be continuously formed using the same equipment, for simplicity and lower costs. - A photoresist pattern may be formed on the upper electrode layer. The phase change material layer, the adhesion layer, and the upper electrode layer may be continuously etched, using the photoresist pattern as an etching mask, to form an
upper electrode 340, anadhesion pattern 330, and a phasechange material pattern 320, respectively. - Referring to
FIG. 9 again, an upper insulatinglayer 322 may be formed on thesemiconductor substrate 300 including theupper electrode 340. A top surface of the upper insulatinglayer 322 may be planarized. A photoresist pattern may be formed on the upper insulatinglayer 322. The upper insulatinglayer 322 may be etched, using the photoresist pattern as an etching mask, to form a bitline contact hole 350 a. The bitline contact hole 350 a may expose at least a portion of theupper electrode 340. A bit line contact conductor may be conformally formed on thesemiconductor substrate 300 including the bitline contact hole 350 a. The bit line contact conductor may fill the bitline contact hole 350 a. Thesemiconductor substrate 300 including the filled bitline contact hole 350 a may be planarized to form a bitline contact plug 350. The bit line contact conductor may then fill only the bitline contact hole 350 a. A bit line layer may be formed on thesemiconductor substrate 300 including the bitline contact plug 350. A photoresist pattern may be formed on the bit line layer. The bit line layer may be patterned, using the photoresist pattern as a mask, to form abit line 360. The bit line layer may include at least one of polysilicon, metal silicide, and metal. -
FIG. 11 illustrates a block diagram of a memory cell array including a nonvolatile memory device according to an embodiment. A diode may be used as a switching device, instead of a MOS transistor. Referring toFIG. 11 , the cell array may include a plurality of bit lines (BL), a plurality of word lines (WL) crossing the plurality of bit lines (BL), and a phase change memory cell disposed at an intersection between the bit line (BL) and the word line (WL). - The phase
change memory cell 10 may include a phase change resistor (Rp′) electrically connected to one of the bit lines (BL), and a cell diode electrically connected to the phase change resistor (Rp′). The phase change resistor (Rp′) may include a sequentially stacked lower electrode, phase change material pattern, adhesion pattern, and upper electrode. The cell diode (D) may include, e.g., a P-type transistor and an N-type transistor. The lower electrode may be electrically connected to a P-type semiconductor of the cell diode, and the upper electrode may be electrically connected to one of the bit lines. Also, an N-type semiconductor of the cell diode of the cell diode may be electrically connected to one of the word lines (WL). The bit line (BL) may be connected to a Y-decoder, and the word line (WL) may be connected to an X-decoder. The Y-decoder may select any one of the bit lines and the X-decoder may select any one of the word lines. -
FIG. 12 illustrates a layout of a memory cell array including a nonvolatile memory device according to an embodiment.FIG. 13 illustrates a cross-sectional view of a nonvolatile memory device according to an embodiment. - A
device isolation layer 501 may be formed in a predetermined region of asemiconductor substrate 500 of a first conductivity type, to define anactive region 502 having a line shape. An impurity of a type different from the first conductivity type may be diffused into theactive region 502, and theactive region 502 may act as a word line (WL). According to another embodiment, the word line (WL) may include, e.g., a conductive interconnection or an epitaxial semiconductor pattern, stacked on thesemiconductor substrate 500. - A lower insulating
interlayer 512 may be provided onto the word line (WL) and thedevice isolation layer 501. At least a portion of an upper surface of the word line (WL) may be exposed by acell diode hole 505 that penetrates the lower insulatinginterlayer 512. A cell diode D may be provided into thecell diode hole 505. The cell diode D may include, e.g., an N-type semiconductor 570 and a P-type semiconductor 572. That is, the cell diode D may correspond to a vertical cell diode. A top surface of the cell diode D may be lower than a top surface of the lower insulatinginterlayer 512. Acell diode electrode 574 and alower electrode 510 may be sequentially disposed on the cell diode D. A top surface of thelower electrode 510 may be substantially coplanar with a top surface of the lower insulatinglayer 512. Thecell diode electrode 574 may include, e.g., metal silicide. The metal silicide may be formed by a silicide process. - A phase
change material pattern 520, anadhesion pattern 530, and anupper electrode 540 may be disposed on thelower electrode 510. Side surfaces of the phasechange material pattern 520, theadhesion pattern 530, and theupper electrode 540 may be aligned. A bitline contact plug 550 may be disposed on theupper electrode 540. Abit line 560 may be disposed on the bitline contact plug 550. An upper insulatinginterlayer 522 may be disposed between thebit line 560 and the lower insulatinginterlayer 512. - According to an embodiment, a cell diode D, a
cell diode electrode 574, alower electrode 510, and a phasechange material pattern 520 may be disposed in thecell diode hole 505. Thelower electrode 510 may be surrounded by a spacer (not shown) formed on thecell diode electrode 574. A top surface of thelower electrode 510 may be lower than a top surface of the lower insulatinglayer 512. The phasechange material pattern 520 may have a “T” shape. - A method of forming a nonvolatile memory device according to an embodiment will be described. Referring to
FIG. 13 , adevice isolation layer 501 may be formed in a predetermined region of asemiconductor substrate 500 having a first conductivity type, to define anactive region 502 having a line shape. An impurity ion of a second conductivity type, different from the first conductivity type, may be diffused into theactive region 502, to form a word line (WL) of the second conductivity type. The first conductivity type may be a P-type and the second conductivity type may be an N-type. - A lower insulating
interlayer 512 may be formed on thesemiconductor substrate 500 including the word line (WL). The lower insulatinginterlayer 512 may be patterned to form acell diode hole 505, which exposes at least a portion of a top surface of the word line (WL). An N-type semiconductor 570 and a P-type semiconductor 572 may be sequentially formed in thecell diode hole 505. The N-type semiconductor 570 and the P-type semiconductor 572 may be formed, e.g., using the word line (WL) as a seed by, e.g., a selective epitaxial growth (SEG). The N-type semiconductor 570 and the P-type semiconductor 572 may be, e.g., in-situ doped. - According to an embodiment, a top surface of the P-
type semiconductor 572, formed by, e.g., selective epitaxial growth (SEG), may be higher than a top surface of the lower insulatinginterlayer 512. Thus, the P-type semiconductor 572 and the lower insulatinginterlayer 512 may be planarized. A top surface of the planarized P-type semiconductor 572 may be selectively recessed. - The N-
type semiconductor 570 and the P-type semiconductor 572 may constitute a cell diode D. Acell diode electrode 574 may be selectively formed on the P-type semiconductor 572. Thecell diode electrode 574 may include, e.g., metal silicide. The metal silicide may be formed by, e.g., a silicide process. A top surface of thecell diode electrode 574 may be lower than a top surface of the lower insulatinginterlayer 512. Alower electrode 510 may be formed on thecell diode electrode 574. A top surface of thelower electrode 510 may be substantially coplanar with the lower insulatinginterlayer 512. That is, a conductive layer may be conformally formed to fill thecell diode hole 505, and the conductive layer may then be planarized to form thelower electrode 510. The planarization may be performed by, e.g., an etch-back process or a chemical mechanical polishing process. - A phase change material layer, an adhesion layer, and an upper electrode layer may be formed on the
semiconductor substrate 500 including thelower electrode 510. The phase change material layer, the adhesion layer, and the upper electrode layer may be sequentially patterned to form anupper electrode 540, anadhesion pattern 530, and a phasechange material pattern 520, respectively. Thelower electrode 510, the phasechange material pattern 520, theadhesion pattern 530, and theupper electrode 540 may constitute a phase change resistor (RP′). - An upper insulating
interlayer 522 may be formed on thesemiconductor substrate 500 including theupper electrode 540. The upper insulatinginterlayer 522 may be patterned to form a bitline contact hole 550 a. The bitline contact hole 550 a may expose at least a portion of a surface of theupper electrode 540. A conductive material may be deposited to fill the bitline contact hole 550 a, and the conductive material may then be patterned to form a bitline contact plug 550. - According to an embodiment, the bit
line contact plug 550 and abit line 560 may be substantially simultaneously formed. Specifically, the bitline contact plug 550 and thebit line 560 may be substantially simultaneously formed by forming a conductive material in the bitline contact hole 550 a, and patterning the conductive material. -
FIG. 14 illustrates a block diagram of a system according to an embodiment. Referring toFIG. 14 , asystem 1000, e.g., a computer system and/or a mobile device, may include amicroprocessor 1100 electrically connected to abus 1001, auser interface 1200, amodem 1300, e.g., a base band chipset, and a phasechange memory device 1400. The phasechange memory device 1400 may include the phase change memory device as described above. The phasechange memory device 1400 may store data treated by themicroprocessor 1100. If the system according to an embodiment includes a mobile device, abattery 1500 for supplying a system operation voltage may also be provided. An applied chipset, a camera image processor, a mobile DRAM, and a NAND flash device, or the like, may also be provided to thesystem 1000. - Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.
Claims (13)
1. A nonvolatile memory device, comprising:
a lower electrode on a semiconductor substrate;
a phase change material pattern on the lower electrode;
an adhesion pattern on the phase change material pattern; and
an upper electrode on the adhesion pattern,
wherein the adhesion pattern includes a conductor including nitrogen.
2. The nonvolatile memory device as claimed in claim 1 , wherein the adhesion pattern and the upper electrode each independently include a metal nitride layer or a metal oxynitride layer, and a ratio of metal to nitrogen in the metal nitride or oxynitride layer in the adhesion pattern is different from a ratio of metal to nitrogen in the metal nitride or oxynitride layer in the upper electrode.
3. The nonvolatile memory device as claimed in claim 1 , wherein the adhesion pattern includes a metal nitride layer, and a ratio of metal to nitrogen in the metal nitride layer is about 1:0.95 to about 1:1.03.
4. The nonvolatile memory device as claimed in claim 3 , wherein the metal of the metal nitride layer includes at least one of titanium, tantalum, molybdenum, and tungsten.
5. The nonvolatile memory device as claimed in claim 1 , wherein the upper electrode includes at least one of metal, metal nitride, and metal oxynitride.
6. The nonvolatile memory device as claimed in claim 5 , wherein the upper electrode includes a metal including at least one of Ti, Ta, Mo, W, TiW, TiSi, and TaSi.
7. The nonvolatile memory device as claimed in claim 5 , wherein the upper electrode includes a metal nitride including at least one of TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, TaSiN, and TaAlN.
8. The nonvolatile memory device as claimed in claim 5 , wherein the upper electrode includes a metal oxynitride including at least one of TiON, TiAlON, WON, and TaON.
9. The nonvolatile memory device as claimed in claim 1 , wherein the phase change material pattern includes at least one of Ge—Sb—Te, Sb—Te, As—Sb—Te, and Sb—Se.
10. The nonvolatile memory device as claimed in claim 9 , wherein the phase change material pattern further includes at least one metal.
11. The nonvolatile memory device as claimed in claim 1 , wherein the lower electrode includes at least one of metal nitride, metal, metal oxynitride, silicide, and conductive carbon.
12. The nonvolatile memory device as claimed in claim 11 , wherein the lower electrode includes at least one of Ti, Ta, Mo, W, TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, TaSiN, TaAlN, TiW, TiSi, TaSi, TiON, TiAlON, WON, and TaON.
13-24. (canceled)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/224,940 US20110315946A1 (en) | 2008-02-19 | 2011-09-02 | Nonvolatile memory device |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2008-0014940 | 2008-02-19 | ||
KR1020080014940A KR101394263B1 (en) | 2008-02-19 | 2008-02-19 | A nonvolatile memory device and formign method of forming the same |
US12/379,277 US8012789B2 (en) | 2008-02-19 | 2009-02-18 | Nonvolatile memory device and method of manufacturing the same |
US13/224,940 US20110315946A1 (en) | 2008-02-19 | 2011-09-02 | Nonvolatile memory device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/379,277 Division US8012789B2 (en) | 2008-02-19 | 2009-02-18 | Nonvolatile memory device and method of manufacturing the same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20110315946A1 true US20110315946A1 (en) | 2011-12-29 |
Family
ID=40954256
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/379,277 Expired - Fee Related US8012789B2 (en) | 2008-02-19 | 2009-02-18 | Nonvolatile memory device and method of manufacturing the same |
US13/224,940 Abandoned US20110315946A1 (en) | 2008-02-19 | 2011-09-02 | Nonvolatile memory device |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/379,277 Expired - Fee Related US8012789B2 (en) | 2008-02-19 | 2009-02-18 | Nonvolatile memory device and method of manufacturing the same |
Country Status (2)
Country | Link |
---|---|
US (2) | US8012789B2 (en) |
KR (1) | KR101394263B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110076826A1 (en) * | 2009-09-25 | 2011-03-31 | Applied Materials, Inc. | Passivating glue layer to improve amorphous carbon to metal adhesion |
US20190157551A1 (en) * | 2017-11-21 | 2019-05-23 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and method for forming the same |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI418027B (en) * | 2008-11-28 | 2013-12-01 | Powerchip Technology Corp | Phase-change memory devices and methods for fabricating the same |
US8138056B2 (en) * | 2009-07-03 | 2012-03-20 | International Business Machines Corporation | Thermally insulated phase change material memory cells with pillar structure |
US8105859B2 (en) * | 2009-09-09 | 2012-01-31 | International Business Machines Corporation | In via formed phase change memory cell with recessed pillar heater |
US8828788B2 (en) * | 2010-05-11 | 2014-09-09 | Micron Technology, Inc. | Forming electrodes for chalcogenide containing devices |
KR101781483B1 (en) * | 2010-12-03 | 2017-09-26 | 삼성전자 주식회사 | Method Of Forming Resistance Changeable Memory Device |
KR20130062211A (en) * | 2011-12-03 | 2013-06-12 | 에스케이하이닉스 주식회사 | Variable resistive memory device and method of fabricating the same |
US9853049B2 (en) * | 2016-04-21 | 2017-12-26 | Samsung Electronics Co., Ltd. | Memory devices having common source lines including layers of different materials |
US10902910B2 (en) * | 2019-06-25 | 2021-01-26 | International Business Machines Corporation | Phase change memory (PCM) with gradual reset characteristics |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7456420B2 (en) * | 2006-03-07 | 2008-11-25 | International Business Machines Corporation | Electrode for phase change memory device and method |
US7718989B2 (en) * | 2006-12-28 | 2010-05-18 | Macronix International Co., Ltd. | Resistor random access memory cell device |
US7803656B2 (en) * | 2006-06-29 | 2010-09-28 | Ips Ltd. | Method of depositing chalcogenide film for phase-change memory |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69223479T2 (en) * | 1991-09-27 | 1998-04-02 | Hitachi Metals Ltd | Target for reactive sputtering and method for forming a film using the target |
US7233054B1 (en) * | 2005-11-29 | 2007-06-19 | Korea Institute Of Science And Technology | Phase change material and non-volatile memory device using the same |
KR20070063808A (en) | 2005-12-15 | 2007-06-20 | 주식회사 하이닉스반도체 | Phase change ram device and method of manufacturing the same |
US8426967B2 (en) * | 2007-01-05 | 2013-04-23 | International Business Machines Corporation | Scaled-down phase change memory cell in recessed heater |
-
2008
- 2008-02-19 KR KR1020080014940A patent/KR101394263B1/en not_active IP Right Cessation
-
2009
- 2009-02-18 US US12/379,277 patent/US8012789B2/en not_active Expired - Fee Related
-
2011
- 2011-09-02 US US13/224,940 patent/US20110315946A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7456420B2 (en) * | 2006-03-07 | 2008-11-25 | International Business Machines Corporation | Electrode for phase change memory device and method |
US7803656B2 (en) * | 2006-06-29 | 2010-09-28 | Ips Ltd. | Method of depositing chalcogenide film for phase-change memory |
US7718989B2 (en) * | 2006-12-28 | 2010-05-18 | Macronix International Co., Ltd. | Resistor random access memory cell device |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110076826A1 (en) * | 2009-09-25 | 2011-03-31 | Applied Materials, Inc. | Passivating glue layer to improve amorphous carbon to metal adhesion |
US8278139B2 (en) * | 2009-09-25 | 2012-10-02 | Applied Materials, Inc. | Passivating glue layer to improve amorphous carbon to metal adhesion |
US8569105B2 (en) | 2009-09-25 | 2013-10-29 | Applied Materials, Inc. | Passivating glue layer to improve amorphous carbon to metal adhesion |
US20190157551A1 (en) * | 2017-11-21 | 2019-05-23 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and method for forming the same |
US11038101B2 (en) * | 2017-11-21 | 2021-06-15 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure having a phase change memory device |
Also Published As
Publication number | Publication date |
---|---|
US20090206318A1 (en) | 2009-08-20 |
KR20090089652A (en) | 2009-08-24 |
KR101394263B1 (en) | 2014-05-14 |
US8012789B2 (en) | 2011-09-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8012789B2 (en) | Nonvolatile memory device and method of manufacturing the same | |
USRE47506E1 (en) | Variable resistance memory device | |
US8871559B2 (en) | Methods for fabricating phase change memory devices | |
US7768016B2 (en) | Carbon diode array for resistivity changing memories | |
US7728319B2 (en) | Vertical phase change memory cell and methods for manufacturing thereof | |
JP5544104B2 (en) | Resistive memory element and method of forming the same | |
US20070063180A1 (en) | Electrically rewritable non-volatile memory element and method of manufacturing the same | |
US7582889B2 (en) | Electrically rewritable non-volatile memory element and method of manufacturing the same | |
US20080272355A1 (en) | Phase change memory device and method for forming the same | |
US20070108077A1 (en) | Spacer Electrode Small Pin Phase Change Memory RAM and Manufacturing Method | |
US8133758B2 (en) | Method of fabricating phase-change memory device having TiC layer | |
US20110044098A1 (en) | Nonvolatile Memory Cells Having Phase Changeable Patterns Therein for Data Storage | |
US20060108667A1 (en) | Method for manufacturing a small pin on integrated circuits or other devices | |
US20100096609A1 (en) | Phase change memory device having a layered phase change layer composed of multiple phase change materials and method for manufacturing the same | |
US8288752B2 (en) | Phase change memory device capable of reducing disturbance and method of manufacturing the same | |
US8686393B2 (en) | Integrated circuit semiconductor devices including channel trenches and related methods of manufacturing | |
US20080048293A1 (en) | Semiconductor device having heating structure and method of forming the same | |
TW201419449A (en) | Three dimensional memory array architecture | |
US8810003B2 (en) | Semiconductor device and method of fabricating the same | |
KR101481401B1 (en) | Nonvolatile meomory device | |
CN102820299A (en) | Semiconductor device | |
KR20120135089A (en) | Memory devices and method of manufacturing the same | |
KR20110009545A (en) | Method of forming semiconductor device having metal carbide electrode and related device | |
US20140131655A1 (en) | Semiconductor memory devices and methods of fabricating the same | |
US20180166502A1 (en) | Semiconductor device including a line pattern having threshold switching devices |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |