US20110309365A1 - Thin film transistor backplane - Google Patents
Thin film transistor backplane Download PDFInfo
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- US20110309365A1 US20110309365A1 US13/219,571 US201113219571A US2011309365A1 US 20110309365 A1 US20110309365 A1 US 20110309365A1 US 201113219571 A US201113219571 A US 201113219571A US 2011309365 A1 US2011309365 A1 US 2011309365A1
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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Abstract
A fabrication process for a device such as a backplane for a flat panel display includes depositing thin film layers on a substrate, forming a 3D template overlying the thin film layers, and etching the 3D template and the thin film layers to form gate lines and transistors from the thin film layers. An insulating or passivation layer can then be deposited on the gate lines and the transistors, so that column or data lines can be formed on the insulating layer.
Description
- Current flat panel displays such as LCD, LED, and electrophoretic displays generally include backplane circuitry for operation of picture elements or pixels that are arranged in rows and columns in the display. The backplane may, for example, implement an active matrix that is able to refresh an entire row of pixels at once. Such backplanes generally include an array of thin film transistors (TFTs), where one or more TFTs have their source or drain coupled to respective electrodes in a corresponding pixel. The TFTs for a row of pixels have gates coupled to a gate or row line corresponding to the row, and the TFTs corresponding to a column of pixels generally have their drains or sources coupled to a data or column line corresponding to the column.
- Conventional integrated circuit processing techniques such as precision photolithography can be difficult to employ for fabrication of a backplane for a large display because of the large area covered and because materials commonly employed in the displays are flexible and difficult to keep flat over the large area. In general, fabricating a TFT requires at least three masking levels, and more masking levels may be needed to form the backplane of a display. Accurately aligning mask patterns against each level is difficult for flexible substrates which have poor dimension stability.
- U.S. Pat. No. 7,202,179, entitled “Method of forming at least one Thin Film Device” describes fabrication processes using three-dimensional (3D) templates that can be imprinted on a large area such as the area of a flat panel display. Using these techniques, a 3D template is imprinted on top of a multilayer stack to be patterned. The 3D template generally has multiple levels, with each level corresponding to different thicknesses of the 3D template and a different underlying layer to be patterned. An anisotropic etching process can then thin the 3D template and etch through portions of the underlying layers that become exposed. The process etches deeper into the underlying layers where the 3D template was thinner. For example, the etch process may etch down through the bottom layer of a multi-layer stack where the 3D template was thinnest, but the other levels of the 3D template are thick enough that the portions of the bottom layer under other levels of the 3D template remain. After the process is complete, each layer of the multilayer stack is left with a pattern corresponding to the areas where the 3D template and overlying layers of the multilayer stack were thick enough to protect the layer.
- An advantage of using a 3D template in manufacture of a backplane for a display is that the multiple layers of the stack that are patterned with a single 3D template are automatically aligned with each other. Further, roll-to-roll imprinting techniques can cover the large area of a display. Etching multiple layers with a 3D template does have difficulty when producing signal lines or other structures that cross in different layers. For example, the row lines and data lines of a conventional backplane cross each other, so that a conventional fabrication process using 3D templates requires an undercut process (e.g., a wet etch process) to remove portions of the row or data line that are under portions of the data or row lines.
- In order to realize high yield manufacturing processes, methods for fabricating a backplane for a display that efficiently align overlying layers and that provide low defect rates are desired.
- In accordance with an aspect of the invention, a device fabrication process includes depositing thin film layers on a substrate, forming a 3D template overlying the thin film layers, and etching the 3D template and the thin film layers to form gate lines and transistors from the thin film layers. An insulating or passivation layer can then be deposited on the gate lines and the transistors, so that column or data lines can be formed on the insulating layer. The gate lines are respectively coupled to rows of the transistors, and the column lines are respectively coupled to columns of the transistors.
- Another embodiment of the invention is a system such as a flat-panel display or a backplane for a flat panel display. The system includes a self-aligned structure, a passivation layer overlying the self-aligned thin-film structure, and conductive traces on the passivation layer. The self-aligned structure includes gate lines and rows of thin-film transistors that are respectively gated by the gate lines. The conductive traces are subject to alignment variations relative to the self-aligned structure and include data lines that cross over the gate lines. Each of the data lines is coupled to a column of the thin-film transistors.
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FIG. 1 is a high level flow diagram of a process for fabricating a backplane in accordance with an embodiment of the invention. -
FIGS. 2A , 2B, 2C, and 2D show perspective views of structures created during a fabrication process for the backplane circuit in accordance with an embodiment of the invention. -
FIGS. 3A , 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K, 3L, and 3M show cross-sectional views of intermediate structures during a fabrication process for the backplane circuit in accordance with an embodiment of the invention. -
FIGS. 4A and 4B illustrate structures suitable for defect repair processes in a backplane in accordance with an embodiment of the invention. -
FIG. 5 is a circuit diagram for a display such as an LCD or electrophoretic display employing a backplane containing TFT circuitry in accordance with an embodiment of the invention. -
FIG. 6 is a circuit diagram for a LED display employing a backplane containing TFT circuitry in accordance with an embodiment of the invention. -
FIG. 7 shows a layout for a portion of a backplane corresponding to a pixel in an LED display in accordance with an embodiment of the invention. - Use of the same reference symbols in different figures indicates similar or identical items.
- In accordance with an aspect of the current invention, a fabrication process for circuitry such as a backplane having crossing signal lines can employ Self-Aligned Imprint Lithography (SAIL) for fabrication of circuit structures that require precisely controlled alignment and tolerances and still avoid the need for underetching.
FIG. 1 is a high level flow chart of anexemplary process 100 for forming a backplane in accordance with an embodiment of the invention. Fabrication of a backplane is described here as an illustrative example, but fabrication of other thin-film circuits having crossing signal lines could also benefit from use of the techniques illustrated inFIG. 1 . Afirst step 110 ofprocess 100 is providing a substrate. Generally, displays employ a rigid or flexible substrate that serves as a base for the backplane. Thin film device layers are then deposited upon the substrate instep 120. -
Steps Process 100 may also be employed upon a non-flexible substrate, while remaining within the spirit and scope of at least one embodiment. -
Step 130 is the imprinting of the 3D template on the thin film device layers formed instep 120. The thin film device layers and the 3D template structure are then selectively etched instep 140. This etching forms the rudimentary structure for a TFT array or other circuitry to be fabricated. The rudimentary structure for the backplane of a display includes multiple rows of TFTs. TFTs in a row can share a gate line, with the channel width of each TFT being approximately aligned with the gate line. The source and drain of each TFT are electrically isolated from the neighboring TFTs. Optionally, each row of the TFTs may have a continuous gate dielectric strip that underlies the TFTs in the row. -
Step 150 performs an in-line test and defect repair of TFTs of the thin-film circuit structure after the SAIL process but before fabrication of overlying layers. The in-line test can test for shorting of signal lines, e.g., gate lines and common lines, formed during the SAIL process. Identified shorts may then be repaired, for example, using laser cutting. -
Step 160 deposits an insulating layer on the rudimentary structure tested instep 150. Via holes through the insulating layer are then formed to expose contacts of the sources and drains of TFTs. Step 170 then deposits a conductive layer on the insulating layer for formation data lines and an array of pixel electrodes connected to TFT drains and sources, respectively. - The gates of TFTs in an array fabricated using processes described herein can be aligned with small area channel regions using a self-aligned process, and channel lengths can be defined with precision. The contacts of sources and drains of the TFTs can be made relatively large, so that alignment tolerances for data lines and contacts to electrodes are similarly large. The relatively large alignment tolerances allow the data lines, which cross the gate lines, to be fabricated separately, for example, using conventional techniques such as step-and-repeat photolithography, template imprinting, or trace printing techniques. Fabrication processes described here also advantageously allow thin film layers to be deposited onto flexible or non-flexible substrates prior to any patterning step and therefore can minimize the number of processing steps and reduce processing related contamination to the device layer. In addition, the present methods provide opportunities for performing in-line TFT testing and repairing, therefore improving manufacturing yield of backplanes. Furthermore, the device structure produced by the present method isolates possible shunt defects in the device layers thereby improving backplane performance and quality.
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FIGS. 2A , 2B, 2C, and 2D illustrate structures created during fabrication of a portion ofbackplane 200 in accordance with an exemplary embodiment of the invention.FIG. 2D , in particular, shows the completed portion ofbackplane 200.Backplane 200 can be a flexible circuit that includes an array ofthin film devices 290 that are used in operation of a display. A full version ofbackplane 200 would typically contain hundreds to thousands of row and columns ofTFTs 290 with the number ofdevices 290 being determined by the number of pixels in the display.Backplane 200 more specifically includes conductive row orgate lines 222 and ground orcommon lines 224 on a supportingsubstrate 210. A gate dielectric such as silicon nitride or other gatedielectric layer 232 ongate lines 222 is betweengate lines 222 and respective thin film regions ofTFTs 290. EachTFT 290 includes a body region 242 (e.g., an N-type semiconductor region for an N-channel transistor) including achannel region 244 and drain andsource regions source contacts conductive vias 286 that pass through apassivation layer 280 for electrical connections to drain andsource regions Data lines 282 and pixel electrodes orcontacts 284 are on an insulatingpassivation layer 280 that protects theunderlying gate lines 222 andTFTs 290.Conductive vias 286 throughpassivation layer 280 electrically connect eachdata line 282 todrains 252 ofTFTs 290 corresponding to a column of pixels and electrically connectelectrodes 284 tosources 254 ofindividual TFTs 290. - The size of pixels in a
display incorporating backplane 200 dictates the spacing ofgate lines 222 anddata lines 282. A typical pixel pitch for displays of 72 dpi (dot per inch) is on the order of about 350 μm. In contrast, the dimensions ofTFTs 290 are selected according to desired switching performance. In general, a higher ratio of TFT channel width to channel length results in a higher channel current and faster pixel switching speed. -
Backplane 200 can be fabricated using conventional techniques topattern gate lines 222 andcommon lines 224 prior to material depositions for gate dielectric and thin film semiconductor layers forTFTs 290. For example, photolithography processes can be used to mask and etch a bottom conductor layer andform gate lines 222 andcommon lines 224. However, the surface of the patternedgate lines 222 andcommon lines 224, as well as the exposed portions ofsubstrate 210 would have to be cleaned well for the deposition of a stack of device layers thereon. Further, alignment ofgate lines 222 with overlying structures can suffer when a bottom conductor/metal layer is patterned to formgate lines 222 before deposition of gate insulators and thin films that formbody regions 242 and drain andsource regions backplane 200 as illustrated inFIGS. 2A , 2B, and 2C deposits thin film layers forTFTs 290 on an unpatterned bottom conductor layer and uses a 3D template to simultaneously formgate lines 222 andTFTs 290.Passivation layer 280 can then be deposited, and structures such asdata lines 282 andpixel contacts 284, which are more tolerant of alignment errors, can be formed onpassivation layer 280 using more conventional techniques for forming conductive traces. - Details of an exemplary fabrication process for
backplane 200 are described here with reference to the perspective view ofFIGS. 2A , 2B, and 2C and the cross-sectional view ofFIGS. 3A through 3M . In the exemplary embodiment,backplane 200 is built with a-Si:H TFT materials on a polyimide web. However, other thin-film devices such as organic semiconductor devices could be similarly employed. -
FIG. 2A shows anintermediate structure 200A including an unpatterned multilayer stack formed onsubstrate 210.Substrate 210 can be any supportive insulating structure having the characteristics desired for the display to includebackplane 200. However, in an exemplary embodiment,substrate 210 is a flexible polyimide substrate having a thickness of about 1 to 5 mil. Aconductive layer 220 can be deposited onsubstrate 210 using conventional techniques such as chemical vapor deposition, sputtering, spraying, or printing. In the exemplary embodiment,conductive layer 220 is a metal such as aluminum about 50 nm to 200 nm thick and is on an adhesion layer such as a silicon nitride layer onsubstrate 210. An insulatinglayer 230, which will serve as a gate dielectric layer, is deposited onconductive layer 220. In an exemplary embodiment, insulatinglayer 230 is a silicon nitride layer about 200 nm to 400 nm thick. -
Layers TFTs 290, are thin film semiconductor layers. For example, for N-channel transistors,layer 240 can be an intrinsic hydrogenated amorphous silicon (a-Si:H) layer, andlayer 250 can be an a-Si:H layer with heavy N-type (e.g., phosphorous) doping. Alayer 260, which is deposited on thin-film semiconductor layer 250, is a conductive layer that will be used to form drain and source pads. For example,layer 260 can be a chromium layer about 50 nm to 200 nm thick. Deposition oflayers -
FIG. 2B shows anintermediate structure 200B created after a3D template 270 is imprinted using a polymer material on themultilayer stack 200A ofFIG. 2A .FIGS. 3A and 3B show cross-sectional views ofstructure 200B respectively along a cross-section that is along gate line direction and a cross-section that is along data line direction.Structure 270 can be fabricated using a roll-to-roll Self-Aligned Imprint Lithography (SAIL) process that is able to produce multilevel templates on flexible substrates. U.S. Pat. No. 6,861,365, entitled “Method and System for Forming a Semiconductor Device” describes the general SAIL process and is hereby incorporated herein by reference. The SAIL process generally includes depositing a layer of an uncured polymer or resist material and applying a stamping tool to cure and shape the layer. When the desired shape of the layer is a repetitive 3D template, the stamping tool can include a roller that can roll against a flat surface of a flexible or rigid substrate coated with resist or the surface of a coated flexible material being fed through a reel and roller system. The 3D resist can be cured or hardened. -
FIGS. 2B , 3A, and 3B show an embodiment of3D template 270 having fourlevels Level 271 is the lowest and thinnest level that results and corresponds to a thin layer of imprinted polymer that is residual on the thin film layers. Typically, the thickness of the polymer residual can be less than 100 nm. The area atlevel 271 corresponds to separations betweengate lines 222 and the pixelcommon lines 224 to be formed fromlayers Level 272 is the next higher level, about 0.5 to 2 μm, and defines areas aroundTFTs 290 and the pixel electrodes.Level 273, which is the next higher level oftemplate 270, defines the TFT channels.Level 273 can be about 0.5 μm to 2 μm higher thanlevel 272.Level 274 is the highest level ofstructure 270 and defines the TFT drain andsource regions Level 274 can be about 0.5 μm to 2 μm higher thanlevel 273. Alternative embodiments ofstructure 270 can employ additional levels. For example, the area atlevel 272 may be split into two sub-levels to separately define pixel areas and TFT isolation to create different thicknesses of the dielectric for the TFT gates and pixel storage capacitors. - An etch process using
3D template 270 generally involves thinning of 3D template to expose underlying layers and the etching the exposed layers using the remaining portions of3D template 160 as a mask. More specifically, in the embodiment ofFIG. 2B ,3D template 270 is initially thinned, for example, using an anisotropic etch process, so that portions of 3D template corresponding tolevel 271 are removed, which exposes areas oflayer 260. Using the same or a different etch chemistry, the exposed portion of layer 260 (e.g., chromium metal), semiconductor layer 250 (doped a-Si), semiconductor layer 240 (intrinsic a-Si), gate dielectric layer 230 (silicon nitride), and conductive layer 220 (aluminum) are etched away. As shown inFIG. 3C , which is a cross-sectional view along the data line direction, this initial etching step formsgate lines 222 andcommon lines 224, which are isolated fromgate lines 222.Common lines 224 can be connected together outside of the array (not shown). - An etch process is performed to
thin 3D template 270 by one step height, thereby exposing areas oflayer 260 corresponding tocommon lines 224 and portions ofgate lines 222 that between two neighboringTFTs 290. The exposedlayer 260 and underlying portions oflayers FIGS. 3D and 3E . The remaining portions oflayer 240 then form thebody regions 242 of the TFTs. - Thinning
3D template 270 again leaves regions of template over areas corresponding to the drain and sources of the TFT and exposeslayer 260 in areas corresponding to theTFT channel 244. An etch process then removes the exposed portions oflayer 260 and dopedSi 250 as shown in the cross-sectional views along the gate line and data line directions respectively inFIGS. 3F and 3G , but this etch is of a controlled duration to leavechannel regions 244. After removing the remaining portions of3D template 270, which were on drain andsource contacts TFTs 290 are above gate lines 222.FIGS. 2C , 3H, and 31 respectively show a perspective view, a cross-sectional view along the gate line direction, and a cross-sectional view along the data line direction of thestructure 200C that remains after final removal of3D template 270 from the structure ofFIGS. 3F and 3G . - According to one embodiment, an in-line test and defect repair process can be performed on
structure 200C. One common defect is a short betweengate lines 222 andcommon lines 224 caused by an imprint defect, particle contamination, or a non-uniform etching process. One such defect results in an entirely defective row in a display. It is therefore desirable to identify and remove the shorts before further processing. An in-line test can automatically probe conductance between each gate line and the common lines. An identified short 226 as shown inFIG. 31 can be removed by alaser tool 300 such as a pulsed YAG or excimer laser. - Referring now to
FIGS. 3J and 3K , which respectively show cross-sectional views along the gate line and data line directions, alayer 280 of passivation material is deposited to coverintermediate structure 200C ofFIGS. 2C , 3H, and 3I.Passivation layer 280 can be an organic material such as DOW Cyclotene, FujiFilm polyimide, and Honeywell PTS-E or an inorganic film such as oxynitride plasma deposited at a low temperature.Passivation layer 280 protects underlyingTFTs 290 from moisture contamination and mechanical damage.Passivation layer 280 also buffersdata lines 282 from capacitive coupling to gate lines 222. Electrical connection ofdata lines 282 andpixel electrodes 284 to drain andsource pads holes 285 throughpassivation layer 280. Metal or other conductive material that formsdata lines 282,pixel electrodes 284, andconductive plugs 286 as shown inFIG. 2D can be formed onpassivation layer 280 after the formation of viaholes 285. - Various techniques such as photolithography, imprint lithography, direct laser writing/ablation, ink-jetting, and screen printing may be used to form via
holes 285 and conductive traces, and in general, the technique used will depend on the required device dimension and alignment tolerance. In one embodiment, photoimageable Cyclotene, polyimide, or PTS-E may be used as the passivation material inlayer 280. Photolithography or laser writing can then be used to define vias to drain andsource pads passivation layer 280 is planarized over polymer pillars that were imprinted on drain andsource regions holes 285 throughpassivation layer 280 can be remnants of3D template 270 that are left after the etch process described above. -
FIGS. 3L and 3M show cross-sectional views respectively along the gate line and data line directions and illustrate aconductive layer 288 such as aluminum that is deposited overpassivation layer 280.Backplane 200 ofFIG. 2D can be completed by patterningconductive layer 288 and formingdata lines 282 andpixel electrodes 284 onpassivation layer 280. Since the alignment tolerance for patterning oflayer 288 is relatively large, e.g., on the order of about 10 μm, screen printing or a low resolution photolithography process are suitable for formation ofdata lines 282 andelectrodes 284 even though such processes may not be able to achieve the line width or alignment tolerances required when defining the channels of theTFTs 290. - In the embodiment of
backplane 200 ofFIG. 2D ,pixel electrodes 284 minimize overlap withgate lines 222, but ifpassivation layer 280 is sufficiently thick,pixel electrodes 284 could extend overgate lines 222 without having a capacitive coupling problem, which can significantly improve the pixel fill factor, e.g., the percentage of the area of the display covered by optically active pixel area. - Further defect repair may be performed before forming top conductive layers or after completing a display backplane to improve array performance and production yield. A common defect is a shunt defect caused by pin holes in the
gate dielectric layer 230. The defect leads to a leakage path between the bottom gate metal and source/drain metal and has been one of the major problems in producing TFT backplanes. However, inbackplane 200,passivation layer 280 can be made sufficiently thick to practically eliminate direct shunt defects that are away fromTFTs 290. As a result, the number of defects at the array level can be greatly reduced inbackplane 200, and most shunt defects are limited to the crossover area betweengate lines 222 anddata lines 282. In particular, most shunts may be due to defects in thegate dielectric 232 inTFTs 290. Improving the quality of the dielectric material is important to minimizing this problem, and as noted above with reference toFIG. 2A , forming gate dielectric 230 on a planarunpatterned layer 220 can improve the quality ofgate dielectric 230. However, a few shunts ingate dielectric layer 232 inbackplane 200 may result from defects such as pin holes ingate dielectric layer 232. - A single shunt located below a data line in some convention backplane circuits causes a failure of the entire data line and the corresponding column of pixels. However,
backplane 200 ofFIG. 2D allows for defect repair during the fabrication process to isolate defective crossovers and save the column of pixels. For example, once a shunt defect is identified during the in-line test process as described earlier, thedefective TFT 290 can be sealed by jetting a polymer to fill those viaholes 285 on the intermediate structure ofFIG. 4A or 3J. Overlying conductive traces can then be formed as described above, but no connection to thedefective TFT 290 will be created because viaholes 285 associated with the defect are filled with an insulating material. - An alternative method for isolating a defective crossover can be directly applied to
backplane 400 ofFIG. 4B .Backplane 400 contains structures that can be identical to those ofbackplane 200 ofFIG. 2D , except thatbackplane 400 hasdata lines 410 andpixel electrodes 420 that are shaped differently fromdata lines backplane 200. In particular, the shape ofdata lines 410 providesnecks 415 betweenrespective drains 252 and continuous portions of data lines 410. When a crossover defect is detected in aparticular TFT 290, theneck 415 that leads to thedrain 252 of thatTFT 290 can be cut with a laser to isolate the defect from the rest of thecontinuous data line 410. - The above repair methods minimize the number of defective display rows and columns Redundant TFTs may be designed for each pixel for further reduction of the effects of single-pixel defects.
- Backplanes described above have drains and
sources gate lines 222 and drain/source regions -
FIG. 5 is a circuit diagram of a portion of adisplay 500 that can incorporate a circuit such asbackplane 200 ofFIG. 2D orbackplane 400 ofFIG. 4B . As illustrated inFIG. 5 , eachTFT 290 has a gate coupled to thegate line 222 for the row containing theTFT 290, adrain 252 coupled to a data line for thecolumn containing TFT 290, and asource 254 coupled to apixel 510. Eachpixel 510 can use any desired structure that produces a suitable optical effect that varies with a voltage thatTFT 290 applies topixel 510. For example, in a reflective LCD display,pixel 510 would typically include: areflective back electrode 284; a transparent front electrode, e.g., an Indium Tin Oxide electrode; at least one polarizing filter, and a liquid crystal material between the electrodes. A color filter, e.g., a filter that transmits red, green, or blue light can be included in eachpixel 510 of a color display. As is well known in the art, LCD displays use the birefringence of the liquid crystal material to alter the polarization of traversing light and change the amount light of transmitted through or reflected from the pixel. For example, the thickness of the liquid crystal material (and the orientation of the polarizing filter or filters) can be selected so that when no voltage is applied, eachpixel 510 has highest reflectivity. More specifically, light entering through the front polarizing filter is linearly polarized, and the liquid crystal material rotates that polarization so that the light reflected back through the polarizing filter passes through with little or no absorption. WhenTFT 290 applies a voltage from the attacheddata line 282 to thepixel electrode 284, the alignment or structure of the liquid crystal material changes, and the effect of the liquid crystal material on the polarization of traversing light changes so that more of the light is absorbed by the polarizing filter or filters. Near total absorption can be achieved when the liquid crystal material changes the polarization of the light so that the reflected light has a polarization perpendicular to the polarization axis at the front polarizing filter. -
Pixel 510 can alternatively employ other technologies that change the optical properties as desired in a display. For example,pixel 510 can be an electrophoretic pixel. In an electrophoretic pixel, the electric field created by a voltage thatTFT 290 applies to an electrode of the electrophoretic pixel moves an electronic ink (e.g., dark colored particles) toward or away from a light color reflective surface or particles. As a result, the pixel can appear light or dark depending on whether reflective surface ofpixel 510 is dominated by light or dark colored particles. - The structure and processing techniques described above have been illustrated using the example of a backplane containing a TFT array. Embodiments of the invention can be integrated in other types of devices or contain more complex circuitry in a backplane. For example, a backplane for an LED display could be fabricated using above described techniques.
FIG. 6 is a circuit diagram for an embodiment of anLED display 600.LED display 600 includesgate lines 222 anddata lines 282 that cross each other and can be fabricated using the processes described above. Coupled togate lines 222 anddata lines 282 areselect transistors 612, which can be TFTs fabricated in the same manner asTFTs 290 described above. The circuitry for each pixel indisplay 600 further includes astorage capacitor 614, adrive transistor 616, and anLED 618. In the circuitry for a single pixel,select transistor 612 is betweendata line 282 andstorage capacitor 612, so that when thegate line 222 attached to theselect transistor 612 is asserted,select transistor 612charges storage capacitor 614 to the voltage ondata line 282.Storage capacitor 614 is coupled to the gate ofdrive transistor 616, which is connected in series withLED 618 between a supply voltage and ground. Accordingly, the voltage onstorage capacitor 614 controls the current flowing throughdrive transistor 616 andLED 618, and therefore controls the intensity of light that LED 618 emits. -
Display 600 can be fabricated using a thin film stack and a 3D template as described above to formgate lines 222 and arrays oftransistors FIG. 7 shows a layout for multiple layers forming circuitry in apixel 700 forLED display 600. In the embodiment ofFIG. 7 , agate line 222, thelower plate 722 ofcapacitor 614, aground line 724, and alower plate 726 for the gate ofTFT 616 are formed from bottom conductive layer during a SAIL process (e.g., steps 120 to 140 ofFIG. 1 .) The SAIL process also formsTFTs gate line 222 controllingTFT 612. Anupper plate 762 ofcapacitor 614 can be formed during the SAIL process from the same metal layer that forms drain and source pads forTFTs transistors data lines 282 with a conductive via to the drain ofTFT 612, abridge 782 electrically connecting the source ofTFT 612 toupper plate 762. Abridge 786 connectsupper plate 762 togate 726 ofTFT 616 through vias. Abridge 788 connects aground line 724 to the source ofTFT 616. An LED overlyingpixel structure 700 connects to the drain ofTFT 616. In an exemplary embodiment, the upper layer is a metal/PIN/metal stack that could be patterned to fabricatedata lines 282 andLEDs 618. - Although the invention has been described with reference to particular embodiments, the description is only an example of the invention's application and should not be taken as a limitation. For example, although the specific embodiments of the invention described above are employed in displays similar fabrication techniques could be employed in other devices such as sensor arrays that may employ crossing circuit features over a large area. Various other adaptations and combinations of features of the embodiments disclosed are within the scope of the invention as defined by the following claims.
Claims (10)
1-12. (canceled)
13. A system comprising:
a self-aligned structure including a plurality of gate lines and a plurality of rows of thin-film transistors that are respectively gated by the gate lines;
a passivation layer overlying the self-aligned thin-film structure; and
conductive traces that are on the passivation layer and subject to alignment variations relative to the self-aligned structure, wherein the conductive traces include a plurality of data lines that cross over the gate lines, each of the data lines being coupled to a column of the thin-film transistors.
14. The system of claim 13 , further comprising an array of pixels, wherein the conductive traces further comprise pixel electrodes that are coupled to respective pixels.
15. The system of claim 14 , wherein the pixels comprise LCD pixels.
16. The system of claim 14 , wherein the pixels comprise electrophoretic pixels.
17. The system of claim 14 , wherein each of the data lines includes a continuous portion and a plurality of necks, the necks being between the continuous portion of the data line and the thin-film transistors in the column coupled to the data line.
18. The system of claim 17 , wherein one of the necks is cut so that a corresponding one of the thin film transistors is isolated from the continuous portion of the data line.
19. The system of claim 13 , wherein the self-aligned structure further comprises:
a plurality of drive transistors; and
a plurality of capacitors; the capacitors having plates that extend to form respective gates of the drive transistors.
20. The system of claim 19 , further comprising an array of light emitting diodes overlying the passivation layer, wherein each of the light emitting diodes is connected in series with a corresponding one of the drive transistors.
21. The system of claim 13 , wherein the system forms a backplane of a flat panel display.
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US13787408P | 2008-08-01 | 2008-08-01 | |
US12/243,073 US8021935B2 (en) | 2008-10-01 | 2008-10-01 | Thin film device fabrication process using 3D template |
US13/219,571 US20110309365A1 (en) | 2008-08-01 | 2011-08-26 | Thin film transistor backplane |
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Also Published As
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US8021935B2 (en) | 2011-09-20 |
US20100078640A1 (en) | 2010-04-01 |
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