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Publication numberUS20110025898 A1
Publication typeApplication
Application numberUS 12/674,393
PCT numberPCT/EP2008/061261
Publication date3 Feb 2011
Filing date27 Aug 2008
Priority date28 Aug 2007
Also published asCN101796810A, CN101796810B, EP2186318A1, EP2186318B1, US9768742, US20150207470, WO2009027449A1
Publication number12674393, 674393, PCT/2008/61261, PCT/EP/2008/061261, PCT/EP/2008/61261, PCT/EP/8/061261, PCT/EP/8/61261, PCT/EP2008/061261, PCT/EP2008/61261, PCT/EP2008061261, PCT/EP200861261, PCT/EP8/061261, PCT/EP8/61261, PCT/EP8061261, PCT/EP861261, US 2011/0025898 A1, US 2011/025898 A1, US 20110025898 A1, US 20110025898A1, US 2011025898 A1, US 2011025898A1, US-A1-20110025898, US-A1-2011025898, US2011/0025898A1, US2011/025898A1, US20110025898 A1, US20110025898A1, US2011025898 A1, US2011025898A1
InventorsYang Ni
Original AssigneeYang Ni
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Cmos active pixel with very high functional dynamics
US 20110025898 A1
Abstract
The invention relates to a structure of an active pixel of the CMOS type (1) that comprises: at least one photodiode (10), characterised in that it comprises means for reading any bias voltage in the evolution phase of the photodiode (10) upon exposure.
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Claims(17)
1. A structure of an active pixel of the CMOS type (1) comprising:
at least one photodiode (10),
means for reading a voltage with any polarity in the time-dependent variation phase of the photodiode (10) during exposure, including a buffer amplifier (30) including a read-out transistor (T2) and a charging transistor (T3),
characterized in that it further includes a capacitive coupling capacitor (50) mounted in series between the photodiode (10) and the buffer amplifier (30).
2. The structure of an active pixel of the CMOS type (1) according to claim 1, characterized in that the read-out transistor (T2) has negative threshold voltage.
3. The structure of an active pixel of the CMOS type (1) according to claim 1, characterized in that the charging transistor (T3) is located inside the structure of the pixel (1).
4. The structure of an active pixel of the CMOS type (1) according to claim 1, characterized in that the charging transistor (T3) is located outside the structure of the pixel (1).
5. The structure of an active pixel of the CMOS type (1) according to any of claims 1 to 2, characterized in that a threshold voltage of the read-out transistor (T2) is less than a voltage, the most negative voltage, capable of passing through the photodiode (10).
6. The structure of an active pixel of the CMOS type (1) according to claim 1, characterized in that it includes a means with which an output signal from the buffer amplifier (30) may be sent onto a communications bus (40).
7. The structure of an active pixel of the CMOS type (1) according to claim 6, characterized in that the means for sending the output signal of the buffer amplifier (30) onto a communications bus (40) is a transistor (T4) connected to a selection signal (SEL).
8. The structure of an active pixel of the CMOS type (1) according to any of claims 1 to 7, characterized in that it includes means for setting up a voltage on the coupling capacitor (50) within the pixel (1).
9. The structure of an active pixel of the CMOS type (1) according to claim 8, characterized in that the setting-up means are resistors (60) mounted between the buffer amplifier (30) and a positive voltage source (70).
10. The structure of an active pixel of the CMOS type (1) according to claim 9, characterized in that the resistor (60) consists of an NMOS transistor (TR) connected as a diode.
11. The structure of an active pixel of the CMOS type (1) according to claim 9, characterized in that the drain and the gate of the transistor (TR) are connected to two different power supply sources (70, 72).
12. The structure of an active pixel of the CMOS type (1) according to any of claims 8 to 11, characterized in that the setting-up means are an injection of a positive charge under ultraviolet radiation into the plate (51) of the coupling capacitor (50) connected to a buffer amplifier (30).
13. The structure of an active pixel of the CMOS type (1) according to any of claims 8 to 12, characterized in that the setting-up means are an injection of a positive charge by the tunnel effect into the plate (51) of the coupling capacitor (50) connected to the buffer amplifier (30).
14. The structure of an active pixel of the CMOS type (1) according to claim 13, characterized in that the photodiode (10) is used like one of the plates (51, 53) of the coupling capacitor (50).
15. The structure of an active pixel of the CMOS type (1) according to any of claims 1 to 14, characterized in that it includes a reset transistor (T1) capable of being disabled by application of a negative voltage.
16. The structure of an active pixel of the CMOS type (1) according to any of claims 1 to 15, characterized in that the transistors (T1, T2, T3, T4, TR) are of the same type, either NMOS or PMOS, and in that the read-out transistor (T2) is a depleted transistor.
17. A method for operating a pixel (1) according to any of claims 1 to 16, characterized by the fact that it comprises the steps of:
1) resetting a photodiode (10), before taking shots, to an initial voltage V, with a signal RAZ enabling the reset transistor (T1)
2) disabling the reset transistor (T1) and letting the photodiode (10) vary under illumination during the exposure;
3) performing a first read-out at the end of the exposure with a selection signal SEL, and
4) performing a second read-out during or suddenly after re-enabling the reset transistor (T1).
Description
  • [0001]
    The invention relates to CMOS (Complementary Metal Oxide Semiconductor) integration technology which applies a family of electronic components with low electric consumption.
  • [0002]
    The invention in particular relates to CMOS pixels.
  • [0003]
    With CMOS integration technology it is possible to make chips for monolithic cameras with good resolution and a reasonable image quality. These monolithic cameras are mainly intended for mobile devices such as mobile telephones, personal digital assistants (PDAs), or portable computers. The images taken by these cameras are essentially used for viewing on a screen or on Internet.
  • [0004]
    The very economical aspect of this type of camera gives rise to an always increasing interest for applications relating to artificial viewing modes, such as the smart car airbag, side and longitudinal inspection of a car on the motorway, video monitoring of sensitive areas etc. . . . It is easily conceivable that for this type of applications, the taking of shots is generally accomplished under not very ideal illumination conditions, widely exceeding the dynamic range given to this kind of low cost CMOS sensors, thereby preventing them from providing an acceptable response in terms of functional dynamics.
  • [0005]
    One of the major difficulties during the use of such a camera lies in the extent of the variation of the illumination level for a same scene. This variation may easily exceed 120 dB between strongly illuminated areas and poorly illuminated areas. A conventional CCD/CMOS camera having a linear response may adapt to this with difficulty, and generally produces totally or partly saturated images, causing loss of relevant information and leading to an unstable viewing system.
  • [0006]
    A second difficulty lies in the extent and rate of variation of the light in a dynamic scene. The automatic exposure control system produced by a conventional camera cannot suitably respond to this and therefore produces total or partial saturations.
  • [0007]
    These saturation phenomena are extremely detrimental to proper operation of a viewing system.
  • [0008]
    Many methods propose a solution to this problem by generating active pixel structures having widened functional dynamics by means of a non-linear photoelectric response having a drop in sensitivity in the case of significant illumination.
  • [0009]
    Document EP1354360 describes an active pixel structure with a logarithmic response based on utilizing a photodiode in the photovoltaic regime.
  • [0010]
    In the field of standard CMOS technology, a photodiode is generally formed with a PN junction with N diffusion into a substrate of type P. In the photovoltaic operating mode, this photodiode generates a negative voltage in an open circuit, the absolute value of which is proportional to the logarithm of the illumination level of the photodiode. With a switch, it is possible to generate a short circuit in this photodiode in order to simulate the darkness condition in the presence of normal illumination. By reading the difference between the voltage generated by the photodiode in an open circuit and that in a short circuit, it is possible to suppress the additive offset noises in the read-out chain and to thereby obtain a clean image.
  • [0011]
    Prototype circuits implementing the structure of the pixel described in document EP1354360 have provided very high functional dynamics and satisfactory image quality. Nevertheless, this pixel structure still suffers from a certain number of deficiencies.
  • [0012]
    Indeed, first of all, it lacks physical compactness, this lack being the result of the simultaneous mandatory presence of NMOS and PMOS transistors within a same pixel, which requires an insulation case causing the loss of a large portion of useful surface area. Now, this loss of surface area increases the size of the pixel, reduces the size of the photodiode and therefore also reduces the photoelectric performance.
  • [0013]
    Next, within this structure, the photodiode only operates in the photovoltaic mode. Now, because of strong logarithmic compression, this operating mode generates an output signal of very low amplitude, thereby limiting the signal-to-noise ratio which may be obtained in the case of diurnal illumination.
  • [0014]
    Finally, the short-circuit switching transistor has some residual conductivity during its disabling. This phenomenon becomes critical in a creation of submicron CMOS technology.
  • [0015]
    Further, if document EP1354360 describes an active pixel structure utilizing the logarithmic area, this is not the same for the majority of the existing active pixels, which on the contrary utilize the linear area of the variation of the voltage on a photodiode after its reset. The reason for this is that the operation of a photodiode in the mixed or logarithmic portion is supposed to pose photoelectric problems within an array, therefore, a photodiode is generally prevented from entering these areas.
  • [0016]
    Now, complete utilization of the variation range generates a signal of strong amplitude by means of the linear area and extended functional dynamics by means of the mixed and logarithmic areas. Indeed, in the linear area, the relative noise of the image signal is strongly reduced so that the obtained image is of good quality; however, the dynamic range remains small. The mixed and logarithmic areas on the contrary strongly compress the amplitude of the image signal so as to almost eliminate completely the saturation of said signal, but the low amplitude and the negative polarity of the image signal make it difficult to read. It would therefore be interesting to combine the three areas so as to obtain at the same time good image quality and extended dynamic range.
  • [0017]
    An object of the invention is to provide at least one pixel structure with very high functional dynamics, which not only has a large physical compactness but also allows significant improvement of the signal-to-noise ratio.
  • [0018]
    For this purpose, according to the invention, an active pixel structure of the CMOS type is provided, comprising at least one photodiode, characterized in that it includes means for reading out a voltage of any polarity in the time-dependent variation phase of the photodiode during exposure. This gives said pixel structure high functional dynamics allowing an acknowledged improvement of the signal-to-noise ratio.
  • [0019]
    Advantageously but optionally, the structure includes at least one of the following features:
      • the means for reading out a voltage of any polarity comprise a read-out transistor,
      • the structure includes a buffer amplifier including the read-out transistor and a charging transistor,
      • the read-out transistor has a negative threshold voltage,
      • the charging transistor is located inside the structure of the pixel,
      • the charging transistor is located outside the structure of the pixel,
      • a threshold voltage of the read-out transistor is less than a voltage, the most negative voltage crossing the photodiode,
      • the structure includes a means with which an output signal from the buffer amplifier may be sent onto a communications bus,
      • the means for sending the output signal from the buffer amplifier onto a communications bus is a fourth transistor connected on a selection signal,
      • the structure further includes a capacitive coupling capacitor mounted in series between the photodiode and the buffer amplifier,
      • the structure includes means for setting up a voltage on the coupling capacitor within the pixel,
      • the setting-up means are a resistor mounted between the buffer amplifier and a positive
      • the resistor consists of an NMOS transistor connected as a diode,
      • the drain and the gate of said NMOS transistor are connected to two different power supply sources,
      • the setting-up means are injection of a positive charge under ultraviolet radiation into the plate of the coupling capacitor connected to the buffer amplifier,
      • the setting-up means are injection of a positive charge via the tunnel effect into the plate of the coupling capacitor connected to the buffer amplifier,
      • the photodiode is used as one of the plates of the coupling capacitor,
      • the structure includes an reset transistor capable of being disabled by application of a negative voltage, and
      • the aforementioned transistors are of the same type, either NMOS or PMOS, and the read-out transistor is of the depleted NMOS type.
  • [0038]
    According to the invention, a method for operating a pixel according to the invention is also provided, characterized by the fact that it comprises the steps consisting of: resetting a photodiode, before taking shots, to an initial voltage V by means of a zero-resetting signal (RAZ) which enables the reset transistor; disabling the reset transistor and letting the photodiode vary under an illumination during the exposure; performing a first read-out at the end of the exposure by means of a selection signal SEL; and performing a second read-out during or suddenly after re-enabling of the reset transistor.
  • [0039]
    Advantageously, but optionally, the method for operating a pixel utilizes the following areas of the variation of the voltage on the photodiode after its reset:
      • the linear area,
      • the logarithmic area,
      • the mixed area.
  • [0043]
    Other features, objects and advantages of the invention will further become apparent from the description which follows, which is purely illustrative and non-limiting, and should be read with reference to the appended drawings, wherein:
  • [0044]
    FIG. 1 a is a view of a photoreceiver with a photodiode in a photovoltaic mode according to the prior art,
  • [0045]
    FIG. 1 b is a view of a structure of a pixel provided with a photoreceiver according to the prior art,
  • [0046]
    FIG. 2 is a curve illustrating the variation of the voltage on a photodiode after its reset,
  • [0047]
    FIGS. 3 a and 3 b are two views of a pixel structure according to a first embodiment of the invention,
  • [0048]
    FIGS. 4 a and 4 b are two time diagrams showing the operation of a pixel according to the first and a second embodiment of the invention, respectively,
  • [0049]
    FIG. 5 is a view of a pixel structure according to a second embodiment of the invention,
  • [0050]
    FIGS. 6 a, 6 b, 6 c, 6 d and 6 e are five views of a pixel structure according to five alternatives of the second embodiment of the invention,
  • [0051]
    FIGS. 7 a and 7 b are two views of a pixel structure according to two other alternatives of the second embodiment of the invention,
  • [0052]
    FIG. 8 a is a view of a pixel structure according to another alternative of the second embodiment of the invention,
  • [0053]
    FIG. 8 b is a partial view of a pixel structure according to another alternative of the second embodiment of the invention,
  • [0054]
    FIG. 9 is a view of a typical transistor, and
  • [0055]
    FIG. 10 is a view of an array configuration of a pixel structure.
  • [0056]
    With reference to FIGS. 3 a-4 a, we shall now describe a first embodiment of the invention.
  • [0057]
    According to this first embodiment of the invention, a pixel structure 1 includes:
      • a photodiode 10 having a junction capacitance CPD, made by N type diffusion into a substrate of type P,
      • transistors 20, including at least one reset transistor T1 of the NMOS (N Metal Oxide Semiconductor) type,
  • [0060]
    means for reading out a voltage of any polarity in the photodiode 10 when the latter is illuminated.
  • [0061]
    The depleted N type transistor has a negative threshold voltage TS—the threshold voltage TS being the voltage at one of the poles of the transistor called the “gate” G, the two other poles being the “source” S and the “drain” D—which allows it to be kept “conducting” when a voltage greater than TS, and in particular a negative voltage belonging to the interval [TS; 0], is applied between the gate G and the source S. When the photodiode 10 varies in a logarithmic area, a negative voltage likely to be present is relatively low: it does not exceed 0.7 V in absolute value. Therefore a threshold voltage TS of the order of −1 V allows the voltage of the photodiode 10 to be read out over the whole range of its variation over time and it may be translated into a purely positive voltage by means of such a depleted transistor, which may be utilized by conventional read-out circuits.
  • [0062]
    The photodiode 10 is used with reverse bias. Before taking shots, a generator, either external or internal to the pixel produces a reverse initial voltage Vinit powering the reset transistor T1, which sets up this initial reverse voltage Vinit in the photodiode 10. This operation is called “initializing or resetting to zero (RAZ) the photodiode”.
  • [0063]
    In an alternative embodiment, the initial voltage Vinit, is programmable. Thus, it allows determination of the range of use of the photodiode 10, which either starts in the linear area, or in the mixed area or in the logarithmic area (cf. FIG. 2), depending on the luminosity to which it is subject and on the conditions of its use which follows this reset.
  • [0064]
    Next, during a so-called exposure period Texp, the transistor T1 is disabled, so that a photoelectric current Iλ induced within the photodiode 10 then illuminated, gradually discharges the voltage into the photodiode 10. A variation between the initial voltage in the photodiode 10 and a voltage obtained at the end of the exposure forms the output signal of the pixel 1. The voltage curve of the photodiode 10 is visible in FIG. 2.
  • [0065]
    The time-dependent variation range of a photodiode is divided into two main areas, defined as follows.
  • [0066]
    If the light intensity is relatively low, at the end of the exposure period, the photodiode remains under reverse bias. That is to say that the voltage on the photodiode remains positive:
  • [0000]
    V PD = V init - I λ * T exp C PD > 0
  • [0000]
    wherein CPD is the junction capacitance of the photodiode and Texp is the exposure time. Therefore, it is stated in this case that the photodiode is operating in the linear area.
  • [0067]
    If the light on the contrary is very intense, the photodiode will be completely discharged and the voltage on the photodiode then becomes negative:
  • [0000]
    V PD = - kT q ln ( I λ I S + 1 ) < 0
  • [0000]
    wherein k is the Boltzmann constant, q is the elementary charge, T is the absolute operating temperature of the photodiode and IS represents a reverse current also called the saturation current of the junction of the photodiode, observed when a diode is reverse-biased in the total absence of light. The voltage on the photodiode becomes proportional to the logarithm of the light intensity. It is stated in this case that the photodiode operates in the logarithmic area.
  • [0068]
    After the exposure, the voltage VPD of the photodiode 10 has therefore become either
  • [0000]
    V PD = V init - I λ * T exp C PD > 0
  • [0000]
    if the photodiode 10 remains in the linear area, or
  • [0000]
    V PD = - kT q ln ( I λ I S + 1 ) < 0 if
  • [0000]
    the photodiode enters the logarithmic area.
  • [0069]
    A MOS follower 30—also called a buffer amplifier—is connected between the reset transistor T1 and the photodiode 10. It includes means for reading out a voltage of any polarity in the photodiode 10. These read-out means comprise a read-out depleted NMOS transistor T2. The follower 30 also includes a transistor T3 having a charging function included in the pixel 1. Alternatively, the transistor 13 is positioned outside the pixel 1. The configuration which places the charge T3 in the pixel 1 is however more stable than the one which places it outside the pixel 1.
  • [0070]
    The read-out depleted NMOS transistor T2 is used here, over the whole range where it is conducting, in order to translate the electric level of the voltage read on the photodiode 10 so as to obtain a voltage forming an output signal, which may be utilized by the circuit using this output signal.
  • [0071]
    In order to transmit the output signal of the follower 30 on a communications bus 40, the follower 30 is selectively connected onto the bus 40 with a fourth transistor T4, called a selection transistor. The latter may be enabled by a selection signal SEL, arriving on the gate of the transistor T4. This selection mechanism allows access to a determined pixel in a pixel array. At the end of the exposure, a first read-out L1 is achieved by means of this SEL signal. This read-out gives the final voltage in the photodiode 10 plus an offset component Voffset of the translation, provided by the voltage follower 30.
  • [0072]
    At the end of the exposure period, the reset transistor T1 is re-enabled. A second read-out L2 is then made during or immediately after the end of the re-enabling of the reset transistor T1. This read-out L2 gives the initial voltage in the photodiode 10 added to the offset component Voffset of the voltage follower 30.
  • [0073]
    A subtraction between the values of both of these read-outs gives an image signal free of the offset of the voltage follower 30 within the pixel 1. FIG. 4 a gives a time diagram of the operation of the pixel 1.
  • [0074]
    In the case of this embodiment, the pixel structure 1 only uses a single type of transistor 20. This suppresses the need for an insulation case, required upon the simultaneous presence of NMOS and PMOS transistors within a same pixel 1, and provides a significant gain in space within the pixel 1. By saving a useful surface area, it is possible not to reduce the photodiode 10 and therefore to gain in photoelectric performance.
  • [0075]
    Another object of the invention is to provide at least one pixel structure which may utilize the whole range of variation of a photodiode, which means the possibility of utilizing in addition to the linear area, the mixed and logarithmic portions for which the voltage on the photodiode becomes negative.
  • [0076]
    Now, a compact pixel using a single type of transistors can normally only read a positive voltage of the illuminated photodiode.
  • [0077]
    Another object of the invention is therefore to provide at least one pixel structure enabling by using a single type of transistor the utilization or all the variation areas of the photodiode.
  • [0078]
    With reference to FIGS. 4 b-8 b, we shall now describe a second embodiment of the invention.
  • [0079]
    According to this second particular embodiment of the invention, a pixel structure 1 includes:
      • a photodiode 10 having a junction capacitor CPD, made by N diffusion into a substrate of type P,
      • transistors 20, including at least one reset transistor T1 of the NMOS type,
      • means for reading a voltage of any polarity in the illuminated photodiode 10,
      • a capacitive coupling capacitor 50.
  • [0084]
    This second pixel structure 1 proposes the utilization of the complete range of the variation of a photodiode 10 without using any depleted NMOS transistor for T2.
  • [0085]
    The operation of the pixel 1 is identical with that of the first structure: the photodiode 10 is reset to a reference voltage by enabling the transistor T1, and then when the transistor T1 is disabled, the photodiode 10 is discharged during the exposure period, at the end of which two read-outs of the voltage of the photodiode 10 are performed, one before the re-enabling of the transistor T1 and the other one after or during the re-enabling of the transistor T1. A subtraction between the values of these two read-outs gives a clean image signal since it is free of the offset of the voltage follower 30 within the pixel 1.
  • [0086]
    The difference relatively to the first pixel structure 1 lies in the fact that the cathode of the photodiode 10 is coupled, not with a read-out depleted NMOS transistor T2, but with a normal read-out NMOS type transistor T2 with a positive threshold voltage TS, by means of a capacitive coupling capacitor 50. The voltage at the input of the read-out transistor T2 is thus the result of the sum between the voltage of the photodiode 10 and the voltage of the capacitor 50 mounted in series. It is possible, depending on the amount and on the polarity of the charges within the capacitor 50, to translate the voltage of the photodiode 10 into a range which may be handled by the read-out transistor T2. Setting up a suitable amount of charges within the capacitor 50 allows the read-out transistor T2 to read out the voltage of the photodiode 10 over the whole range of its variation, so that the thereby obtained voltage is always greater than the threshold voltage TS of the read-out NMOS transistor T2.
  • [0087]
    Different methods are proposed for setting up a suitable voltage on the coupling capacitor 50 within a pixel 1.
  • [0088]
    A first method illustrated in FIGS. 6 a-6 e consists of connecting the input (gate) of the read-out transistor T2 to a positive voltage with a value greater than the threshold voltage TS of the read-out transistor T2 through a resistor 60 consisting of an NMOS transistor TR and connected to a positive voltage source 70. The resistor 60 is of a determined value R such that a time constant RC, wherein C is the capacitance of the coupling capacitor 50, is, for example, ten times greater than the time interval existing between two read-outs L1, L2 at the end of the exposure. In this way, there is practically no loss of charge on the capacitor 50 between the two read-outs and the image signal is then reliably retransmitted to the input of the read-out transistor T2.
  • [0089]
    Alternatively, as illustrated in FIG. 6 e, the transistor TR is powered at its gate by a voltage source 72 while its drain is connected to the voltage source 70. Both voltage sources 70 and 72 may be of the same voltage or of different voltages.
  • [0090]
    Within the scope of this first method, the first read-out measures the voltage at the output of the follower 30, this voltage being substantially equal to VDD−Vth wherein VDD is the power supply voltage 70 and Vth, is the threshold voltage of the transistor TR. The output of the follower 30 is expressed by: (VDD−Vth)−Voffset. The value of this read-out is subsequently stored in a memory, either an analog or digital memory, which may either be found on a chip including pixels or outside the latter.
  • [0091]
    The second read-out is accomplished in the same way as for the first embodiment of the invention: by enabling the RAZ signal. When the latter is enabled for the second time, the voltage on the photodiode 10 is again reset to Vinit. This causes a change in voltage on the photodiode 10 which is either equal to
  • [0000]
    Δ V PD = I λ * T exp C PD
  • [0000]
    if the photodiode 10 remains in the linear area or to
  • [0000]
    Δ V PD = V init + kT q ln ( I λ I S + 1 )
  • [0000]
    if the photodiode 10 enters the logarithmic area. This positive change in the voltage of the photodiode 10 also generates a positive change at the input of the follower 30 through the capacitor 50, which positive change momentarily blocks the transistor 60. The value of the change at the input of the voltage follower 30 is equal to
  • [0000]
    Δ V PD * C C + C t
  • [0000]
    wherein CT represents the equivalent parasitic capacitance at the input of the follower 30 and C is the capacitance of the capacitor 50.
  • [0092]
    The voltage change at the output of the follower 30 after re-enabling of the reset transistor T1 may be written in the following way:
  • [0000]
    ( V DD - V th ) - V off set + η * Δ V PD * C C + C t
  • [0000]
    wherein η represents the gain of the follower 30. A read-out of this value is performed, but this value is subtracted from the value of the first read-out: (VDD−Vth)−Voffset. In this way, an image signal is obtained:
  • [0000]
    η * Δ V PD C C + C t
  • [0000]
    which is linear with the image signal on the photodiode 10; in other words, the variation between both signals is preserved.
  • [0093]
    Alternatively, the resistor 60 is made in thin layer(s) after forming the integrated transistors 20.
  • [0094]
    A second method illustrated in FIGS. 7 a and 7 b consists of using point-like conductivity within an electric insulator. This point-like conductivity may come from different physical phenomena:
  • [0095]
    1. ionizing radiation
  • [0096]
    2. a tunnel effect of cold electrons,
  • [0097]
    3. the effect of hot electrons.
  • [0098]
    It is possible in this case to add a charge injection device to the capacitor 50 which sets up in a controlled (implicit or explicit) way a suitable amount of charge within this capacitor 50. This charge injection may be accomplished in two ways:
      • 1. an offset voltage set up on the coupling capacitor 50 by means of an injection of a positive charge under ultraviolet radiation into its plate 51 connected to the voltage follower 30 (FIG. 7 a),
      • 2. an overvoltage applied to the coupling capacitor 50 by means of an injection of a positive charge by a tunnel effect in its plate 51 connected to voltage follower 30 of the normal NMOS type (FIG. 7 b).
  • [0101]
    As shown in FIG. 8 a, it is possible to reduce the darkness current of the photodiode 10 by using its cathode 11 like one of the plates 51, 53 of the coupling capacitor 50. For this, the N diffusion of the source S of the transistor T1 is merged with the N diffusion of the photodiode 10. This physical arrangement suppresses the need of ohmic contact on the photodiode 10, so as to prevent the photodiode 10 from potential physical damages related to the making of the contacts, and reduce the reverse current TS which flows through it.
  • [0102]
    Alternatively, the capacitor 50 may be made with a transistor 20, for which the drain D or the source S or both coincide with the N diffusion of the photodiode 10 (see FIG. 8 b).
  • [0103]
    In the case of both particular embodiments of the invention, the whole range of the variation of the photodiode 10 is utilized.
  • [0104]
    When the photodiode 10 varies in the logarithmic area, the negative voltage of the photodiode 10 may cause involuntary conduction of the reset transistor T1, causing fixed or variable noises on the acquired image and thereby strongly reducing the quality of the image. To overcome this flaw, a negative voltage is applied to the gate G of the transistor T1 during the exposure period. This negative voltage suppresses the parasitic conduction of transistor T1 so as to disable it. It may be provided by an external power supply source or by a generator internal to the CMOS sensor comprising the pixel 1.
  • [0105]
    An incorporation of the pixel of the invention in an array configuration of two dimensions with (m+1) lines and (n+1) columns is illustrated in FIG. 10. This figure illustrates in a non-exclusive way a particular embodiment compliant with the description of the pixel structure 1 of the invention, from which other designs may easily be inferred by one skilled in the art.
  • [0106]
    The operation of this configuration is the following: a line of pixels is selected by applying an address Yi to an addressing circuit Y. An output of pixels of the line Yi is connected onto a column read-out bus COL. The output of this line is sampled and stored in an analog memory MA1 by enabling the signal L1. A signal RAZ_ G is then enabled, also causing the enabling for resetting to zero the pixels of the selected line Yi. The output of this line is sampled in a second analog memory MA2 by the signal L2. Once this line access phase is completed, an address X is applied to an addressing circuit X. The contents of the analog memories MA1 and MA2 are directed towards a differential amplifier via the busses OB1 and OB2. This differential amplifier produces a difference which allows suppression of the offset errors in the read-out.
  • [0107]
    Of course the present invention is not limited to the particular embodiments which have just been described, but extends to all alternatives which comply with its spirit.
  • [0108]
    Alternatively, in a non-limiting and non-exclusive way, the transistors T1, T2, T3, T4 and TR are of the PMOS type.
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Classifications
U.S. Classification348/308, 348/E05.091
International ClassificationH04N5/335
Cooperative ClassificationH04N3/155, H04N5/35509, H03F3/082
European ClassificationH04N3/15E
Legal Events
DateCodeEventDescription
11 May 2010ASAssignment
Owner name: NEW IMAGING TECHNOLOGIES, FRANCE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NI, YANG;REEL/FRAME:024368/0041
Effective date: 20100324