US20100167471A1 - Reducing warpage for fan-out wafer level packaging - Google Patents
Reducing warpage for fan-out wafer level packaging Download PDFInfo
- Publication number
- US20100167471A1 US20100167471A1 US12/495,734 US49573409A US2010167471A1 US 20100167471 A1 US20100167471 A1 US 20100167471A1 US 49573409 A US49573409 A US 49573409A US 2010167471 A1 US2010167471 A1 US 2010167471A1
- Authority
- US
- United States
- Prior art keywords
- integrated circuit
- layer
- encapsulant
- forming
- bond pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1433—Application-specific integrated circuit [ASIC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Definitions
- This description generally relates to the field of chip packaging, and more particularly to fan-out wafer level packaging.
- ICs integrated circuits
- the redistribution process converts peripheral wire bond pads on an IC to an area array of solder bumps via a redistribution layer.
- the resulting fan-out wafer level packaging may have a larger solder bump bonding area and may be more easily integrated into electronic devices and larger chip packages.
- conventional fan-out wafer level packaging is illustrated.
- a backside of an IC 2 is first encapsulated in a molding compound 1 .
- a plurality of dielectric layers 4 and redistribution layers 3 are then deposited on a front side of the IC 2 to form electrical connections between wire bond pads 7 on the IC 2 and redistributed solder bump bond pads 5 .
- solder bumps 6 are formed at the redistributed bond pad locations 5 , and the fan-out wafer level packaging is ready to be soldered to a printed circuit board.
- FIG. 2 illustrates the encapsulation process as applied to a plurality of ICs 2 arranged on a surface, such as a tape 8 on a carrier 9 .
- the mold compound 1 is dispensed centrally on the tape 8 at a thickness sufficient to completely cover all exposed surfaces of each IC 2 .
- the ICs 2 are placed in a mold chase 10 that is configured to compress the molding compound 1 down and around all of the ICs 2 . A large amount of molding compound 1 is required to ensure that all side surfaces and the backside of each IC 2 is completely covered.
- a protective film 11 is arranged over the molding compound 1 and across exterior edges 12 , 13 of the mold chase.
- the protective film 11 decreases the amount of compressive force applied to the ICs 2 .
- the molding compound 1 is compressed down and spreads around each of the ICs 2 .
- the backside of the IC 2 is typically covered by a relatively thick layer of the molding compound 1 , as illustrated in FIG. 1 .
- this can result in increased warping of the packaging due to coefficient of thermal expansion mismatch, and the thickness of the packaging.
- Integrated circuits are often packaged in encapsulation layers, such as molding compounds, to protect the circuit elements.
- the front side has bonding pads on the integrated circuits coupled to soldering bumps for future connection to a larger circuit, such as a motherboard of a computer, whereas the backside is exposed or has a thin layer of epoxy covering it.
- an integrated circuit is first placed on an adhesive tape.
- An active surface of the integrated surface adheres to the tape so that the inactive surface is exposed, extending away from the tape.
- the tape is not rigid, but rather flexible and may act as a cushion for the integrated circuit.
- the tape is attached to a rigid carrier that supports the tape having the integrated circuit for transportation between processes. The tape and the carrier are attached in a manner that allows the two pieces to move as one.
- a molding chamber is provided that is sized and shaped to receive the integrated circuit attached to the tape and carrier.
- a molding compound is melted in the molding chamber.
- the carrier and tape combination is turned over so the inactive surface of the integrated circuit contacts the molding compound in the molding chamber first.
- the carrier and tape are then compressed to press the integrated circuit into the molding compound.
- a protective layer lines the interior surfaces of the molding chamber.
- the protective layer may be plastic or any material that is flexible and not rigid.
- the integrated circuit is compressed into the molding chamber until the inactive surface contacts the protective layer. Both the tape and the protective layer prevent damage to the integrated circuit by absorbing the compressive stress.
- a method of manufacturing fan-out wafer level packaging comprises: positioning an integrated circuit on a first surface; forming a layer of encapsulant on the first surface substantially surrounding the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit; forming a redistribution layer configured to electrically couple a bond pad of the integrated circuit to a redistributed bond pad; and forming a bump at the redistributed bond pad.
- FIG. 1 is a cross-sectional, side, schematic view of prior art fan-out wafer level packaging.
- FIGS. 2 and 3 are cross-sectional side views of a prior art process of forming the wafer level packaging of FIG. 1 .
- FIG. 4 is a cross-sectional, side, schematic view of fan-out wafer level packaging, according to one embodiment.
- FIGS. 5 and 6 illustrate a first plurality of processing acts that may be used in manufacturing the fan-out wafer level packaging of FIG. 4 , according to one embodiment.
- FIGS. 7A-7C illustrate an encapsulation process in accordance with one embodiment.
- FIGS. 8-13 illustrate a second plurality of processing acts that may be used in manufacturing the fan-out wafer level packaging of FIG. 4 , according to one embodiment.
- FIG. 4 shows fan-out wafer level packaging 100 , according to one illustrated embodiment.
- the fan-out wafer level packaging 100 may be configured to at least partially protect an integrated circuit 102 from the external environment.
- the fan-out wafer level packaging 100 is configured to include a plurality of bumps 104 electrically coupled to the integrated circuit 102 , and the fan-out wafer level packaging 100 may thus enable electrical connections to be formed between the integrated circuit 102 and external circuitry.
- other electrically conductive structures may be formed along an external surface of the fan-out wafer level packaging 100 in order to enable such electrical connections with the integrated circuit 102 .
- the integrated circuit 102 includes a variety of electronic circuitry.
- the integrated circuit 102 may comprise a controller for an electronic computing device, or a computer-readable memory.
- the integrated circuit 102 may be formed using any of a variety of semiconductor fabrication processes.
- the integrated circuit 102 is defined by layers of semi-conducting, dielectric and conducting materials deposited onto a semiconductor substrate in accordance with pre-defined patterns.
- Recent integrated circuits can use different materials for the integrated circuit construction than previously used. For many years, standard silicon dioxide, silicon nitride, and polysilicon layers were used to construct various interconnection layers between the substrate and the operational transistors that formed the integrated circuit. Initial circuits made some years ago had one or two layers of polysilicon on top of which may be one or two layers of metal. Recent advances in semiconductor technology have drastically increased the complexity of integrated circuits. Many circuits may have between two and five layers of polysilicon and between seven and twelve layers of metal above the polysilicon layers. Further, the size of the minimum gate width of transistors has shrunk dramatically with transistors in the range of 65 nm, 45 nm, and 32 nm becoming common. Future transistor sizes may approach 20 or 18 nm for the gate length.
- an uppermost polysilicon layer may be positioned over a plurality of insulating layers, which can include various nitride and oxide layers as well as a plurality of additionally polysilicon layers separated from each other by various sublayers of silicon nitride, silicon dioxide, and other types of insulators.
- metal layers may be formed with a premetal dielectric layer composed of a plurality of sublayers. In small geometry silicon chips, such as 90 nm and smaller, the premetal dielectrics are usually made of a low-k material.
- This low-k material may be an aerogel, a nanoporous dielectric, or other extremely low-k dielectric material.
- the low-k dielectric layers may be composed of a plurality of low-k dielectric layers and followed by yet another metal layer. This continues for many layers and sublayers.
- dielectric layers between the various metal layers may be composed of one or perhaps two glass layers, such as a spin-on glass, a silicon dioxide glass, or other strong layers which had high adhesive properties, and bonded strongly to each other.
- dielectric materials which have numerous small pockets of air distributed throughout in order to reduce the dielectric constant.
- Such low-k dielectric materials are not as structurally strong as a more solid glass, such as a spin-on glass or a solid silicon dioxide glass.
- these layers often contain chemical compositions which do not stick as tightly to each other as the prior art glasses.
- dielectric compounds may contain various combinations of carbon, fluoride, hydrogen, and other elements to increase the porosity and reduce the dielectric constant.
- the integrated circuit 102 When the integrated circuit 102 is heated or cooled, it expands or shrinks according to a coefficient of thermal expansion (CTE) particular to the material of the integrated circuit 102 .
- CTE coefficient of thermal expansion
- Each dielectric layer may have a slightly different CTE coefficient of expansion during heating.
- a material with a high CTE will expand or shrink more than a material with a lower CTE under a given increase or decrease in temperature.
- the molding compound, the integrated circuit 102 , the substrate, and the sublayers expand or contract differently from each other. This disparity in expansion causes the integrated circuit 102 to experience compressive, expansive, and tensile forces.
- the stress is felt more intensely at the edges and corners of the integrated circuit 102 .
- the repeated cycles of expansion and contraction may eventually cause layers in the integrated circuit to warp and separate. If a crack propagates from the inactive surface to the integrated circuitry, the crack can be fatal to the functionality of the integrated circuit.
- the repeated stresses may also cause delamination of the layers in the integrated circuit 102 .
- Delamination is the separation or unbending of any of the layers, sublayers, or components of the integrated circuit 102 .
- the adhesion between the various layers in integrated circuit 102 may fail. Delamination between any of the components can damage functionality of the integrated circuit.
- the stresses also cause warping of the integrated circuit 102 .
- the stress of the expansion and contraction of the components of the package can cause curvature of the integrated circuit 102 .
- This curvature which is focused at the edges and corners of the integrated circuit 102 , can result in poor solder joint formation in certain kinds of packages. Furthermore, the curvature can result in a loss of functionality of the integrated circuit 102 .
- a porous silicon is often used as a dielectric between circuit components and layers of the integrated circuit.
- the porous silicon is particularly prone to fracturing under stress. Any warping of the integrated circuit 102 can cause fracturing of the porous silicon. Compressive forces of contraction and expansion may also cause the porous silicon to fracture. This fracturing can damage functionality of the integrated circuit.
- thermo-mechanical stress is greater with larger integrated circuit 102 size.
- SOC system on chip
- integrated circuit 102 sizes increase due to the number of systems being integrated into one integrated circuit. Stress at the corners and edges of a larger integrated circuit 102 cause greater torque on the integrated circuit 102 and can more easily cause cracking, warping, or delamination of the integrated circuit 102 .
- the present invention is designed to prevent these problems in the large integrated circuit 102 s having low-k dielectrics.
- the integrated circuit 102 includes a front or top surface 106 and a back side or bottom surface 108 .
- front or top refers to the surface having the circuits therein and the back side or bottom is the other side of pure silicon.
- the back side 108 is exposed in the final package in one embodiment; in other embodiments it may have a thin layer of silicon carbide, resin or an epoxy or other passivation layer. Having the back side 108 exposed or having a thin covering of resin, epoxy or the like ensures reduced stress due to a thermal mismatch of the package holding the die.
- the packing resin material 112 will have a different Coefficient of Thermal Expansion, CTE, from the die 102 , by having a small amount of resin on the sides and either a thin or no layer on the back side, stress caused by differences in CTE of the different materials is kept low.
- CTE Coefficient of Thermal Expansion
- the integrated circuit 102 may further include a plurality of side surfaces 110 . Although not visible in FIG. 2 , the integrated circuit 102 may further include one or more bond pads defined on the top surface 106 . The number of bond pads may vary greatly depending upon the particular application for the integrated circuit 102 . For example, controller circuitry may require more bond pads defining input/outputs than memory circuitry.
- the bond pads may comprise any type of conducting material, such as copper, silver, or gold.
- the integrated circuit 102 may have any of a variety of shapes and sizes.
- the integrated circuit 102 has a generally rectilinear top surface 106 .
- the top surface 106 may have a generally square shape, and thus the integrated circuit 102 may include four side surfaces 110 . In other embodiments, more irregular shapes may define the integrated circuit 102 .
- the fan-out wafer level packaging 100 may further comprise a layer of encapsulant 112 substantially surrounding the side surfaces 110 of the integrated circuit 102 .
- the layer of encapsulant 112 may comprise any of a variety of encapsulants, such as a molding compound.
- the encapsulant comprises a dielectric material that serves to electrically insulate as well as at least partially protect the integrated circuit 102 from the external environment.
- the layer of encapsulant 112 may have any of a variety of shapes and sizes. As illustrated, the layer of encapsulant 112 has a height substantially equal to a height of the integrated circuit 102 . In one embodiment, the layer of encapsulant 112 has a height that is less than 20% greater than a height of the integrated circuit 102 . In other embodiments, the height of the layer of encapsulant 112 is less than 10% greater than the height of the integrated circuit 102 . In still other embodiments, the height of the layer of encapsulant 112 is equal to the height of integrated circuit 102 .
- the potential for warpage can be substantially reduced.
- the layer of encapsulant 112 may further have a generally rectilinear outer perimeter, such that the shape of the layer of encapsulant 112 and the shape of the integrated circuit 102 are geometrically similar.
- the fan-out wafer level packaging 100 may further include one or more bumps 104 positioned proximate a top surface 114 of the fan-out wafer level packaging 100 .
- Each of these bumps 104 is spaced apart from the integrated circuit 102 , but may be electrically coupled thereto.
- the bumps 104 may comprise any of a variety of solder bumps formed from different materials.
- the bumps 104 comprise lead-free solder bumps, while, in other embodiments, the bumps 104 include lead as well as other conductive materials, such as tin.
- two bumps 104 are visible in the cross-section of FIG. 2 , more bumps 104 are incorporated into the fan-out wafer level packaging 100 in different embodiments.
- at least one bump 104 may correspond to each bond pad defined on the top surface 106 of the integrated circuit 102 .
- the bumps 104 may also have any of a variety of sizes. In one embodiment, the bumps 104 have diameters of between 10 and 200 ⁇ m, depending upon their composition, as well as the processes used to form them.
- the fan-out wafer level packaging 100 may further include a redistribution layer 116 , also called a wiring layer or solder ball to bond pad coupling layers, configured to electrically couple a bond pad of the integrated circuit 102 to a corresponding bump 104 .
- the redistribution layer 116 may comprise any of a variety of electrically conductive materials defining at least part of an electrical path between particular bond pads of the integrated circuit 102 and corresponding bumps 104 .
- the redistribution layer 116 may comprise copper or gold in some embodiments.
- the redistribution layer 116 itself may include redistributed bond pads (located directly underneath corresponding bumps 104 ), and the bumps 104 may be in direct contact with the redistribution layer 116 .
- redistributed bond pads may be formed atop the redistribution layer 116 (as discussed in greater detail below), and the bumps 104 may be coupled thereto.
- the redistribution layer 116 may have any of a variety of thicknesses. In one embodiment, the redistribution layer 116 may be between 1 and 10 ⁇ m thick. Such a substantial thickness may facilitate the use of the redistribution layer 116 itself as a redistributed bond pad with lead-free bumps. In other embodiments, the redistribution layer 116 may be at least 1 ⁇ m thick. In such embodiments, it may be desirable to use the redistribution layer 116 with a separate redistributed bond pad to form the final interface with a corresponding bump 104 .
- the fan-out wafer level packaging 100 may further include dielectric layers 118 , 120 .
- Such dielectric layers 118 , 120 may add structural integrity to the fan-out wafer level packaging 100 , while keeping conductive elements of the fan-out wafer level packaging 100 electrically insulated from one another.
- a first dielectric layer 118 extends at least partially over the top surface 106 of the integrated circuit 102 .
- the first dielectric layer 118 may define at least one bond pad via, through which the redistribution layer 116 may contact a corresponding bond pad of the integrated circuit 102 . Two such bond pad vias are illustrated in the cross-sectional view of FIG. 4 . Of course, in other embodiments, more or fewer bond pad vias may be defined.
- a second dielectric layer 120 extends at least partially over the redistribution layer 116 .
- the second dielectric layer 120 may define at least one redistribution via therethrough that extends to the redistribution layer 116 .
- Two such redistribution vias are illustrated in the cross-sectional view of FIG. 2 .
- more or fewer redistribution vias may be defined.
- each redistribution via through the second dielectric layer 120 may correspond to exactly one bond pad via through the first dielectric layer 118 .
- the first dielectric layer 118 and the second dielectric layer 120 comprise the same dielectric material.
- a photosensitive polymer such as polyimide, polybenzoxazole or solder resist, may be used to define both the first dielectric layer 118 and the second dielectric layer 120 .
- different materials may be used to define the two dielectric layers 118 , 120 .
- the first dielectric layer 118 may have any of a variety of thicknesses. In one embodiment, the first dielectric layer 118 may be between approximately 5 and 10 ⁇ m thick, as measured from the top surface 106 of the integrated circuit 102 to the redistribution layer 116 .
- the second dielectric layer 120 may also be formed to define any of a variety of thicknesses. In one embodiment, a thickness of the second dielectric layer 120 may be greater than 2 ⁇ m added to a thickness of the redistribution layer 116 .
- FIGS. 5-13 illustrate different processing acts that may be used in a method of manufacturing fan-out wafer level packaging, according to one embodiment. This method will be discussed in the context of the fan-out wafer level packaging 100 of FIG. 4 . However, it may be understood that the acts disclosed herein may also be executed to manufacture a variety of differently configured fan-out wafer level packaging, in accordance with the described method.
- all of the acts comprising the method may be orchestrated by a manufacturing processor or controller based at least in part on execution of computer-readable instructions stored in memory.
- a hardware implementation of all or some of the acts of the manufacturing method may be used.
- a plurality of integrated circuits 102 may be formed by any of a variety of manufacturing processes.
- a wafer 300 including a plurality of integrated circuits 102 is provided.
- the wafer 300 may be processed in accordance with a variety of semiconductor processing techniques to form the integrated circuits 102 , and, in one embodiment, each of the integrated circuits 102 defined within the wafer 300 may be similarly configured.
- the wafer 300 may then be divided (e.g. by laser-cutting or die sawing) to define the individual integrated circuits 102 .
- the wafer 300 may also comprise a square panel ranging in size from 8′′ ⁇ 8′′ up to 12′′ ⁇ 12′′.
- the integrated circuits 102 may be positioned on a surface 302 of a backing 304 .
- the backing 304 may comprise any of a variety of surfaces, and, in one embodiment, the backing 304 may comprise an adhesive surface of a piece of tape. In one embodiment, only a single integrated circuit 102 may be positioned on the piece of tape; however, in other embodiments, as illustrated, a plurality of integrated circuits 102 may be positioned in an array thereon.
- the integrated circuits 102 may be placed atop the surface 302 in a variety of ways. For example, in one embodiment, a robotic end effector may be used to properly position the integrated circuits 102 . In another embodiment, a human operator places the integrated circuit 102 manually or by a user-controlled machine. The integrated circuits 102 may be positioned with the top surface 106 of the integrated circuits 102 facing the surface 302 . The top surface 106 may correspond to the area of the integrated circuit 102 that contains active regions as opposed to a silicon substrate. The integrated circuits 102 are spaced on the surface 302 by a predetermined distance to ensure sufficient space for singulating the ICs later in the process.
- a layer of encapsulant 112 may then be formed on the first surface 302 substantially surrounding the integrated circuits 102 , as shown in FIG. 6 .
- the layer of encapsulant 112 has a height substantially equal to a height of the integrated circuits 102 .
- the layer of encapsulant 112 may be formed by any of a variety of manufacturing processes.
- FIGS. 7A-7C illustrate a manufacturing process for forming the encapsulation layer 112 of a height substantially similar to the height of the IC 102 .
- a predetermined amount of encapsulant 112 is placed on a protective layer 208 in a mold chase 200 .
- the protective layer 208 may be formed of plastic or other material that is not rigid.
- the protective layer 208 is configured to depress or otherwise cushion the inactive surface, i.e. the bottom surface 108 , of the integrated circuit 102 when the inactive surface is compressed onto the protective layer 208 , as described below.
- the encapsulant 112 may be a molding compound or a molding resin.
- the encapsulant 112 may be in a liquid or a powder form.
- the mold chase 200 may be formed of metal and is configured to heat the powder to a liquid form. If the encapsulant is initially liquid, the mold chase 200 is configured to maintain the liquid at a specific temperature in preparation for application to the ICs 102 . For example, the liquid encapsulant 112 may be kept at a temperature of 120 to 150 degrees Celsius. Additionally, the encapsulant may be used that is liquid at lower temperature and subsequently form crosslinks at higher temperatures. The crosslinks may cause the encapsulant to withstand more heat after initial solidification so that the encapsulant does not re-melt if the IC 102 operates at a temperature higher than 120 degrees Celsius.
- FIG. 7B illustrates the encapsulant in a molten form, evenly disbursed across the entire mold chase 200 .
- the protective layer 208 which may be plastic, completely covers all interior surfaces of the mold chase 200 including top and side surfaces of walls 204 and 206 .
- the protective layer 208 prevents the ICs 102 from contacting the hard metal surfaces of the mold chase 200 .
- the protective layer 208 is 100 microns thick.
- FIG. 7C illustrates the compressive molding of the encapsulant 112 around the side surfaces 110 of the ICs 102 .
- the backing 304 may be applied to a carrier layer 306 before or after the ICs 102 are arranged on the surface 302 .
- the backing 304 may be an adhesive tape that is elastic or otherwise flexible.
- the active surface of the integrated circuit, i.e., the top surface 106 is positioned on the backing 304 .
- the carrier layer 306 may be a plexiglass plate and may provide support for the backing.
- the carrier layer 306 allows for transport of the ICs 102 to the mold chase 200 .
- the carrier layer 306 allows for the backing 304 and ICs 102 to be turned over so that the bottom surfaces 108 of the ICs 102 enter the encapsulant 112 in the mold chase 200 first.
- a portion of the backing 304 and the carrier 306 extend past the exterior boundary 110 of the outermost IC 102 so that when turned over the portion rests on the protective layer 208 over the top surface of the walls 204 , 206 .
- the walls 204 , 206 have a height that corresponds to a height of the ICs 102 so that little or no encapsulant covers the bottom surface 108 of the IC 102 .
- a compressive force is applied with a compressive member 210 .
- the compressive member 210 is sized and shaped to correspond to the mold chase 200 and is configured to hold the carrier 306 by vacuum suction. During compression, the mold chase 200 is under pressure to remove air.
- the encapsulant 112 wicks around the side surfaces 110 of the ICs 102 as the compressive member presses down and the air is removed.
- the encapsulant 112 covers all of the side surfaces 110 of the ICs and is substantially the same height as the ICs.
- the protective layer 208 protects the IC 102 from any damage or scratching that may be caused by the compression. It also absorbs some of the compression from the fluid resin 112 , thus reducing the amount of stress placed on the die 102 during the molding process.
- the integrated circuit As the compressive member 210 presses the carrier and the integrated circuit into the mold chase 200 , the integrated circuit is cushioned by the backing 304 on the top surface 106 and by the protective layer 208 on the bottom surface 108 .
- the integrated circuit experiences non-compressive forces of the liquid encapsulant 112 only on the sides 110 . Liquid is non-compressable and by having the backing 304 and layer 208 present, compressive forces on the sides of the die are reduced or eliminated. This significantly reduces the amount of compressive stress experienced by the integrated circuit, which in turn significantly reduces the problems of warpage during heating and cooling of the packaged integrated circuit. Further as the hot resin 112 cools to form a solid, stress from the effects of difference in CTE are greatly reduced.
- the desired weight of the encapsulant is calculated, then weighed as it is put in the mold. Too much encapsulant 112 prevents the mold chase 200 and compressive member 210 from pressing down the desired amount and causes the final thickness of the encapsulant to be higher, so this is avoided.
- the encapsulant may be heat-treated, cold-treated or otherwise processed in order to change the chemical or physical characteristics of the encapsulant 112 .
- the encapsulant 112 is cured in some manner. In other embodiments, other manufacturing processes for forming the layer of encapsulant 112 may be used.
- the piece of tape 304 may then be removed, as illustrated in FIG. 8 , to leave what is effectively an array of integrated circuits 102 encased in the layer of encapsulant 112 .
- the top surface 106 of the integrated circuit 102 may have been facing towards the tape 304 .
- the top surface 106 of the integrated circuit 102 is facing the top of the drawing.
- the top surface 106 and the bottom surface 108 of the integrated circuit 102 are both exposed, and the layer of encapsulant 112 substantially covers four side surfaces 110 of the integrated circuit 102 .
- a first dielectric layer 118 may be formed extending at least partially over the top surface 106 of the integrated circuit 102 .
- the first dielectric layer 118 may be formed to include at least one bond pad via 122 through which at least a portion of a bond pad of the integrated circuit 102 is exposed. These bond pad vias 122 may enable subsequent electrical connections to be formed between the bond pads of the integrated circuit 102 and one or more redistributed bond pads.
- the first dielectric layer 118 may comprise any of a variety of dielectric materials.
- the first dielectric layer 118 comprises a photosensitive polymer, such as polyimide, polybenzoxazole, or solder resist.
- the first dielectric layer 118 may also be deposited and then patterned to form the bond pad vias 122 by any of a variety of processes. If the first dielectric layer 118 comprises a photosensitive polymer, the photosensitive polymer may first be coated over the layer of encapsulant 112 and integrated circuit 102 . After this coating, in some embodiments, the first dielectric layer 118 is planarized. Portions of the first dielectric layer 118 may then be exposed to light (e.g., to ultraviolet light) to create a desired patterning in this layer 118 .
- light e.g., to ultraviolet light
- the exposed portions of the first dielectric layer 118 may then be removed by application of a developer solvent if a positive photosensitive polymer is used, or the unexposed portions may be removed if a negative photosensitive polymer is used.
- a developer solvent if a positive photosensitive polymer is used, or the unexposed portions may be removed if a negative photosensitive polymer is used.
- other patterning processes may be used.
- a separate photoresist layer may be deposited on top of the first dielectric layer 118 in order to define and then transfer a desired pattern to the first dielectric layer 118 .
- Additional chemical, physical or thermal processing may be carried out to cure or harden the first dielectric layer 118 .
- the partially formed fan-out wafer level packaging 100 may be baked to cure the first dielectric layer 118 .
- a redistribution layer 116 configured to electrically couple the bond pad of the integrated circuit 102 to a redistributed bond pad may also be formed.
- the redistribution layer 116 may comprise any of a variety of electrically conductive materials, as discussed above. As illustrated, the redistribution layer 116 may be formed over at least a portion of the first dielectric layer 118 and may fill at least partially the bond pad via 122 . Thus, the redistribution layer 116 may create electrical connections between the bond pads of the integrated circuit 102 and one or more redistributed bond pads through the bond pad vias 122 .
- a seed layer (not shown) may first be sputtered over the first dielectric layer 118 .
- the seed layer may comprise a metallic thin film, such as copper. This seed layer may thus extend over the entire exposed surface of the partially formed fan-out wafer level packaging 100 .
- a patterned layer may then be formed over the seed layer using photolithography. Any of a variety of photolithographic techniques may be used to form such a patterned layer over the seed layer.
- the patterned layer may comprise, for example, photoresist material.
- the patterned layer may leave portions of the seed layer exposed in a pattern that will eventually define the pattern of the redistribution layer 116 .
- At least a portion of the seed layer exposed through the patterned layer may then be plated to form the redistribution layer 116 .
- electrochemical plating or electroless plating may be performed to create a copper redistribution layer 116 .
- the patterned layer may then be removed, and the remaining portions of the seed layer that were not plated may also be removed. Any of a variety of chemical or physical processes, such as wet etching, may be used to remove these layers, leaving the patterned redistribution layer 116 . Of course, in other embodiments, other techniques for forming a patterned redistribution layer 116 may be used.
- a second dielectric layer 120 may be formed extending at least partially over the redistribution layer 116 and including at least one redistribution via 124 through which at least a portion of the redistribution layer 116 is exposed.
- These redistribution vias 124 may define the locations for one or more redistributed bond pads.
- the redistribution layer 116 may itself define the redistributed bond pads.
- a redistributed bond pad may be formed at least partially within a corresponding redistribution via 124 , as described in greater detail below.
- the second dielectric layer 120 may comprise any of a variety of dielectric materials.
- the second dielectric layer 120 and the first dielectric layer 118 comprise the same material.
- the second dielectric layer 120 may comprise a photosensitive polymer, such as polyimide, polybenzoxazole or solder resist.
- the second dielectric layer 120 may be deposited and then patterned to form the redistribution vias 124 in a variety of ways. If the second dielectric layer 120 comprises a photosensitive polymer, the photosensitive polymer may first be coated over the redistribution layer 116 and exposed portions of the first dielectric layer 118 . After this coating, in some embodiments, the second dielectric layer 120 is planarized. Portions of the second dielectric layer 120 may then be exposed to light (e.g., to ultraviolet light) to create the desired patterning in this layer 120 .
- light e.g., to ultraviolet light
- the exposed portions of the second dielectric layer 120 may then be removed by application of a developer solvent if a positive photosensitive polymer is used, or the unexposed portions may be removed if a negative photosensitive polymer is used.
- a developer solvent if a positive photosensitive polymer is used, or the unexposed portions may be removed if a negative photosensitive polymer is used.
- other patterning processes may be used.
- a separate photoresist layer may be deposited on top of the second dielectric layer 120 in order to define and then transfer a desired pattern to the second dielectric layer 120 .
- Additional chemical, physical or thermal processing may be carried out to cure or harden the second dielectric layer 120 .
- the partially formed fan-out wafer level packaging 100 may be baked to cure the second dielectric layer 120 .
- Bumps 104 may then be formed at the redistributed bond pad, as illustrated in FIG. 11 .
- the bumps 104 may comprise any of a variety of conductive materials, as described above.
- the bumps 104 may comprise lead-free bumps, although in other embodiments leaded bumps may be used.
- the redistributed bond pad may simply be defined by the portions of the redistribution layer 116 exposed through the redistribution vias 124 , as illustrated in FIG. 11 .
- the bumps 104 may be formed by conventional ball bonding techniques in direct contact with the redistribution layer 116 .
- the bumps 104 may be formed on the partially formed fan-out wafer level packaging 100 to form the completed fan-out wafer level packaging 100 of FIG. 4 .
- a redistributed bond pad may be formed at least partially within the redistribution via 124 .
- Such a redistributed bond pad may comprise an under-bump-metallurgy layer configured to facilitate the electrical connection formed between the bump 104 and the redistribution layer 116 .
- This redistributed bond pad may be formed by a variety of processes.
- the redistributed bond pad may be formed by sputtering a compound of either: (a) titanium, nickel and copper, or (b) aluminum, nickel and copper.
- the sputtered compound may then be plated with a compound of either: (a) titanium and copper, (b) titanium, tungsten and copper, or (c) chromium and copper.
- the redistributed bond pad may be formed by plating the exposed redistribution layer 116 with at least one of: (a) copper, (b) nickel, or (c) copper and nickel.
- FIG. 12 illustrates planarization of the ICs 102 .
- portions of the encapsulant layer 112 and the inactive region of the integrated circuit 102 that is exposed or covered by a thin layer of encapsulant is ground away leaving 450 microns of the ICs.
- the vertical dotted lines illustrate where a die cutter or laser may singulate the ICs 102 .
- FIG. 13 illustrates an alternative embodiment, where a backside coating 130 protects the bottom surface 108 of the ICs 102 prior to singulation.
- the backside coating 130 may be an epoxy or other material suitable for protecting the bottom surface 108 of the IC from damage. Additionally or alternatively, the backside coating may have a similar coefficient of thermal expansion as the silicon of the IC 102 .
- the layer 130 can be thin, so that if it has a CTE different from the die 102 , there is little to no additional stress put on the die 102 when it goes through heating and cooling cycles. Another way to achieve this is to have the same CTE for both materials, while yet another way is to have no layer over the back side 108 .
- a prior art die would have height h between 800 and 2000 microns of resin above the bottom surface of the die (see FIG. 1 ).
- a resin height h of 1000 microns is common.
- one embodiment of the present invention has no resin on the back side of the die, avoiding the issue completely.
- a thin layer of material under 120 microns and preferably in the range of about 40 to 90 microns of material 130 is on the back side 108 of the die, with 80 microns being preferred.
- the material 130 can be a type of material having a CTE that is closer to that of the die than the encapsulating resin 112 , thus providing even less stress. It can also be an epoxy, a polymer, or other material which, even though the CTE is different from the die, the height “h” is in the range of about 80 to 100 microns, thus not providing large stress on the die during heating and cooling cycles.
- the completed fan-out wafer level packaging 100 is illustrated in FIG. 4 .
- the resulting wafer may be tested and then singulated to form the individual fan-out wafer level packaging 100 (e.g., via dicing or laser-cutting), as shown in FIGS. 12 and 13 .
- the packaging 100 may have been singulated at an earlier stage in the process.
- the fan-out wafer level packaging 100 may be coupled to one or more additional chip packages or electronic devices via the bumps 104 .
- logic or information can be stored on any computer readable storage medium for use by or in connection with any processor-related system or method.
- a memory is a computer readable storage medium that is an electronic, magnetic, optical, or other physical device or means that contains or stores a computer and/or processor program and/or data or information.
- Logic and/or the information can be embodied in any computer readable storage medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions associated with logic and/or information.
Abstract
Description
- 1. Technical Field
- This description generally relates to the field of chip packaging, and more particularly to fan-out wafer level packaging.
- 2. Description of the Related Art
- Redistributing the bond pads of integrated circuits (“ICs”) in chip packages is becoming increasingly common. In general, the redistribution process converts peripheral wire bond pads on an IC to an area array of solder bumps via a redistribution layer. The resulting fan-out wafer level packaging may have a larger solder bump bonding area and may be more easily integrated into electronic devices and larger chip packages.
- Referring to
FIG. 1 , conventional fan-out wafer level packaging is illustrated. Conventionally, a backside of anIC 2 is first encapsulated in a molding compound 1. A plurality ofdielectric layers 4 andredistribution layers 3 are then deposited on a front side of theIC 2 to form electrical connections betweenwire bond pads 7 on theIC 2 and redistributed solderbump bond pads 5. Finally,solder bumps 6 are formed at the redistributedbond pad locations 5, and the fan-out wafer level packaging is ready to be soldered to a printed circuit board. -
FIG. 2 illustrates the encapsulation process as applied to a plurality ofICs 2 arranged on a surface, such as a tape 8 on a carrier 9. The mold compound 1 is dispensed centrally on the tape 8 at a thickness sufficient to completely cover all exposed surfaces of eachIC 2. TheICs 2 are placed in amold chase 10 that is configured to compress the molding compound 1 down and around all of theICs 2. A large amount of molding compound 1 is required to ensure that all side surfaces and the backside of eachIC 2 is completely covered. - As shown in
FIG. 3 , prior to compressing the mold compound 1 down around the ICs 2 aprotective film 11 is arranged over the molding compound 1 and acrossexterior edges protective film 11 decreases the amount of compressive force applied to theICs 2. Subsequently, the molding compound 1 is compressed down and spreads around each of theICs 2. - Unfortunately, after employing such packaging methods, the backside of the
IC 2 is typically covered by a relatively thick layer of the molding compound 1, as illustrated inFIG. 1 . As a result, this can result in increased warping of the packaging due to coefficient of thermal expansion mismatch, and the thickness of the packaging. - There remains a need in the art, therefore, for an improved method of manufacturing fan-out wafer level packaging.
- A method of packing a die in which an encapsulation layer is formed around the four sides of an integrated circuit and is not formed on the front side or the back side, thus providing a package die in which an inactive surface of the integrated circuit is not covered by the encapsulation layer. Integrated circuits are often packaged in encapsulation layers, such as molding compounds, to protect the circuit elements. The front side has bonding pads on the integrated circuits coupled to soldering bumps for future connection to a larger circuit, such as a motherboard of a computer, whereas the backside is exposed or has a thin layer of epoxy covering it.
- According to one embodiment of the present disclosure, an integrated circuit is first placed on an adhesive tape. An active surface of the integrated surface adheres to the tape so that the inactive surface is exposed, extending away from the tape. The tape is not rigid, but rather flexible and may act as a cushion for the integrated circuit. The tape is attached to a rigid carrier that supports the tape having the integrated circuit for transportation between processes. The tape and the carrier are attached in a manner that allows the two pieces to move as one.
- A molding chamber is provided that is sized and shaped to receive the integrated circuit attached to the tape and carrier. A molding compound is melted in the molding chamber. Subsequently, the carrier and tape combination is turned over so the inactive surface of the integrated circuit contacts the molding compound in the molding chamber first. The carrier and tape are then compressed to press the integrated circuit into the molding compound.
- A protective layer lines the interior surfaces of the molding chamber. The protective layer may be plastic or any material that is flexible and not rigid. The integrated circuit is compressed into the molding chamber until the inactive surface contacts the protective layer. Both the tape and the protective layer prevent damage to the integrated circuit by absorbing the compressive stress.
- A method of manufacturing fan-out wafer level packaging is disclosed. The method comprises: positioning an integrated circuit on a first surface; forming a layer of encapsulant on the first surface substantially surrounding the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit; forming a redistribution layer configured to electrically couple a bond pad of the integrated circuit to a redistributed bond pad; and forming a bump at the redistributed bond pad.
- In the drawings, identical reference numbers identify similar elements or acts. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes of various elements and angles are not drawn to scale, and some of these elements are enlarged and positioned to improve drawing legibility. Further, the particular shapes of the elements as drawn, are not intended to convey any information regarding the actual shape of the particular elements, and have been solely selected for ease of recognition in the drawings.
-
FIG. 1 is a cross-sectional, side, schematic view of prior art fan-out wafer level packaging. -
FIGS. 2 and 3 are cross-sectional side views of a prior art process of forming the wafer level packaging ofFIG. 1 . -
FIG. 4 is a cross-sectional, side, schematic view of fan-out wafer level packaging, according to one embodiment. -
FIGS. 5 and 6 illustrate a first plurality of processing acts that may be used in manufacturing the fan-out wafer level packaging ofFIG. 4 , according to one embodiment. -
FIGS. 7A-7C illustrate an encapsulation process in accordance with one embodiment. -
FIGS. 8-13 illustrate a second plurality of processing acts that may be used in manufacturing the fan-out wafer level packaging ofFIG. 4 , according to one embodiment. - In the following description, certain specific details are set forth in order to provide a thorough understanding of various disclosed embodiments. However, one skilled in the relevant art will recognize that embodiments may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures and methods associated with integrated circuits and semiconductor manufacturing/packaging processes have not been shown or described in detail to avoid unnecessarily obscuring descriptions of the embodiments.
- Unless the context requires otherwise, throughout the specification and claims which follow, the word “comprise” and variations thereof, such as, “comprises” and “comprising” are to be construed in an open, inclusive sense, that is, as “including, but not limited to.”
- Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
- As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. It should also be noted that the term “or” is generally employed in its sense including “and/or” unless the context clearly dictates otherwise.
- The headings and Abstract of the Disclosure provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.
-
FIG. 4 shows fan-outwafer level packaging 100, according to one illustrated embodiment. The fan-outwafer level packaging 100 may be configured to at least partially protect anintegrated circuit 102 from the external environment. In other embodiments, the fan-outwafer level packaging 100 is configured to include a plurality ofbumps 104 electrically coupled to theintegrated circuit 102, and the fan-outwafer level packaging 100 may thus enable electrical connections to be formed between theintegrated circuit 102 and external circuitry. In other embodiments, other electrically conductive structures may be formed along an external surface of the fan-outwafer level packaging 100 in order to enable such electrical connections with theintegrated circuit 102. - The
integrated circuit 102 includes a variety of electronic circuitry. For example, theintegrated circuit 102 may comprise a controller for an electronic computing device, or a computer-readable memory. In different embodiments, theintegrated circuit 102 may be formed using any of a variety of semiconductor fabrication processes. In one embodiment, theintegrated circuit 102 is defined by layers of semi-conducting, dielectric and conducting materials deposited onto a semiconductor substrate in accordance with pre-defined patterns. - Recent integrated circuits can use different materials for the integrated circuit construction than previously used. For many years, standard silicon dioxide, silicon nitride, and polysilicon layers were used to construct various interconnection layers between the substrate and the operational transistors that formed the integrated circuit. Initial circuits made some years ago had one or two layers of polysilicon on top of which may be one or two layers of metal. Recent advances in semiconductor technology have drastically increased the complexity of integrated circuits. Many circuits may have between two and five layers of polysilicon and between seven and twelve layers of metal above the polysilicon layers. Further, the size of the minimum gate width of transistors has shrunk dramatically with transistors in the range of 65 nm, 45 nm, and 32 nm becoming common. Future transistor sizes may approach 20 or 18 nm for the gate length.
- Another improvement further increasing the complexity is the use of many different types of dielectric layers between the substrate and the first metal layer and between various metal layers. For example, an uppermost polysilicon layer may be positioned over a plurality of insulating layers, which can include various nitride and oxide layers as well as a plurality of additionally polysilicon layers separated from each other by various sublayers of silicon nitride, silicon dioxide, and other types of insulators. Additionally, metal layers may be formed with a premetal dielectric layer composed of a plurality of sublayers. In small geometry silicon chips, such as 90 nm and smaller, the premetal dielectrics are usually made of a low-k material. This low-k material may be an aerogel, a nanoporous dielectric, or other extremely low-k dielectric material. The low-k dielectric layers may be composed of a plurality of low-k dielectric layers and followed by yet another metal layer. This continues for many layers and sublayers.
- In the prior art, dielectric layers between the various metal layers may be composed of one or perhaps two glass layers, such as a spin-on glass, a silicon dioxide glass, or other strong layers which had high adhesive properties, and bonded strongly to each other. On the other hand, the more modern chips, use dielectric materials which have numerous small pockets of air distributed throughout in order to reduce the dielectric constant. Such low-k dielectric materials are not as structurally strong as a more solid glass, such as a spin-on glass or a solid silicon dioxide glass. In addition, these layers often contain chemical compositions which do not stick as tightly to each other as the prior art glasses. Such dielectric compounds may contain various combinations of carbon, fluoride, hydrogen, and other elements to increase the porosity and reduce the dielectric constant. These low-k dielectrics provide enhanced electrical performance, but the structural integrity is substantially less than was provided in prior art semiconductor devices. In addition, the adhesive bonding strength between the various layers is reduced.
- Repeated cycles of heating and cooling are problematic to the structural integrity of integrated circuits with many low-k dielectric layers. When the
integrated circuit 102 is heated or cooled, it expands or shrinks according to a coefficient of thermal expansion (CTE) particular to the material of theintegrated circuit 102. Each dielectric layer may have a slightly different CTE coefficient of expansion during heating. A material with a high CTE will expand or shrink more than a material with a lower CTE under a given increase or decrease in temperature. When the package is heated or cooled, the molding compound, theintegrated circuit 102, the substrate, and the sublayers expand or contract differently from each other. This disparity in expansion causes theintegrated circuit 102 to experience compressive, expansive, and tensile forces. The stress is felt more intensely at the edges and corners of theintegrated circuit 102. The repeated cycles of expansion and contraction may eventually cause layers in the integrated circuit to warp and separate. If a crack propagates from the inactive surface to the integrated circuitry, the crack can be fatal to the functionality of the integrated circuit. - The repeated stresses may also cause delamination of the layers in the
integrated circuit 102. Delamination is the separation or unbending of any of the layers, sublayers, or components of theintegrated circuit 102. For example, under stress, the adhesion between the various layers inintegrated circuit 102 may fail. Delamination between any of the components can damage functionality of the integrated circuit. - The stresses also cause warping of the
integrated circuit 102. The stress of the expansion and contraction of the components of the package can cause curvature of theintegrated circuit 102. This curvature, which is focused at the edges and corners of theintegrated circuit 102, can result in poor solder joint formation in certain kinds of packages. Furthermore, the curvature can result in a loss of functionality of theintegrated circuit 102. - In applications where a small dielectric constant is needed (low k applications), a porous silicon is often used as a dielectric between circuit components and layers of the integrated circuit. The porous silicon is particularly prone to fracturing under stress. Any warping of the
integrated circuit 102 can cause fracturing of the porous silicon. Compressive forces of contraction and expansion may also cause the porous silicon to fracture. This fracturing can damage functionality of the integrated circuit. - The effects of thermo-mechanical stress are greater with larger
integrated circuit 102 size. With system on chip (SOC) technology, integratedcircuit 102 sizes increase due to the number of systems being integrated into one integrated circuit. Stress at the corners and edges of a largerintegrated circuit 102 cause greater torque on theintegrated circuit 102 and can more easily cause cracking, warping, or delamination of theintegrated circuit 102. The present invention is designed to prevent these problems in the large integrated circuit 102 s having low-k dielectrics. - As illustrated, the
integrated circuit 102 includes a front ortop surface 106 and a back side orbottom surface 108. Of course, the terms, top and bottom, should not be understood to imply any absolute positioning of theintegrated circuit 102, rather, front or top refers to the surface having the circuits therein and the back side or bottom is the other side of pure silicon. Theback side 108 is exposed in the final package in one embodiment; in other embodiments it may have a thin layer of silicon carbide, resin or an epoxy or other passivation layer. Having theback side 108 exposed or having a thin covering of resin, epoxy or the like ensures reduced stress due to a thermal mismatch of the package holding the die. The packingresin material 112 will have a different Coefficient of Thermal Expansion, CTE, from thedie 102, by having a small amount of resin on the sides and either a thin or no layer on the back side, stress caused by differences in CTE of the different materials is kept low. - The
integrated circuit 102 may further include a plurality of side surfaces 110. Although not visible inFIG. 2 , theintegrated circuit 102 may further include one or more bond pads defined on thetop surface 106. The number of bond pads may vary greatly depending upon the particular application for theintegrated circuit 102. For example, controller circuitry may require more bond pads defining input/outputs than memory circuitry. The bond pads may comprise any type of conducting material, such as copper, silver, or gold. - The
integrated circuit 102 may have any of a variety of shapes and sizes. In one embodiment, theintegrated circuit 102 has a generally rectilineartop surface 106. For example, thetop surface 106 may have a generally square shape, and thus theintegrated circuit 102 may include four side surfaces 110. In other embodiments, more irregular shapes may define theintegrated circuit 102. - The fan-out
wafer level packaging 100 may further comprise a layer ofencapsulant 112 substantially surrounding the side surfaces 110 of theintegrated circuit 102. The layer ofencapsulant 112 may comprise any of a variety of encapsulants, such as a molding compound. In one embodiment, the encapsulant comprises a dielectric material that serves to electrically insulate as well as at least partially protect theintegrated circuit 102 from the external environment. - The layer of
encapsulant 112, like theintegrated circuit 102, may have any of a variety of shapes and sizes. As illustrated, the layer ofencapsulant 112 has a height substantially equal to a height of theintegrated circuit 102. In one embodiment, the layer ofencapsulant 112 has a height that is less than 20% greater than a height of theintegrated circuit 102. In other embodiments, the height of the layer ofencapsulant 112 is less than 10% greater than the height of theintegrated circuit 102. In still other embodiments, the height of the layer ofencapsulant 112 is equal to the height ofintegrated circuit 102. In one embodiment, by making the height of the layer ofencapsulant 112 substantially equal to the height of theintegrated circuit 102, the potential for warpage can be substantially reduced. The layer ofencapsulant 112 may further have a generally rectilinear outer perimeter, such that the shape of the layer ofencapsulant 112 and the shape of theintegrated circuit 102 are geometrically similar. - The fan-out
wafer level packaging 100 may further include one ormore bumps 104 positioned proximate atop surface 114 of the fan-outwafer level packaging 100. Each of thesebumps 104 is spaced apart from theintegrated circuit 102, but may be electrically coupled thereto. Thebumps 104 may comprise any of a variety of solder bumps formed from different materials. In one embodiment, thebumps 104 comprise lead-free solder bumps, while, in other embodiments, thebumps 104 include lead as well as other conductive materials, such as tin. Although twobumps 104 are visible in the cross-section ofFIG. 2 ,more bumps 104 are incorporated into the fan-outwafer level packaging 100 in different embodiments. For example, in some embodiments, at least onebump 104 may correspond to each bond pad defined on thetop surface 106 of theintegrated circuit 102. - The
bumps 104 may also have any of a variety of sizes. In one embodiment, thebumps 104 have diameters of between 10 and 200 μm, depending upon their composition, as well as the processes used to form them. - The fan-out
wafer level packaging 100 may further include aredistribution layer 116, also called a wiring layer or solder ball to bond pad coupling layers, configured to electrically couple a bond pad of theintegrated circuit 102 to acorresponding bump 104. Theredistribution layer 116 may comprise any of a variety of electrically conductive materials defining at least part of an electrical path between particular bond pads of theintegrated circuit 102 andcorresponding bumps 104. For example, theredistribution layer 116 may comprise copper or gold in some embodiments. - In one embodiment, as illustrated in
FIG. 4 , theredistribution layer 116 itself may include redistributed bond pads (located directly underneath corresponding bumps 104), and thebumps 104 may be in direct contact with theredistribution layer 116. However, in other embodiments, redistributed bond pads may be formed atop the redistribution layer 116 (as discussed in greater detail below), and thebumps 104 may be coupled thereto. - The
redistribution layer 116 may have any of a variety of thicknesses. In one embodiment, theredistribution layer 116 may be between 1 and 10 μm thick. Such a substantial thickness may facilitate the use of theredistribution layer 116 itself as a redistributed bond pad with lead-free bumps. In other embodiments, theredistribution layer 116 may be at least 1 μm thick. In such embodiments, it may be desirable to use theredistribution layer 116 with a separate redistributed bond pad to form the final interface with acorresponding bump 104. - The fan-out
wafer level packaging 100 may further includedielectric layers dielectric layers wafer level packaging 100, while keeping conductive elements of the fan-outwafer level packaging 100 electrically insulated from one another. In one embodiment, a firstdielectric layer 118 extends at least partially over thetop surface 106 of theintegrated circuit 102. Thefirst dielectric layer 118 may define at least one bond pad via, through which theredistribution layer 116 may contact a corresponding bond pad of theintegrated circuit 102. Two such bond pad vias are illustrated in the cross-sectional view ofFIG. 4 . Of course, in other embodiments, more or fewer bond pad vias may be defined. - In one embodiment, a
second dielectric layer 120 extends at least partially over theredistribution layer 116. Thesecond dielectric layer 120 may define at least one redistribution via therethrough that extends to theredistribution layer 116. Two such redistribution vias are illustrated in the cross-sectional view ofFIG. 2 . Of course, in other embodiments, more or fewer redistribution vias may be defined. In one embodiment, each redistribution via through thesecond dielectric layer 120 may correspond to exactly one bond pad via through thefirst dielectric layer 118. - In one embodiment, the
first dielectric layer 118 and thesecond dielectric layer 120 comprise the same dielectric material. For example, a photosensitive polymer, such as polyimide, polybenzoxazole or solder resist, may be used to define both thefirst dielectric layer 118 and thesecond dielectric layer 120. In other embodiments, different materials may be used to define the twodielectric layers - The
first dielectric layer 118 may have any of a variety of thicknesses. In one embodiment, thefirst dielectric layer 118 may be between approximately 5 and 10 μm thick, as measured from thetop surface 106 of theintegrated circuit 102 to theredistribution layer 116. Thesecond dielectric layer 120 may also be formed to define any of a variety of thicknesses. In one embodiment, a thickness of thesecond dielectric layer 120 may be greater than 2 μm added to a thickness of theredistribution layer 116. -
FIGS. 5-13 illustrate different processing acts that may be used in a method of manufacturing fan-out wafer level packaging, according to one embodiment. This method will be discussed in the context of the fan-outwafer level packaging 100 ofFIG. 4 . However, it may be understood that the acts disclosed herein may also be executed to manufacture a variety of differently configured fan-out wafer level packaging, in accordance with the described method. - As described herein, all of the acts comprising the method may be orchestrated by a manufacturing processor or controller based at least in part on execution of computer-readable instructions stored in memory. In other embodiments, a hardware implementation of all or some of the acts of the manufacturing method may be used.
- First, a plurality of
integrated circuits 102 may be formed by any of a variety of manufacturing processes. In one embodiment, as illustrated inFIG. 5 , awafer 300 including a plurality ofintegrated circuits 102 is provided. Thewafer 300 may be processed in accordance with a variety of semiconductor processing techniques to form theintegrated circuits 102, and, in one embodiment, each of theintegrated circuits 102 defined within thewafer 300 may be similarly configured. Thewafer 300 may then be divided (e.g. by laser-cutting or die sawing) to define the individualintegrated circuits 102. Although illustrated as round, thewafer 300 may also comprise a square panel ranging in size from 8″×8″ up to 12″×12″. - Once separated, the
integrated circuits 102 may be positioned on asurface 302 of abacking 304. Thebacking 304 may comprise any of a variety of surfaces, and, in one embodiment, thebacking 304 may comprise an adhesive surface of a piece of tape. In one embodiment, only a singleintegrated circuit 102 may be positioned on the piece of tape; however, in other embodiments, as illustrated, a plurality ofintegrated circuits 102 may be positioned in an array thereon. - The
integrated circuits 102 may be placed atop thesurface 302 in a variety of ways. For example, in one embodiment, a robotic end effector may be used to properly position theintegrated circuits 102. In another embodiment, a human operator places theintegrated circuit 102 manually or by a user-controlled machine. Theintegrated circuits 102 may be positioned with thetop surface 106 of theintegrated circuits 102 facing thesurface 302. Thetop surface 106 may correspond to the area of theintegrated circuit 102 that contains active regions as opposed to a silicon substrate. Theintegrated circuits 102 are spaced on thesurface 302 by a predetermined distance to ensure sufficient space for singulating the ICs later in the process. - A layer of
encapsulant 112 may then be formed on thefirst surface 302 substantially surrounding theintegrated circuits 102, as shown inFIG. 6 . The layer ofencapsulant 112 has a height substantially equal to a height of theintegrated circuits 102. The layer ofencapsulant 112 may be formed by any of a variety of manufacturing processes. -
FIGS. 7A-7C illustrate a manufacturing process for forming theencapsulation layer 112 of a height substantially similar to the height of theIC 102. A predetermined amount ofencapsulant 112 is placed on aprotective layer 208 in amold chase 200. Theprotective layer 208 may be formed of plastic or other material that is not rigid. Theprotective layer 208 is configured to depress or otherwise cushion the inactive surface, i.e. thebottom surface 108, of theintegrated circuit 102 when the inactive surface is compressed onto theprotective layer 208, as described below. - The
encapsulant 112 may be a molding compound or a molding resin. Theencapsulant 112 may be in a liquid or a powder form. Themold chase 200 may be formed of metal and is configured to heat the powder to a liquid form. If the encapsulant is initially liquid, themold chase 200 is configured to maintain the liquid at a specific temperature in preparation for application to theICs 102. For example, theliquid encapsulant 112 may be kept at a temperature of 120 to 150 degrees Celsius. Additionally, the encapsulant may be used that is liquid at lower temperature and subsequently form crosslinks at higher temperatures. The crosslinks may cause the encapsulant to withstand more heat after initial solidification so that the encapsulant does not re-melt if theIC 102 operates at a temperature higher than 120 degrees Celsius. -
FIG. 7B illustrates the encapsulant in a molten form, evenly disbursed across theentire mold chase 200. Theprotective layer 208, which may be plastic, completely covers all interior surfaces of themold chase 200 including top and side surfaces ofwalls protective layer 208 prevents theICs 102 from contacting the hard metal surfaces of themold chase 200. In one embodiment, theprotective layer 208 is 100 microns thick. -
FIG. 7C illustrates the compressive molding of theencapsulant 112 around the side surfaces 110 of theICs 102. Thebacking 304 may be applied to acarrier layer 306 before or after theICs 102 are arranged on thesurface 302. As mentioned above, thebacking 304 may be an adhesive tape that is elastic or otherwise flexible. The active surface of the integrated circuit, i.e., thetop surface 106, is positioned on thebacking 304. Thecarrier layer 306 may be a plexiglass plate and may provide support for the backing. In addition, thecarrier layer 306 allows for transport of theICs 102 to themold chase 200. Thecarrier layer 306 allows for thebacking 304 andICs 102 to be turned over so that the bottom surfaces 108 of theICs 102 enter theencapsulant 112 in themold chase 200 first. - A portion of the
backing 304 and thecarrier 306 extend past theexterior boundary 110 of theoutermost IC 102 so that when turned over the portion rests on theprotective layer 208 over the top surface of thewalls walls ICs 102 so that little or no encapsulant covers thebottom surface 108 of theIC 102. A compressive force is applied with acompressive member 210. Thecompressive member 210 is sized and shaped to correspond to themold chase 200 and is configured to hold thecarrier 306 by vacuum suction. During compression, themold chase 200 is under pressure to remove air. Theencapsulant 112 wicks around the side surfaces 110 of theICs 102 as the compressive member presses down and the air is removed. Theencapsulant 112 covers all of the side surfaces 110 of the ICs and is substantially the same height as the ICs. Theprotective layer 208 protects theIC 102 from any damage or scratching that may be caused by the compression. It also absorbs some of the compression from thefluid resin 112, thus reducing the amount of stress placed on thedie 102 during the molding process. - As the
compressive member 210 presses the carrier and the integrated circuit into themold chase 200, the integrated circuit is cushioned by the backing 304 on thetop surface 106 and by theprotective layer 208 on thebottom surface 108. The integrated circuit experiences non-compressive forces of theliquid encapsulant 112 only on thesides 110. Liquid is non-compressable and by having thebacking 304 andlayer 208 present, compressive forces on the sides of the die are reduced or eliminated. This significantly reduces the amount of compressive stress experienced by the integrated circuit, which in turn significantly reduces the problems of warpage during heating and cooling of the packaged integrated circuit. Further as thehot resin 112 cools to form a solid, stress from the effects of difference in CTE are greatly reduced. - In order to avoid
excess encapsulant 112 in the mold chase and thereforeexcess encapsulant 112 over thebackside 108 of theIC 102, the desired weight of the encapsulant is calculated, then weighed as it is put in the mold. Toomuch encapsulant 112 prevents themold chase 200 andcompressive member 210 from pressing down the desired amount and causes the final thickness of the encapsulant to be higher, so this is avoided. - Further processing steps may also be carried out. For example, the encapsulant may be heat-treated, cold-treated or otherwise processed in order to change the chemical or physical characteristics of the
encapsulant 112. In one embodiment, theencapsulant 112 is cured in some manner. In other embodiments, other manufacturing processes for forming the layer ofencapsulant 112 may be used. - The piece of
tape 304 may then be removed, as illustrated inFIG. 8 , to leave what is effectively an array ofintegrated circuits 102 encased in the layer ofencapsulant 112. As described above, thetop surface 106 of theintegrated circuit 102 may have been facing towards thetape 304. As oriented inFIG. 8 , thetop surface 106 of theintegrated circuit 102 is facing the top of the drawing. Upon removing the piece oftape 304, in one embodiment, thetop surface 106 and thebottom surface 108 of theintegrated circuit 102 are both exposed, and the layer ofencapsulant 112 substantially covers fourside surfaces 110 of theintegrated circuit 102. - In one embodiment, as illustrated in
FIG. 9 , a firstdielectric layer 118 may be formed extending at least partially over thetop surface 106 of theintegrated circuit 102. Thefirst dielectric layer 118 may be formed to include at least one bond pad via 122 through which at least a portion of a bond pad of theintegrated circuit 102 is exposed. These bond pad vias 122 may enable subsequent electrical connections to be formed between the bond pads of theintegrated circuit 102 and one or more redistributed bond pads. - As described above, the
first dielectric layer 118 may comprise any of a variety of dielectric materials. In one embodiment, thefirst dielectric layer 118 comprises a photosensitive polymer, such as polyimide, polybenzoxazole, or solder resist. - The
first dielectric layer 118 may also be deposited and then patterned to form the bond pad vias 122 by any of a variety of processes. If thefirst dielectric layer 118 comprises a photosensitive polymer, the photosensitive polymer may first be coated over the layer ofencapsulant 112 andintegrated circuit 102. After this coating, in some embodiments, thefirst dielectric layer 118 is planarized. Portions of thefirst dielectric layer 118 may then be exposed to light (e.g., to ultraviolet light) to create a desired patterning in thislayer 118. After the light exposure, the exposed portions of thefirst dielectric layer 118 may then be removed by application of a developer solvent if a positive photosensitive polymer is used, or the unexposed portions may be removed if a negative photosensitive polymer is used. Of course, in other embodiments, other patterning processes may be used. For example, a separate photoresist layer may be deposited on top of thefirst dielectric layer 118 in order to define and then transfer a desired pattern to thefirst dielectric layer 118. - Additional chemical, physical or thermal processing may be carried out to cure or harden the
first dielectric layer 118. For example, the partially formed fan-outwafer level packaging 100 may be baked to cure thefirst dielectric layer 118. - As illustrated in
FIG. 9 , aredistribution layer 116 configured to electrically couple the bond pad of theintegrated circuit 102 to a redistributed bond pad may also be formed. Theredistribution layer 116 may comprise any of a variety of electrically conductive materials, as discussed above. As illustrated, theredistribution layer 116 may be formed over at least a portion of thefirst dielectric layer 118 and may fill at least partially the bond pad via 122. Thus, theredistribution layer 116 may create electrical connections between the bond pads of theintegrated circuit 102 and one or more redistributed bond pads through thebond pad vias 122. - In one embodiment, after the
first dielectric layer 118 has been formed, a seed layer (not shown) may first be sputtered over thefirst dielectric layer 118. The seed layer may comprise a metallic thin film, such as copper. This seed layer may thus extend over the entire exposed surface of the partially formed fan-outwafer level packaging 100. A patterned layer may then be formed over the seed layer using photolithography. Any of a variety of photolithographic techniques may be used to form such a patterned layer over the seed layer. The patterned layer may comprise, for example, photoresist material. The patterned layer may leave portions of the seed layer exposed in a pattern that will eventually define the pattern of theredistribution layer 116. At least a portion of the seed layer exposed through the patterned layer may then be plated to form theredistribution layer 116. For example, electrochemical plating or electroless plating may be performed to create acopper redistribution layer 116. The patterned layer may then be removed, and the remaining portions of the seed layer that were not plated may also be removed. Any of a variety of chemical or physical processes, such as wet etching, may be used to remove these layers, leaving thepatterned redistribution layer 116. Of course, in other embodiments, other techniques for forming apatterned redistribution layer 116 may be used. - As illustrated in
FIG. 10 , once theredistribution layer 116 has been formed, asecond dielectric layer 120 may be formed extending at least partially over theredistribution layer 116 and including at least one redistribution via 124 through which at least a portion of theredistribution layer 116 is exposed. These redistribution vias 124 may define the locations for one or more redistributed bond pads. As described above, in one embodiment, theredistribution layer 116 may itself define the redistributed bond pads. In other embodiments, a redistributed bond pad may be formed at least partially within a corresponding redistribution via 124, as described in greater detail below. - As described above, the
second dielectric layer 120 may comprise any of a variety of dielectric materials. In one embodiment, thesecond dielectric layer 120 and thefirst dielectric layer 118 comprise the same material. For example, thesecond dielectric layer 120 may comprise a photosensitive polymer, such as polyimide, polybenzoxazole or solder resist. - The
second dielectric layer 120 may be deposited and then patterned to form the redistribution vias 124 in a variety of ways. If thesecond dielectric layer 120 comprises a photosensitive polymer, the photosensitive polymer may first be coated over theredistribution layer 116 and exposed portions of thefirst dielectric layer 118. After this coating, in some embodiments, thesecond dielectric layer 120 is planarized. Portions of thesecond dielectric layer 120 may then be exposed to light (e.g., to ultraviolet light) to create the desired patterning in thislayer 120. After the light exposure, the exposed portions of thesecond dielectric layer 120 may then be removed by application of a developer solvent if a positive photosensitive polymer is used, or the unexposed portions may be removed if a negative photosensitive polymer is used. Of course, in other embodiments, other patterning processes may be used. For example, a separate photoresist layer may be deposited on top of thesecond dielectric layer 120 in order to define and then transfer a desired pattern to thesecond dielectric layer 120. - Additional chemical, physical or thermal processing may be carried out to cure or harden the
second dielectric layer 120. For example, the partially formed fan-outwafer level packaging 100 may be baked to cure thesecond dielectric layer 120. -
Bumps 104 may then be formed at the redistributed bond pad, as illustrated inFIG. 11 . Thebumps 104 may comprise any of a variety of conductive materials, as described above. In one embodiment, thebumps 104 may comprise lead-free bumps, although in other embodiments leaded bumps may be used. - In one embodiment, the redistributed bond pad may simply be defined by the portions of the
redistribution layer 116 exposed through theredistribution vias 124, as illustrated inFIG. 11 . In such an embodiment, thebumps 104 may be formed by conventional ball bonding techniques in direct contact with theredistribution layer 116. Thus, thebumps 104 may be formed on the partially formed fan-outwafer level packaging 100 to form the completed fan-outwafer level packaging 100 ofFIG. 4 . - In other embodiments, after forming the
second dielectric layer 120, a redistributed bond pad may be formed at least partially within the redistribution via 124. Such a redistributed bond pad may comprise an under-bump-metallurgy layer configured to facilitate the electrical connection formed between thebump 104 and theredistribution layer 116. This redistributed bond pad may be formed by a variety of processes. In one embodiment, the redistributed bond pad may be formed by sputtering a compound of either: (a) titanium, nickel and copper, or (b) aluminum, nickel and copper. The sputtered compound may then be plated with a compound of either: (a) titanium and copper, (b) titanium, tungsten and copper, or (c) chromium and copper. In another embodiment, the redistributed bond pad may be formed by plating the exposedredistribution layer 116 with at least one of: (a) copper, (b) nickel, or (c) copper and nickel. - After the
bump 104 is connected to theredistribution layer 116, the bottom surface, i.e., the backside of theIC 102 is thinned and planarized.FIG. 12 illustrates planarization of theICs 102. In one embodiment, portions of theencapsulant layer 112 and the inactive region of theintegrated circuit 102 that is exposed or covered by a thin layer of encapsulant is ground away leaving 450 microns of the ICs. The vertical dotted lines illustrate where a die cutter or laser may singulate theICs 102. -
FIG. 13 illustrates an alternative embodiment, where abackside coating 130 protects thebottom surface 108 of theICs 102 prior to singulation. Thebackside coating 130 may be an epoxy or other material suitable for protecting thebottom surface 108 of the IC from damage. Additionally or alternatively, the backside coating may have a similar coefficient of thermal expansion as the silicon of theIC 102. Thelayer 130 can be thin, so that if it has a CTE different from thedie 102, there is little to no additional stress put on thedie 102 when it goes through heating and cooling cycles. Another way to achieve this is to have the same CTE for both materials, while yet another way is to have no layer over theback side 108. Usually, a prior art die would have height h between 800 and 2000 microns of resin above the bottom surface of the die (seeFIG. 1 ). In the standard packing of the prior art, a resin height h of 1000 microns is common. When the package is repeatedly heated and cooled, this huge bulk of resin, having a different CTE than thedie 102, will put repeated stress on the die. On the other hand, one embodiment of the present invention has no resin on the back side of the die, avoiding the issue completely. In some embodiments, a thin layer of material under 120 microns and preferably in the range of about 40 to 90 microns ofmaterial 130 is on theback side 108 of the die, with 80 microns being preferred. - The
material 130 can be a type of material having a CTE that is closer to that of the die than the encapsulatingresin 112, thus providing even less stress. It can also be an epoxy, a polymer, or other material which, even though the CTE is different from the die, the height “h” is in the range of about 80 to 100 microns, thus not providing large stress on the die during heating and cooling cycles. - The completed fan-out
wafer level packaging 100 is illustrated inFIG. 4 . After completing the processing acts described above upon a plurality of contiguous packaging, the resulting wafer may be tested and then singulated to form the individual fan-out wafer level packaging 100 (e.g., via dicing or laser-cutting), as shown inFIGS. 12 and 13 . In other embodiments, thepackaging 100 may have been singulated at an earlier stage in the process. - In one embodiment, the fan-out
wafer level packaging 100 may be coupled to one or more additional chip packages or electronic devices via thebumps 104. - The foregoing detailed description has set forth various embodiments of the devices and/or processes via the use of block diagrams, schematics, and examples. Insofar as such block diagrams, schematics, and examples contain one or more functions and/or operations, it will be understood by those skilled in the art that each function and/or operation within such block diagrams, flowcharts, or examples can be implemented, individually and/or collectively, by a wide range of hardware, software, firmware, or virtually any combination thereof. In one embodiment, the present subject matter may be implemented via Application Specific Integrated Circuits (ASICs). However, those skilled in the art will recognize that the embodiments disclosed herein, in whole or in part, can be equivalently implemented in standard integrated circuits, as one or more programs executed by one or more processors, as one or more programs executed by one or more controllers (e.g., microcontrollers), as firmware, or as virtually any combination thereof, and that designing the circuitry and/or writing the code for the software and or firmware would be well within the skill of one of ordinary skill in the art in light of this disclosure.
- When logic is implemented as software and stored in memory, one skilled in the art will appreciate that logic or information can be stored on any computer readable storage medium for use by or in connection with any processor-related system or method. In the context of this document, a memory is a computer readable storage medium that is an electronic, magnetic, optical, or other physical device or means that contains or stores a computer and/or processor program and/or data or information. Logic and/or the information can be embodied in any computer readable storage medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions associated with logic and/or information.
- The various embodiments described above can be combined to provide further embodiments. From the foregoing it will be appreciated that, although specific embodiments have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the teachings. Accordingly, the claims are not limited by the disclosed embodiments.
Claims (24)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/495,734 US20100167471A1 (en) | 2008-12-30 | 2009-06-30 | Reducing warpage for fan-out wafer level packaging |
US13/488,276 US9012269B2 (en) | 2008-12-30 | 2012-06-04 | Reducing warpage for fan-out wafer level packaging |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14144908P | 2008-12-30 | 2008-12-30 | |
US12/495,734 US20100167471A1 (en) | 2008-12-30 | 2009-06-30 | Reducing warpage for fan-out wafer level packaging |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/488,276 Division US9012269B2 (en) | 2008-12-30 | 2012-06-04 | Reducing warpage for fan-out wafer level packaging |
Publications (1)
Publication Number | Publication Date |
---|---|
US20100167471A1 true US20100167471A1 (en) | 2010-07-01 |
Family
ID=42285445
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/495,734 Abandoned US20100167471A1 (en) | 2008-12-30 | 2009-06-30 | Reducing warpage for fan-out wafer level packaging |
US13/488,276 Active 2029-08-02 US9012269B2 (en) | 2008-12-30 | 2012-06-04 | Reducing warpage for fan-out wafer level packaging |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/488,276 Active 2029-08-02 US9012269B2 (en) | 2008-12-30 | 2012-06-04 | Reducing warpage for fan-out wafer level packaging |
Country Status (1)
Country | Link |
---|---|
US (2) | US20100167471A1 (en) |
Cited By (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100252919A1 (en) * | 2009-04-07 | 2010-10-07 | Freescale Semiconductor, Inc. | Electronic device and method of packaging an electronic device |
US20110156239A1 (en) * | 2009-12-29 | 2011-06-30 | Stmicroelectronics Asia Pacific Pte Ltd. | Method for manufacturing a fan-out embedded panel level package |
US20110233766A1 (en) * | 2010-03-25 | 2011-09-29 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming a Dual UBM Structure for Lead Free Bump Connections |
KR101227735B1 (en) | 2011-04-28 | 2013-01-29 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and fabricating method thereof |
CN102956547A (en) * | 2011-08-25 | 2013-03-06 | 南茂科技股份有限公司 | Semiconductor packaging structure and manufacturing method thereof |
US8502367B2 (en) | 2010-09-29 | 2013-08-06 | Stmicroelectronics Pte Ltd. | Wafer-level packaging method using composite material as a base |
CN103579022A (en) * | 2012-08-03 | 2014-02-12 | 矽品精密工业股份有限公司 | Structure and manufacturing method of semiconductor package |
US8765527B1 (en) | 2013-06-13 | 2014-07-01 | Freescale Semiconductor, Inc. | Semiconductor device with redistributed contacts |
US8922021B2 (en) | 2011-12-30 | 2014-12-30 | Deca Technologies Inc. | Die up fully molded fan-out wafer level packaging |
US20150093856A1 (en) * | 2013-10-02 | 2015-04-02 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method thereof |
US9177926B2 (en) | 2011-12-30 | 2015-11-03 | Deca Technologies Inc | Semiconductor device and method comprising thickened redistribution layers |
US9337086B2 (en) | 2011-12-30 | 2016-05-10 | Deca Technologies Inc. | Die up fully molded fan-out wafer level packaging |
US9385102B2 (en) | 2012-09-28 | 2016-07-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package |
JP5989929B1 (en) * | 2016-02-17 | 2016-09-07 | 太陽インキ製造株式会社 | Curable resin composition |
US9576919B2 (en) | 2011-12-30 | 2017-02-21 | Deca Technologies Inc. | Semiconductor device and method comprising redistribution layers |
WO2017043375A1 (en) * | 2015-09-08 | 2017-03-16 | 東レ株式会社 | Photosensitive resin composition, photosensitive sheet, semiconductor device, and method for manufacturing semiconductor device |
US9613830B2 (en) | 2011-12-30 | 2017-04-04 | Deca Technologies Inc. | Fully molded peripheral package on package device |
WO2017073481A1 (en) * | 2015-10-28 | 2017-05-04 | 東レ株式会社 | Positive photosensitive resin composition, photosensitive sheet, cured film, interlayer insulating film, semiconductor protective film, method for manufacturing semiconductor device, semiconductor electronic component and semiconductor device |
US9831170B2 (en) | 2011-12-30 | 2017-11-28 | Deca Technologies, Inc. | Fully molded miniaturized semiconductor module |
US10050004B2 (en) | 2015-11-20 | 2018-08-14 | Deca Technologies Inc. | Fully molded peripheral package on package device |
JP2018170500A (en) * | 2017-03-29 | 2018-11-01 | 太陽インキ製造株式会社 | Warp correction material and manufacturing method of fan-out type wafer level package |
US10373870B2 (en) | 2010-02-16 | 2019-08-06 | Deca Technologies Inc. | Semiconductor device and method of packaging |
CN111146159A (en) * | 2018-11-06 | 2020-05-12 | 三星电子株式会社 | Semiconductor package |
US10672624B2 (en) | 2011-12-30 | 2020-06-02 | Deca Technologies Inc. | Method of making fully molded peripheral package on package device |
US11056453B2 (en) | 2019-06-18 | 2021-07-06 | Deca Technologies Usa, Inc. | Stackable fully molded semiconductor structure with vertical interconnects |
US11462440B2 (en) * | 2017-07-25 | 2022-10-04 | Semiconductor Manufacturing International (Shanghai) Corporation | Packaging structure |
US20230150199A1 (en) * | 2017-05-01 | 2023-05-18 | Hewlett-Packard Development Company, L.P. | Molded panels |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9355967B2 (en) | 2013-06-24 | 2016-05-31 | Qualcomm Incorporated | Stress compensation patterning |
WO2016044179A2 (en) | 2014-09-15 | 2016-03-24 | Invensas Corporation | Electronic structures strengthened by porous and non-porous layers, and methods of fabrication |
KR102327142B1 (en) | 2015-06-11 | 2021-11-16 | 삼성전자주식회사 | Wafer Level Package |
TWI622142B (en) | 2016-11-07 | 2018-04-21 | 財團法人工業技術研究院 | Chip package and chip packaging method |
CN109103167B (en) | 2017-06-20 | 2020-11-03 | 晟碟半导体(上海)有限公司 | Heterogeneous fan out structure for memory devices |
US10832987B2 (en) | 2018-03-24 | 2020-11-10 | International Business Machines Corporation | Managing thermal warpage of a laminate |
US10629554B2 (en) | 2018-04-13 | 2020-04-21 | Powertech Technology Inc. | Package structure and manufacturing method thereof |
US11421316B2 (en) | 2018-10-26 | 2022-08-23 | Applied Materials, Inc. | Methods and apparatus for controlling warpage in wafer level packaging processes |
TWI718801B (en) * | 2019-12-06 | 2021-02-11 | 矽品精密工業股份有限公司 | Electronic package manufacturing method |
CN111540750B (en) * | 2020-04-27 | 2021-07-06 | 长江存储科技有限责任公司 | Method for manufacturing 3D memory device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6087202A (en) * | 1997-06-03 | 2000-07-11 | Stmicroelectronics S.A. | Process for manufacturing semiconductor packages comprising an integrated circuit |
US6423570B1 (en) * | 2000-10-18 | 2002-07-23 | Intel Corporation | Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby |
US20040046254A1 (en) * | 2001-12-31 | 2004-03-11 | Mou-Shiung Lin | Integrated chip package structure using metal substrate and method of manufacturing the same |
US6706553B2 (en) * | 2001-03-26 | 2004-03-16 | Intel Corporation | Dispensing process for fabrication of microelectronic packages |
US20050148160A1 (en) * | 2002-03-06 | 2005-07-07 | Farnworth Warren M. | Encapsulated semiconductor components and methods of fabrication |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4612601A (en) | 1983-11-30 | 1986-09-16 | Nec Corporation | Heat dissipative integrated circuit chip package |
US5288944A (en) | 1992-02-18 | 1994-02-22 | International Business Machines, Inc. | Pinned ceramic chip carrier |
US6270019B1 (en) | 1999-10-29 | 2001-08-07 | Nordson Corporation | Apparatus and method for dispensing liquid material |
US6506681B2 (en) * | 2000-12-06 | 2003-01-14 | Micron Technology, Inc. | Thin flip—chip method |
TW584950B (en) | 2001-12-31 | 2004-04-21 | Megic Corp | Chip packaging structure and process thereof |
GB2404280B (en) | 2003-07-03 | 2006-09-27 | Xsil Technology Ltd | Die bonding |
US6930378B1 (en) * | 2003-11-10 | 2005-08-16 | Amkor Technology, Inc. | Stacked semiconductor die assembly having at least one support |
US7459781B2 (en) | 2003-12-03 | 2008-12-02 | Wen-Kun Yang | Fan out type wafer level package structure and method of the same |
US20050275081A1 (en) * | 2004-06-12 | 2005-12-15 | Roger Chang | Embedded chip semiconductor having dual electronic connection faces |
US7645635B2 (en) | 2004-08-16 | 2010-01-12 | Micron Technology, Inc. | Frame structure and semiconductor attach process for use therewith for fabrication of image sensor packages and the like, and resulting packages |
US7658988B2 (en) | 2006-04-03 | 2010-02-09 | E. I. Du Pont De Nemours And Company | Printed circuits prepared from filled epoxy compositions |
US8609471B2 (en) * | 2008-02-29 | 2013-12-17 | Freescale Semiconductor, Inc. | Packaging an integrated circuit die using compression molding |
TWI387074B (en) | 2008-06-05 | 2013-02-21 | Chipmos Technologies Inc | Chip stacked structure and the forming method |
US8106504B2 (en) | 2008-09-25 | 2012-01-31 | King Dragon International Inc. | Stacking package structure with chip embedded inside and die having through silicon via and method of the same |
KR20100071485A (en) | 2008-12-19 | 2010-06-29 | 삼성전기주식회사 | Manufacturing method of wafer level package |
US8378383B2 (en) | 2009-03-25 | 2013-02-19 | Stats Chippac, Ltd. | Semiconductor device and method of forming a shielding layer between stacked semiconductor die |
US20110156239A1 (en) | 2009-12-29 | 2011-06-30 | Stmicroelectronics Asia Pacific Pte Ltd. | Method for manufacturing a fan-out embedded panel level package |
US8558392B2 (en) | 2010-05-14 | 2013-10-15 | Stats Chippac, Ltd. | Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant |
US8502367B2 (en) | 2010-09-29 | 2013-08-06 | Stmicroelectronics Pte Ltd. | Wafer-level packaging method using composite material as a base |
-
2009
- 2009-06-30 US US12/495,734 patent/US20100167471A1/en not_active Abandoned
-
2012
- 2012-06-04 US US13/488,276 patent/US9012269B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6087202A (en) * | 1997-06-03 | 2000-07-11 | Stmicroelectronics S.A. | Process for manufacturing semiconductor packages comprising an integrated circuit |
US6423570B1 (en) * | 2000-10-18 | 2002-07-23 | Intel Corporation | Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby |
US6706553B2 (en) * | 2001-03-26 | 2004-03-16 | Intel Corporation | Dispensing process for fabrication of microelectronic packages |
US20040046254A1 (en) * | 2001-12-31 | 2004-03-11 | Mou-Shiung Lin | Integrated chip package structure using metal substrate and method of manufacturing the same |
US20050148160A1 (en) * | 2002-03-06 | 2005-07-07 | Farnworth Warren M. | Encapsulated semiconductor components and methods of fabrication |
Cited By (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100252919A1 (en) * | 2009-04-07 | 2010-10-07 | Freescale Semiconductor, Inc. | Electronic device and method of packaging an electronic device |
US9054111B2 (en) * | 2009-04-07 | 2015-06-09 | Freescale Semiconductor, Inc. | Electronic device and method of packaging an electronic device |
US20110156239A1 (en) * | 2009-12-29 | 2011-06-30 | Stmicroelectronics Asia Pacific Pte Ltd. | Method for manufacturing a fan-out embedded panel level package |
US10373870B2 (en) | 2010-02-16 | 2019-08-06 | Deca Technologies Inc. | Semiconductor device and method of packaging |
US8759209B2 (en) * | 2010-03-25 | 2014-06-24 | Stats Chippac, Ltd. | Semiconductor device and method of forming a dual UBM structure for lead free bump connections |
US20110233766A1 (en) * | 2010-03-25 | 2011-09-29 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming a Dual UBM Structure for Lead Free Bump Connections |
US9711438B2 (en) | 2010-03-25 | 2017-07-18 | STATS ChipPAC, Pte. Ltd. | Semiconductor device and method of forming a dual UBM structure for lead free bump connections |
US8502367B2 (en) | 2010-09-29 | 2013-08-06 | Stmicroelectronics Pte Ltd. | Wafer-level packaging method using composite material as a base |
KR101227735B1 (en) | 2011-04-28 | 2013-01-29 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and fabricating method thereof |
US9196553B2 (en) | 2011-08-25 | 2015-11-24 | Chipmos Technologies Inc. | Semiconductor package structure and manufacturing method thereof |
CN102956547A (en) * | 2011-08-25 | 2013-03-06 | 南茂科技股份有限公司 | Semiconductor packaging structure and manufacturing method thereof |
US10672624B2 (en) | 2011-12-30 | 2020-06-02 | Deca Technologies Inc. | Method of making fully molded peripheral package on package device |
US8922021B2 (en) | 2011-12-30 | 2014-12-30 | Deca Technologies Inc. | Die up fully molded fan-out wafer level packaging |
US9613830B2 (en) | 2011-12-30 | 2017-04-04 | Deca Technologies Inc. | Fully molded peripheral package on package device |
US9177926B2 (en) | 2011-12-30 | 2015-11-03 | Deca Technologies Inc | Semiconductor device and method comprising thickened redistribution layers |
US10373902B2 (en) | 2011-12-30 | 2019-08-06 | Deca Technologies Inc. | Fully molded miniaturized semiconductor module |
US9337086B2 (en) | 2011-12-30 | 2016-05-10 | Deca Technologies Inc. | Die up fully molded fan-out wafer level packaging |
US9831170B2 (en) | 2011-12-30 | 2017-11-28 | Deca Technologies, Inc. | Fully molded miniaturized semiconductor module |
US9576919B2 (en) | 2011-12-30 | 2017-02-21 | Deca Technologies Inc. | Semiconductor device and method comprising redistribution layers |
CN103579022A (en) * | 2012-08-03 | 2014-02-12 | 矽品精密工业股份有限公司 | Structure and manufacturing method of semiconductor package |
US9385102B2 (en) | 2012-09-28 | 2016-07-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package |
US10297518B2 (en) * | 2012-09-28 | 2019-05-21 | Stats Chippac, Ltd. | Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package |
US8765527B1 (en) | 2013-06-13 | 2014-07-01 | Freescale Semiconductor, Inc. | Semiconductor device with redistributed contacts |
US9209046B2 (en) * | 2013-10-02 | 2015-12-08 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method thereof |
US20150093856A1 (en) * | 2013-10-02 | 2015-04-02 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method thereof |
WO2017043375A1 (en) * | 2015-09-08 | 2017-03-16 | 東レ株式会社 | Photosensitive resin composition, photosensitive sheet, semiconductor device, and method for manufacturing semiconductor device |
WO2017073481A1 (en) * | 2015-10-28 | 2017-05-04 | 東レ株式会社 | Positive photosensitive resin composition, photosensitive sheet, cured film, interlayer insulating film, semiconductor protective film, method for manufacturing semiconductor device, semiconductor electronic component and semiconductor device |
US10050004B2 (en) | 2015-11-20 | 2018-08-14 | Deca Technologies Inc. | Fully molded peripheral package on package device |
JP5989929B1 (en) * | 2016-02-17 | 2016-09-07 | 太陽インキ製造株式会社 | Curable resin composition |
WO2017141818A1 (en) * | 2016-02-17 | 2017-08-24 | 太陽インキ製造株式会社 | Curable resin composition and fan out type wafer level package |
JP2018170500A (en) * | 2017-03-29 | 2018-11-01 | 太陽インキ製造株式会社 | Warp correction material and manufacturing method of fan-out type wafer level package |
US20230150199A1 (en) * | 2017-05-01 | 2023-05-18 | Hewlett-Packard Development Company, L.P. | Molded panels |
US11462440B2 (en) * | 2017-07-25 | 2022-10-04 | Semiconductor Manufacturing International (Shanghai) Corporation | Packaging structure |
CN111146159A (en) * | 2018-11-06 | 2020-05-12 | 三星电子株式会社 | Semiconductor package |
US11056453B2 (en) | 2019-06-18 | 2021-07-06 | Deca Technologies Usa, Inc. | Stackable fully molded semiconductor structure with vertical interconnects |
Also Published As
Publication number | Publication date |
---|---|
US9012269B2 (en) | 2015-04-21 |
US20120244664A1 (en) | 2012-09-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9012269B2 (en) | Reducing warpage for fan-out wafer level packaging | |
US11901332B2 (en) | Semiconductor device and manufacturing method thereof | |
KR101387706B1 (en) | Semiconductor Package, Method of Fabricating the Same and Electronic Device Including the Same | |
US10276545B1 (en) | Semiconductor package and manufacturing method thereof | |
TWI757587B (en) | Semiconductor device | |
CN113380727A (en) | Microelectronic device including dummy die | |
JP5112275B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
KR20190053235A (en) | Wafer level package and method | |
US10978408B2 (en) | Semiconductor package and manufacturing method thereof | |
KR20050063700A (en) | A manufacturing method of a semiconductor device | |
US11081415B2 (en) | Method for manufacturing electronic package | |
US11791266B2 (en) | Chip scale package structure and method of forming the same | |
US11842902B2 (en) | Semiconductor package with alignment mark and manufacturing method thereof | |
TWI550783B (en) | Fabrication method of electronic package and electronic package structure | |
US11855023B2 (en) | Wafer level fan out semiconductor device and manufacturing method thereof | |
TWI421956B (en) | Chip-sized package and fabrication method thereof | |
CN107154391B (en) | Semiconductor packages | |
US20230073399A1 (en) | Chip scale package structure and method of forming the same | |
US6312972B1 (en) | Pre-bond encapsulation of area array terminated chip and wafer scale packages | |
US10825783B2 (en) | Semiconductor packages and devices | |
TW201701429A (en) | Wafer level package and fabrication method thereof | |
US11574820B2 (en) | Semiconductor devices with flexible reinforcement structure | |
US8035220B2 (en) | Semiconductor packaging device | |
CN209804637U (en) | Semiconductor packaging structure | |
JP2003124431A (en) | Wafer-form sheet, a chip-form electronic part, and their manufacturing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: STMICROELECTRONICS ASIA PACIFIC PTE, LTD.,SINGAPOR Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JIN, YONGGANG;BARATON, XAVIER;CHE, FAXING;SIGNING DATES FROM 20090731 TO 20090916;REEL/FRAME:023246/0866 |
|
AS | Assignment |
Owner name: STMICROELECTRONICS PTE LTD., SINGAPORE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:STMICROELECTRONICS ASIA PACIFIC PTE LTD.;REEL/FRAME:027110/0638 Effective date: 20111004 Owner name: STMICROELECTRONICS PTE LTD., SINGAPORE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JIN, YONGGANG;BARATON, XAVIER;CHE, FAXING;SIGNING DATES FROM 20110818 TO 20110831;REEL/FRAME:027110/0629 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |