Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20100095094 A1
Publication typeApplication
Application numberUS 12/640,201
Publication date15 Apr 2010
Filing date17 Dec 2009
Priority date20 Jun 2001
Also published asEP1402382A2, EP1402382B1, EP2224330A1, EP2224330B1, US7657877, US20040243984, WO2002103532A2, WO2002103532A3
Publication number12640201, 640201, US 2010/0095094 A1, US 2010/095094 A1, US 20100095094 A1, US 20100095094A1, US 2010095094 A1, US 2010095094A1, US-A1-20100095094, US-A1-2010095094, US2010/0095094A1, US2010/095094A1, US20100095094 A1, US20100095094A1, US2010095094 A1, US2010095094A1
InventorsMartin Vorbach, Armin Nückel, Frank May, Markus Weinhardt, Joao Manuel Paiva Cardoso
Original AssigneeMartin Vorbach, Nueckel Armin, Frank May, Markus Weinhardt, Joao Manuel Paiva Cardoso
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for processing data
US 20100095094 A1
Abstract
A method and device for translating a program to a system including at least one first processor and a reconfigurable unit. Code portions of the program which are suitable for the reconfigurable unit are determined. The remaining code of the program is extracted and/or separated for processing by the first processor.
Images(8)
Previous page
Next page
Claims(12)
1. A method for translating a program for a system including at least one first processor and a reconfigurable unit, the method comprising:
determining from the program, code portions of the program suitable for the reconfigurable unit; and
at least one of extracting and separating, remaining code of the program for processing by the first processor.
2. The method as recited in claim 1, further comprising:
appending interface code to the code portions extracted for the first processor to permit communication between the first processor and the reconfigurable unit according to the system.
3. The method as recited in claim 1, further comprising:
appending interface to the code portions extracted for the reconfigurable unit so that communication is enabled between the first processor and the reconfigurable unit according to the system.
4. The method as recited in claim 1, wherein the determining step includes determining the code portions based on automated analyses.
5. The method as recited in claim 1, wherein the program includes instructions defining the code portions to be extracted, and wherein the method further comprises automatically analyzing the instructions.
6. The method as recited in claim 1, wherein the code portions to be extracted are determined based on calls of subprograms.
7. The method as recited in claim 1, further comprising:
providing an interface code which provides at least one of memory linkage, register linkage, and linkage via a network.
8. The method as recited in claim 1, further comprising:
analyzing at least one of the extracted code portions and results achievable with a given extraction; and
restarting an extraction with new improved parameters based on the analysis.
9. The method as recited in claim 1, further comprising:
appending control code to the extracted code for at least one of management, control, and communication of the development system.
10. The method as recited in claim 1, wherein the first processor has a conventional processor architecture, the architecture including at least one of a von-Neumann architecture, Harvard architecture, controller, CISC processor, RISC processor, VLIW processor, or DSP processor.
11. The method as recited in claim 1, wherein the remaining code is extracted so that it is translatable via any ordinary unmodified compiler that is suitable for the first processor.
12. A device for data processing, comprising:
at least one conventional processor;
at least one reconfigurable unit; and
an arrangement configured to exchange data and status information between a conventional processor and a reconfigurable unit, the arrangement being configured so that the data and status information exchange is possible therebetween at least one of: i) during processing of one or more programs, ii) without having to interrupt data processing on the reconfigurable processor, and iii) without having to interrupt data processing on the conventional processor.
Description
    CROSS-REFERENCE TO RELATED APPLICATIONS
  • [0001]
    This application is a continuation of U.S. patent application Ser. No. 10/480,003, filed on Jun. 18, 2004, which is a national phase of International Application No. PCT/EP02/06865, filed on Jun. 20, 2002, which claims priority to German Patent Application No. DE 101 29 237.6, filed on Jun. 20, 2001, the entire contents of each of which are expressly incorporated herein by reference thereto.
  • FIELD OF THE INVENTION
  • [0002]
    The present invention relates to data processing. In particular, the present invention relates to traditional, i.e., conventional and reconfigurable processor architectures as well as methods therefor, which permit translation of a classical high-level language (PROGRAM) such as Pascal, C, C++, Java, etc., in particular onto a reconfigurable architecture. The present invention relates in particular to integration and/or close coupling of reconfigurable processors with standard processors, data exchange, and synchronization of data processing.
  • BACKGROUND INFORMATION
  • [0003]
    A conventional processor architecture (PROCESSOR) is understood in the present case to refer to sequential processors having a von Neumann architecture or a Harvard architecture, such as controllers or CISC processors, RISC processors, VLIW processors, DSP processors, etc.
  • [0004]
    The term “reconfigurable target architecture” is understood in the present case to refer to modules (VPUs) having a function and/or interconnection that is repeatedly configurable, in particular configurable without interruption during run time, in particular integrated modules having a plurality of one-dimensionally or multidimensionally arranged arithmetic and/or logic and/or analog and/or memory modules, in particular also coarse-grained modules (PAEs) which are interlinked directly or via a bus system.
  • [0005]
    The generic class of such modules includes in particular systolic arrays, neural networks, multiprocessor systems, processors having a plurality of arithmetic units and/or logic cells, interlinking and network modules such as crossbar switches as well as known modules of the generic types FPGA, DPGA and XPUTER, etc. In this connection, reference is made in particular to the following patents and patent applications: P 44 16 881.0-53, DE 197 81 412.3, DE 197 81 483.2, DE 196 54 846.2-53, DE 196 54 593.5-53, DE 197 04 044.6-53, DE 198 80 129.7, DE 198 61 088.2-53, DE 199 80 312.9, PCT/DE 00/01869, DE 100 36 627.9-33, DE 100 28 397.7, DE 101 10 530.4, DE 101 11 014.6, PCT/EP 00/10516, EP 01 102 674.7, DE 196 51 075.9-53, DE 196 54 846.2-53, DE 196 54 593.5-53, DE 197 04 728.9, DE 197 07 872.2, DE 101 39 170.6, DE 199 26 538.0, DE 101 42 904.5, DE 101 10 530.4. These are herewith incorporated to the full extent for disclosure purposes.
  • [0006]
    This system may be designed in particular as a (standard) processor or module and/or may be integrated into a semiconductor (system on chip, SoC).
  • [0007]
    Reconfigurable modules (VPUs) of different generic types (such as PACT XPP technology, Morphics, Morphosys, Chameleon) are largely incompatible with existing technical environments and programming methods.
  • [0008]
    Programs for these modules are typically incompatible with existing programs of CPUs. A considerable development expense is thus necessary for programming, e.g., in particular for modules of the generic types Morphics, Morphosys. Chameleon already integrates a standard processor (ARC) on more or less reconfigurable modules. This makes approaches for programming tools available. However, not all technical environments are suitable for the use of ARC processors; in particular there are often existing programs, code libraries, etc. for any indeterminate other CPUs.
  • [0009]
    In internal experiments it has been found that there are certain methods and program sequences which may be processed better using a reconfigurable architecture rather than a conventional processor architecture. Conversely, there are also such methods and program sequences which are better executed using a conventional processor architecture. It would be desirable to provide a sequence partitioning to permit appropriate optimization.
  • [0010]
    Conventional translation methods for reconfigurable architectures do not support any forwarding of codes to any standard compilers for generating object codes for any desired PROCESSOR. Ordinarily, the PROCESSOR is fixedly defined within the compiler.
  • [0011]
    In addition, there are no scheduling mechanisms for reconfiguring the individual configurations generated for VPUs. In particular there are no scheduling mechanisms for configuration of independently extracted portions or for individual partitions of extracted portions. Conventional corresponding translation methods are described in the dissertation Übersetzungsmethoden f{umlaut over (r)} strukturprogrammierbare Rechner [Translation Methods for Structure Programmable Computers], by Dr. Markus Weinhardt, 1997, for example.
  • [0012]
    Several conventional methods are known for partitioning array CODE e.g., João M. P. Cardoso, Compilation of Java™ Algorithms onto Reconfigurable Computing Systems with Exploitation of Operation-Level Parallelism, Ph.D. dissertation, Universidade Técnica de Lisboa (UTL), 2000.
  • [0013]
    However, these methods are not embedded into any complete compiler systems. Furthermore, these methods presuppose complete control of the reconfiguration by a host processor, which involves considerable complexity. The partitioning strategies are designed for FPGA-based systems and therefore do not correspond to any actual processor model.
  • SUMMARY
  • [0014]
    An object of the present invention is to provide a method for a commercial application.
  • [0015]
    A reconfigurable processor (VPU) is thus designed into a technical environment which has a standard processor (CPU) such as a DSP, RISC, CISC processor or a (micro)controller. The design may be accomplished according to an embodiment of the present invention in such a way that there is a simple and efficient connection. One resulting aspect is the simple programmability of the resulting system. Further use of existing programs of the CPU as well as the code compatibility and simple integration of the VPU into existing programs are taken into account.
  • [0016]
    A VPU (or a plurality of VPUs, although this need not be mentioned specifically each time) is coupled to a preferred CPU (or a plurality of CPUs, although this need not be mentioned specifically each time) so that it assumes the position and function of a coprocessor (or a plurality of coprocessors that respond optionally). This function permits a simple tie-in into existing program codes according to the pre-existing methods for working with coprocessors according to the related art.
  • [0017]
    The data exchange between the CPU and VPU according to the present invention may be accomplished by memory coupling and/or IO coupling. The CPU and VPU may share all resources; in particular embodiments, it is also possible for the CPU and VPU to jointly use only a portion of the resources and to make other resources available explicitly and/or exclusively for a CPU or VPU.
  • [0018]
    To perform a data exchange, data records and/or configurations may be copied and/or written/read in memory areas particularly provided for those purposes and/or corresponding basic addresses may be set in such a way that these point to the particular data areas.
  • [0019]
    To control the coprocessor, preferably a data record which contains the basic settings of a VPU, e.g., certain basic addresses are provided, for example. In addition, status variables may also be provided for triggering and for function control of a VPU by a CPU and for acknowledgments from a VPU to a CPU. This data record may be exchanged via a shared memory (RAM) and/or via a shared peripheral address space (IO).
  • [0020]
    For synchronization of the CPU and VPU, unilaterally or mutually acting interrupt methods (which are implemented, for example, by signal transfer over interrupt lines and/or interrupt inputs that are specifically dedicated and/or designed for this purpose) and/or the synchronization is accomplished by polling methods. Furthermore, interrupts may also be used for synchronization of data transfers and/or DMA transfers.
  • [0021]
    In an example embodiment that is particularly preferred, a VPU is started by a CPU and thereafter operates preferably independently of the application.
  • [0022]
    A preferred design in which the VPU provides its own mechanisms for loading and controlling configurations is particularly efficient. The generic type of these VPUs include, for example, PACT XPP and Chameleon. The circuits according to the present invention permit a method of operation in which the configurations of the VPU are loaded into a memory together with the program to be executed by the CPU. During execution of the program, the CPU may refer the VPU to the memory locations (e.g., by giving the addresses or pointers), each containing configurations to be executed. The VPU may then load the configurations independently and without further influence by the CPU. The execution by the CPU starts immediately or optionally by means of additional information (e.g., interrupt and/or start instruction).
  • [0023]
    In a particularly preferred expansion, the VPU may read and write data independently within a memory.
  • [0024]
    In a particularly preferred expansion, the VPU may also independently load new configurations out of the memory and may perform new configurations as needed without requiring any further influence by the CPU.
  • [0025]
    These embodiments permit extensive operation of VPUs independently of CPUs. Only a synchronization exchange between CPU and VPU, which may preferably take place bidirectionally, is provided in addition to coordinate data processing operations and/or executions of configurations.
  • [0026]
    It has also been recognized that methods of data processing may and/or should preferably be designed so that particularly suitable portions (VPU code) of the program to be translated are identified and extracted for the reconfigurable target architecture (VPU) to permit particularly efficient data processing. These portions are to be partitioned accordingly and the time sequence configuration of the individual partitions is to be controlled.
  • [0027]
    The remaining portions of the program may be translated onto a conventional processor architecture (PROCESSOR). This is preferably accomplished in such a way that these portions are output as high-level language code in a standard high-level language (e.g., ANSI C) so that an ordinary high-level language compiler (optionally pre-existing) is able to process it without difficulty.
  • [0028]
    It should also be pointed out that these methods may also be used for groups of a plurality of modules.
  • [0029]
    In particular a type of “double buffering” may be used for a particularly simple and at the same time rapid reconfiguration in which a plurality of VPUs are provided, so that a portion of the VPUs may be reconfigured at a time when another portion is computing and perhaps yet another may be inactive, for example. Data links, trigger links, status links, etc. are exchanged among a plurality of VPUs in a suitable way, and are optionally wired through addressed buses and/or multiplexers/demultiplexers according to the VPUs that are currently active and/or to be reconfigured.
  • [0030]
    One advantage of this method is that existing code which has been written for any processor, may continue to be used by involving a VPU, and no modifications or only comparatively minor modifications need be made. The modifications may also be performed incrementally, with more code being transferred gradually from the processor to the VPU. The project risk drops, and there is a significant increase in clarity. It should be pointed out that such a successive transfer of more and more tasks to the VPU, i.e., to the integral, multidimensional, partially reconfigurable and in particular coarse-grained field of elements, has a special meaning on its own and is regarded as being inventive per se because of its major advantages in system porting.
  • [0031]
    In addition, the programmer is able to work in his/her accustomed development environment and need not become adjusted to a novel and possibly foreign development environment.
  • [0032]
    A first aspect of the present invention may be seen in the fact that a PROCESSOR is connected to one or more VPUs so that an efficient exchange of information is possible, in particular in the form of data information and status information.
  • [0033]
    Importance may also be attributed to the configuration of a conventional processor and a reconfigurable processor so that exchange of data information and/or status information between same is possible during running of one or more programs and/or without having to significantly interrupt data processing on the reconfigurable processor and/or the conventional processor in particular; importance may also be attributed to the design of such a system.
  • [0034]
    For example, one or all of the following linking methods and/or means may be used:
    • a) shared memory,
    • b) network (e.g., bus systems such as PCI bus, serial buses such as Ethernet, for example),
    • c) connection to an internal register set or a plurality of internal register sets,
    • d) other memory media (hard drive, flash ROM, etc.).
  • [0039]
    In principle, the VPU and/or the CPU may also independently access the memory without the assistance of a DMA. The shared memory may also be designed as a dual port memory or a multiport memory in particular. Additional modules may be assigned to the system, and in particular reconfigurable FPGAs may be used to permit fine-grained processing of individual signals or data bits and/or to make it possible to establish flexible adaptable interfaces (e.g., various serial interfaces (V24, USB, etc.), various parallel interfaces, hard drive interfaces, Ethernet, telecommunications interfaces (a/b, TO, ISDN, DSL, etc.)).
  • [0040]
    The structure of a VPU is known, for example, from the patents and patent applications described above. Attempts to arrive at alternative module definitions have become known under the name Chameleon, for example. VPUs may be integrated into a system in various ways. For example, a connection to a host processor is possible. Depending on the method, the host processor may assume the configuration control (HOSTRECONF) (e.g., Chameleon) or there may be, for example, a dedicated unit (CT) for controlling the (re)configuration.
  • [0041]
    Accordingly, the translator according to the method described here generates the control information for the reconfiguration for a CT and/or a HOSTRECONF.
  • [0042]
    The translation principle may be embodied in such a way that by using a preprocessor, the portions that may be mapped efficiently and/or reasonably on the particular certain VPU(s) may be extracted from a PROGRAM via a PREPROCESSOR. These portions are transformed into a format suitable for VPUs (NML) and are then translated further into an object code.
  • [0043]
    The remaining code and/or the extracted code is expanded according to experience at or with respect to the location of the code portions that are missing due to the extraction, by adding an interface code which controls communication between PROCESSOR(s) and VPU(s) according to the architecture of the target system. The remaining code which has been optionally expanded may preferably be extracted. This may take place as follows, for example:
  • [0000]
    ...
    Code
    ...
    # START_EXTRACTION
    Code to be extracted
    # END_EXTRACTION
    ...
    Code
    ...
    “// START_EXTRACTION” denotes the start of a code to be extracted.
    “// END_EXTRACTION” denotes the end of a code to be extracted.
  • [0044]
    In such a case, the unit for implementation of the program in configuration codes is designed to recognize the hints and/or implementation instructions.
  • [0045]
    It is also possible for portions of the PROGRAM to be implemented directly in NML for extraction by calling NML routines and to jump to the NML routines using calls. This may take place as follows, for example:
  • [0000]
    a) NML code
    ...
    procedure EXAMPLE
    begin
    ...
    end
    ...
    b) PROGRAM code
    ...
    Code
    ...
    call EXAMPLE      // call of the NML code
    ...
    Code
    ...
  • [0046]
    In this case, the unit for implementation is designed to tie NML program portions, i.e., program portions for execution in and/or on a reconfigurable array, into a larger program.
  • [0047]
    Alternatively and/or additionally, extraction from an object-oriented class is also possible.
  • [0048]
    Macros suitable for a VPU are defined as a class in the class hierarchy of an object-oriented programming language. The macros may be characterized by annotation so that they are recognized as codes intended for a VPU and are processed further accordingly—even in higher hierarchies of the language.
  • [0049]
    Within a macro, a certain networking and/or mapping is preferably predetermined by the macro which then determines the mapping of the macro onto the VPU.
  • [0050]
    Instantiation and chaining of the class results in implementation of the function which includes a plurality of macros on the VPU. In other words, instantiation and chaining of macros define the mapping and interconnection of the individual operations of all macros on the VPU and/or the interconnection and/or data exchange between the VPU and CPU, if necessary.
  • [0051]
    The interface codes are added in instantiation. Chaining describes the detailed mapping of the class on the VPU.
  • [0052]
    A class may also be formed as a call of one or more NML routines, for example.
  • [0000]
    a) Class code
    ...
    class EXAMPLE
    begin
    ...
    end
    ...
    b) PROGRAM code
    ...
    Code
    ...
    EXAMPLE var( )       // instantiation of the class
    ...
    Code
    ...
  • [0053]
    Extraction by analysis is also possible. Portions within the PROGRAM which may be mapped efficiently and/or appropriately on the VPU are recognized using the analytical methods adapted to the particular VPU.
  • [0054]
    These portions are extracted from the PROGRAM.
  • [0055]
    An analytical method suitable for many VPUs, for example, is to create data flow graphs and/or control flow graphs from the PROGRAM. These graphs may then be analyzed automatically with regard to their possible partitioning and/or mapping onto the target VPU. In this case, the portions of the graphs generated and/or the corresponding PROGRAM PORTIONS, which may be partitioned and/or mapped sufficiently well, are extracted. To do so, a partitionability and/or mappability analysis may be performed, evaluating the particular property. Partitioning and extraction of the program portions on the VPU as well as the introduction of the interfaces provided are then performed according to this evaluation.
  • [0056]
    Reference is made here explicitly to the analytical methods described in German Patent Application DE 101 39 170.6 which may be used, for example. The aforementioned patent application is herewith incorporated to full extent for disclosure purposes.
  • [0057]
    One possible analytical method is also provided by recognition of certain data types.
  • [0058]
    Different data types are more or less suitable for processing on a VPU. For example, complex pointer arithmetics, i.e., pointer-based data addressing (pointer) is difficult to map onto a VPU, whereas arrays are very easily mappable.
  • [0059]
    Therefore, the particular suitable data types and at least essential portions of their data processing may be transferred largely automatically or manually to a VPU according to the present invention and extracted accordingly. The extraction is performed in response to the occurrence of certain data types and/or data operations.
  • [0060]
    It should be pointed out here that additional parameters assigned to the data types may provide additional information for determining the executability and/or execution performance on a VPU and therefore may also be used to a significant extent for extraction. For example, the size of the arrays to be computed plays a significant role. It is usually not worthwhile to perform computations for small arrays on a VPU because the resources needed for synchronization and data exchange between the CPU and VPU may be excessive. However, it should again be pointed out that small arrays for which computations are performed particularly frequently within a loop are nevertheless very suitable for VPUs if the loop is computed almost completely on the VPU. Large arrays, however, may usually be computed particularly efficiently on a VPU.
  • [0061]
    In addition, it should be pointed out that certain data types may be created by a specially adapted compiler or, optionally, by a user (e.g., by using TYPE in Pascal), these being particularly suitable for VPUs and data processing of which is then executed on a VPU.
  • [0062]
    For example, there may be the following data types:
  • [0000]
    TYPE stream1 of byte [ ];
    TYPE stream2 of byte [0..255;
  • [0063]
    The term “stream” defines a data stream usually of a great, possibly not previously known, and/or infinite, length. Stream1 here had a length that was not previously known. For example, an FIR filter programmed with this type of data (or, for example, an FFT or DCT) could be mapped automatically onto a VPU—and optionally rolled out. The reconfiguration is then typically and preferably performed in response to other mechanisms than the data stream, e.g., by counters, comparators, CT-controlled and/or by timeout. For example, if wave configuration or some other reconfiguration is to be triggered here, then this characterization of a data packet, in particular data bytes, prompted via conventional methods may be the last to take place to trigger the reconfiguration after and/or with the run-through of this data packet, which is characterized as the last data packet.
  • [0064]
    stream2 defines a data stream having the length of 256 bytes here, which may be treated like stream1, but has the property of ending after 256 bytes and thus possibly triggering a reconfiguration after the end in the sense of the patents cited above by the same applicant. In particular a wave reconfiguration, e.g., according to DE 197 04 728.9, DE 199 26 538.0, DE 102 06 857.7, DE 100 28 397.7 may be triggered with the occurrence of the last data byte and the particular PAE processing the byte may be reconfigured with the processing of this last data byte.
  • [0065]
    A translation of the extracted code according to NML which is suitable for the implemented VPU may preferably be performed.
  • [0066]
    For data flow-oriented VPUs, a data flow graph and/or a control flow graph may be created automatically, for example. The graphs are then translated into NML code.
  • [0067]
    Corresponding code portions such as loops may then be translated via a database (lookup) or ordinary transformations may be performed. For code portions, macros may also be provided and are then used further according to the IKR disclosed in the aforementioned patent applications.
  • [0068]
    Modularization according to PACT13 (PCT/DE00/01869), FIG. 28 may also be supported.
  • [0069]
    Optionally, the mapping and/or its preparation may already take place on the VPU, e.g., by performing the placement of the required resources and routing the connections (place and route). This may be done, for example, according to the conventional rules of placement and routing.
  • [0070]
    It is also possible to analyze the extracted code and/or the translated NML code for its processing efficiency by using an automatic analytical method. The analytical method is preferably selected so that the interface code and the performance influences derived from it are also included in the analysis at a suitable point. Suitable analytical methods are described, for example, in the patent applications by the present patent applicant as cited above.
  • [0071]
    The analysis is optionally performed via complete translation and implementation on the hardware system by executing the PROGRAM and performing measurements using suitable conventional methods.
  • [0072]
    It is also possible that, based on the analyses performed, various portions that have been selected for a VPU by extraction might be identified as unsuitable. Conversely, the analysis may reveal that certain portions that have been extracted for a PROCESSOR would be suitable for execution on a VPU.
  • [0073]
    An optional loop which leads back to the extraction portion after analysis based on suitable decision criteria to execute this loop with extraction specifications according to the analysis permits optimization of the translation results. This is thus an iteration. This procedure is preferred.
  • [0074]
    A loop may be introduced into the compiler run at various points.
  • [0075]
    The resulting NML code is to be partitioned according to the properties of the VPU used as needed, i.e., broken down into individual portions which may be mapped into the particular resources available.
  • [0076]
    A plurality of such mechanisms, in particular those based on graphic analysis, are known per se according to the related art. However, a preferred variant is based on analysis of the program sources and is known by the term temporal partitioning. This method is described in the aforementioned Ph.D. thesis by Cardoso, which is herewith incorporated to the full extent for disclosure purposes.
  • [0077]
    Partitioning methods, regardless of the type, are to be adapted according to the type of VPU used. When using VPUs which allow storage of intermediate results in registers and/or memories, the tie-in of the memories for storage of data and/or states is to be taken into account through the partitioning. The partitioning algorithms (e.g., the temporal partitioning) are to be adapted accordingly. Usually the actual partitioning and scheduling are greatly simplified and made possible in a reasonable manner for the first time through these patents.
  • [0078]
    Many VPUs offer the possibility of differential reconfiguration. This may be used when only relatively few changes within the configuration of PAEs are necessary in a reconfiguration. In other words, only the changes in a configuration in comparison with the present configuration are reconfigured. The partitioning in this case may be done so that the possibly differential configuration following a configuration contains only the required configuration data and does not constitute a complete configuration. It is possible to also take into account the configuration data overhead for analytical purposes in evaluating the partitioning efficiency.
  • [0079]
    The scheduling mechanisms for the partitioned codes may be expanded so that scheduling is controlled by acknowledgment messages of the VPU to the particular unit being reconfigured (CT and/or HOSTRECONF). In particular, the resulting possibility of a conditional execution, i.e., explicit determination of the subsequent partition by the state of the instantaneous partition, is utilized in partitioning. In other words, it is possible to optimize the partitioning so that conditional executions such as IF, CASE, etc. are taken into account.
  • [0080]
    If VPUs which have the ability to transmit status signals between PAEs are used, the PAEs responding to the particular states transmitted and/or cooperating in their processing, then within the partitioning and the scheduling, the additional execution may also be taken into account within the configuration of PAEs, i.e., without the necessity of complete or partial reconfiguration due to an altered conditional program run.
  • [0081]
    In addition, scheduling may support the possibility of preloading configurations during the run time of another configuration. A plurality of configurations may also be preloaded speculatively, i.e., without being certain that the configurations are needed at all. Through selection mechanisms, the configurations that are used may then be selected at run time (see also the example NLS in DE 100 50 442.6, EP 01 102 674.7).
  • [0082]
    According to an additional or alternative variant, data processing within the VPU connected to the CPU requires exactly the same number of cycles as data processing within the computation pipeline of the CPU. In the case of today's high-performance CPUs having a plurality of pipeline stages (>20) in particular, this concept may be used ideally. The special advantage is that no separate synchronization measures such as RDY/ACK are necessary and/or no adaptation of opcodes to the register control is necessary. In this method, the compiler must ensure that the VPU maintains the required number of cycles and that data processing may be balanced by the insertion of delay stages such as a fall-through FIFO, such as that described in other patent applications cited above.
  • [0083]
    The code that is output is usually completely processable on the particular downstream compilers, preferably without any additional measures. If necessary, compiler flags and constraints may be generated for controlling downstream compilers, in which case the user may optionally add his or her own specifications and/or may modify the specifications generated. The downstream compilers do not require any significant modifications, so that standard conventional tools may in principle be used.
  • [0084]
    The method proposed here is thus suitable in particular as a preprocessor and/or as a processor method, for example, upstream from compilers and development systems. However, it should be pointed out explicitly that instead of and/or together with the translator described previously, compilers according to PACT11 (DE 101 39 1706; US 2003/0056202) may also be involved in principle.
  • [0085]
    An FPGA may be connected to the architecture described here, in particular directly to the VPU, to permit fine-grained data processing and/or to permit a flexibly adaptable interface (e.g., various serial interfaces (V24, USB, etc.), various parallel interfaces, hard drive interfaces, Ethernet, telecommunications interfaces (a/b, TO, ISDN, DSL, etc.)) to additional modules. The FPGA may be configured from the VPU architecture, in particular by the CT and/or by the CPU. The FPGA may be operated statically, i.e., without run time reconfiguration, and/or dynamically, i.e., with run time reconfiguration.
  • [0086]
    Providing an interface code has already been mentioned. The interface code which is inserted into the extracted code may be predefined by various methods. The interface code is preferably stored in a database which is accessed. The unit for implementation may be designed to take into account a selection, e.g., by the programmer, in which the appropriate interface code is selected, e.g., based on instructions in the PROGRAM or by compiler flags. An interface code suitable for the implementation method of the VPU/CPU system, used in each case, may be selected.
  • [0087]
    The database itself may be created and maintained by various methods. A few examples will be presented here to illustrate the possibilities:
    • a) The interface code may be predefined by the supplier of the compiler for certain connection methods between the VPU and CPU(s). This may be taken into account in the organization of the database by keeping an appropriate memory device ready and available for this information.
    • b) The interface code may be written by the user himself, who determined the system structure, or it may be modified from existing (exemplary) interface code and added to the database. The database is preferably designed to be user-modifiable in this regard to allow the user to modify the database.
    • c) The interface code may be generated automatically by a development system using which the system structure of the VPU-CPU system has been planned and/or described and/or tested, for example.
  • [0091]
    The interface code is usually preferably designed in such a way that it conforms to the requirements of the programming language in which the extracted code was written and into which the interface code is to be inserted.
  • Debugging and Integration of the Tool Sets
  • [0092]
    Communication routines may be introduced into the interface codes to synchronize various development systems for the PROCESSOR and the VPU. In particular, code for the particular debugger (e.g., according to PACT11) may also be included.
  • [0093]
    The interface code is designed to control and/or enable data exchange between the PROCESSOR and the VPU. It is therefore a suitable and preferred interface for controlling the particular development systems and debuggers. For example, it is possible to activate a debugger for the PROCESSOR as long as the data is being processed by the processor. As soon as the data is transferred via the interface code to one or more VPUs, a debugger for the VPUs is to be activated. If the code is sent back to the PROCESSOR, the PROCESSOR debugger is again to be activated. It is therefore also possible and preferable to handle such sequences by inserting control codes for debuggers and/or development systems into the interface code.
  • [0094]
    Communication and control between the different development systems should therefore preferably be handled via control codes introduced into the interface codes of the PROCESSOR and/or VPU. The control codes may largely correspond to existing standards for the control of development systems.
  • [0095]
    Administration and communication of the development systems are preferably handled as described in the interface codes, but they may also be handled separately from them (if appropriate) according to a corresponding similar method.
  • [0096]
    In many programming languages, in particular in sequential languages such as C, a precise chronological order is predetermined implicitly by the language. In the case of sequential programming languages, this is accomplished by the sequence of individual instructions, for example. If required by the programming language and/or the algorithm, the time information may be mapped onto synchronization models such as RDY/ACK and/or REQ/ACK or to a time stamp method.
  • [0097]
    For example, a subsequent FOR loop may be run and iterated only when a variable (inputstream here) is acknowledged with a RDY in each run. If there is no RDY, the loop run is stopped until RDY is received:
  • [0000]
    while TRUE
      s := 0
      for i: 1 to 3
        s := s + inputstream;
  • [0098]
    The property of sequential languages of being controlled only by instruction processing is connected to the data flow principle of controlling processing through the data flow, i.e., the existence of data. In other words, an instruction and/or a statement (e.g., s:=s+inputstream;) is processed only when it is possible to execute the operation and the data is available.
  • [0099]
    It is noteworthy that this method does not usually result in any change in the syntax or semantics of a high-level language.
  • [0100]
    More complex functions of a high-level language such as looping are implemented by macros. The macros are predefined by the compiler and are instantiated at the translation time.
  • [0101]
    Macros are constructed either of simple language constructs of the high-level language or they are constructed at the assembler level. Macros may be parameterized to permit simple adaptation to the algorithm described (see also PACT11).
  • [0102]
    A standard processor, e.g., an RISC, CISC or DSP (CPU), is thus linked to a reconfigurable processor (VPU).
  • [0103]
    Two different linkage variants, but preferably variants that may also be implemented simultaneously, may be described as follows.
  • [0104]
    A first variant includes a direct link to the instruction set of a CPU (instruction set linkage).
  • [0105]
    A second variant involves linkage via tables in the main memory. Tabulation means are therefore provided in this variant.
  • [0106]
    Free unused instructions are usually present within an instruction set (USA) of a CPU. One or more of these free unused instructions is now used to control VPUs (VPUCODE).
  • [0107]
    A configuration unit (CT) of a VPU is triggered by the decoding of a VPUCODE, and executes certain sequences as a function of the VPUCODE. There is thus a responsive CT for VPU decoding.
  • [0108]
    A VPUCODE may, for example, trigger the loading and/or execution of configurations by the configuration unit (CT) for a VPU.
  • [0109]
    In an expanded embodiment, a VPUCODE may be translated to different VPU instructions via a translation table which is preferably managed by the CPU, or alternatively it may also be managed by the CPU, by a VPU, or from an external unit.
  • [0110]
    The configuration table may be set as a function of the CPU program or code section that has been executed.
  • [0111]
    After arrival of a load instruction, the VPU loads configurations out of its own memory or a memory shared with the CPU. In particular, a VPU configuration may be included in the code of the CPU program being executed at the moment.
  • [0112]
    After receiving an execution instruction, a VPU executes the configuration to be executed and performs the corresponding data processing. The end of data processing may be indicated to the CPU by a termination signal (TERM). Appropriate signal lines/interrupt inputs, etc. are present and/or configured accordingly.
  • [0113]
    Due to the occurrence of a VPUCODE, wait cycles may be executed on the CPU until the termination signal (TERM) of the termination of data processing by the CPU arrives.
  • [0114]
    In a preferred embodiment, processing of the next code continues. If another VPUCODE occurs, then it is possible to wait for the preceding code to be terminated or all the VPCODEs that have been started are queued in a processing pipeline or a task switch is performed, in particular as described below.
  • [0115]
    Termination of data processing is signaled by the arrival of the termination signal (TERM) in a status register. Termination signals arrive in the order of a possible processing pipeline.
  • [0116]
    Data processing on the CPU may be synchronized to the arrival of a termination signal by testing the status register.
  • [0117]
    In one possible embodiment, a task switch may be triggered if an application cannot be continued before the arrival of TERM, e.g., due to data dependencies.
  • [0118]
    It is preferable if loose links are established between processors and VPUs, in which VPUs function largely as independent coprocessors.
  • [0119]
    Such a linkage involves one or more shared data sources and data sinks, usually over shared bus systems and/or shared memories. Data is exchanged between a CPU and a VPU via DMAs and/or other memory access controllers. Data processing is preferably synchronized via an interrupt control or a status query mechanism (e.g., polling).
  • [0120]
    A tight linkage corresponds to the direct linkage of a VPU to the instruction set of a CPU, as described above.
  • [0121]
    In a direct arithmetic unit linkage, a high reconfiguration performance in particular is important. Therefore, wave reconfiguration is preferred. In addition, the configuration words are preferably preloaded so that when the instruction is executed, the configuration may be configured particularly rapidly (via wave reconfiguration, in the optimum case within one cycle). It would also be possible to provide a plurality of arrays, identical arrays in particular, instead of a partial array configuration in the case of high-performance applications, but also in the case of primarily low-performance applications in particular, and to reconfigure at least one of these for a new task, in particular in advance, and then to change easily and completely to another array as needed instead of a reconfiguration or partial reconfiguration of an integral multidimensional coarse-grained field which is partially reconfigurable in run time. Signals may be sent to the subarrays, e.g., via MUX/DEMUX stages, in particular I/O signals, data signals, status signals, and/or trigger signals.
  • [0122]
    For wave reconfiguration, the configurations that are presumably to be executed will preferably be recognized in advance by the compiler at compilation time and preloaded accordingly at run time.
  • [0123]
    At the time of instruction execution, the corresponding configuration is optionally selected and executed individually for each PAE and/or for a PAE subset. Such methods are also described in the publications identified above.
  • [0124]
    A preferred implementation may provide for different data transfers between a CPU and a VPU. Three particularly preferred methods that may be used individually or in combination are described below.
  • [0125]
    In the case of register linkage, the VPU may take data from a CPU register, process it and write it back to a CPU register.
  • [0126]
    Synchronization mechanisms are preferably used between the CPU and the VPU.
  • [0127]
    For example, the VPU may receive a RDY signal due to the data being written to the CPU register by the CPU and then the VPU may process the data thus written. Readout of data from a CPU register by the CPU may result in an ACK signal, which thus signals to the VPU data acceptance by the CPU. Use of the conventional RDY/ACK protocol in a different manifestation is advantageous in the present case precisely with coarse-grained cells of reconfigurable units.
  • [0128]
    CPUs do not typically make similar mechanisms available.
  • [0129]
    Two possible implementations are described in greater detail.
  • [0130]
    One approach that is easily implemented is to perform the data synchronization via a status register. For example, the VPU may indicate to the status register the successful readout of data from a register and the associated ACK signal and/or input of data into a register and the associated RDY signal. The CPU first tests the status register and performs wait loops or task switching, for example, until the RDY or ACK is received, depending on the operation. The CPU will then continue to perform the particular register data transfer.
  • [0131]
    In an expanded embodiment, the instruction set of the CPU is expanded by adding load/store instructions with an integrated status query (load_rdy, store_ack). For example, a new data word is written into a CPU register only when the register has first been read out by the VPU and an ACK signal has been received. Accordingly, load_rdy reads data out of a CPU register only when the VPU has previously entered new data and generated a RDY signal.
  • [0132]
    Data belonging to a configuration to be executed may be written to the CPU registers and/or may be read out of the registers successively more or less by block moves as in the related art. Block move instructions that are implemented if necessary may preferably be expanded by the integrated RDY/ACK status query described here.
  • [0133]
    A plurality of modifications and different embodiments of this basic method are possible.
  • [0134]
    The wave reconfiguration mentioned above allows starting of a new VPU instruction and the corresponding configuration as soon as the operand of the previous VPU instruction has been accepted from the CPU registers. The operands for the new instruction may be written directly into the CPU register after the instruction start.
  • [0135]
    According to the wave reconfiguration method, the VPU is reconfigured successively for the new VPU instruction on completion of data processing of the previous VPU instruction, and the new operands are processed.
  • [0136]
    In addition, data may be exchanged between a VPU and a CPU through suitable bus accesses to shared resources.
  • [0137]
    If there is to be an exchange of data that has been processed by the CPU just prior to the exchange and therefore is presumably still in the cache of the CPU which is preferably to be provided or if the data is processed by the CPU immediately next and therefore is logically placed in the cache of the CPU, this data is preferably read by the VPU out of the cache of the CPU or it is written to the cache of the CPU. This may be determined largely in advance at the compilation time through suitable analyses of the application by the compiler and the binary code may be generated accordingly.
  • [0138]
    If there is to be an exchange of data that is presumably not in the cache of the CPU and/or is presumably not needed subsequently in the cache of the CPU, it is preferably read directly by the VPU from the external bus and the data source connected to it (e.g., memory, peripheral) and/or written to the external bus and the data sink associated with it (e.g., memory, peripheral). This may be ascertained by the compiler largely in advance at compilation time of the application through suitable analyses, and the binary code may be generated accordingly.
  • [0139]
    In a transfer over the bus bypassing the cache, a protocol between the cache and the bus is preferably implemented, ensuring correct contents of the cache. For example, the conventional MESI protocol may be used for this purpose.
  • [0140]
    The methods described here need not at first have any particular mechanism for operating system support. It is preferable to ensure that an operating system to be executed behaves according to the status of a VPU to be supported, which is possible and to which end in particular schedulers may be provided.
  • [0141]
    In the case of a tight arithmetic unit linkage, the status register of the CPU into which the linked VPU enters its data processing status (termination signal) is preferably queried. If further data processing is to be transmitted to the VPU and the VPU has not yet terminated the previous data processing, the system will wait and/or a task switch will preferably be performed.
  • [0142]
    For coprocessor coupling, mechanisms controlled via the operating system, in particular the scheduler, are preferably used.
  • [0143]
    A simple scheduler may either allow the current task to continue running on the CPU after transfer of a function to a VPU, if it is able to run independently and simultaneously with data processing on a VPU. If or as soon as the task must wait for termination of data processing on the VPU, the task scheduler switches to another task.
  • [0144]
    Each task newly activated will check (if it uses the VPU) before use on whether the VPU is available for data processing and/or whether it is still processing data at the present time. Either it must then wait for termination of data processing or preferably the task is switched.
  • [0145]
    A simple and nevertheless efficient method may be created by so-called descriptor tables which may be implemented as follows, for example.
  • [0146]
    Each task generates one or more tables (VPUCALL) having a suitable fixed data format in the memory area assigned to it for callup of the VPU. This table contains all the control information for a VPU such as the program/configuration to be executed and/or the pointer to the memory location(s) or data sources of the input data and/or the memory location(s) or data sinks of the result data and/or additional execution parameters, e.g., data array variables.
  • [0147]
    The memory area of the operating system contains a table or an interlinked list (LINKLIST) which points to all the VPUCALL tables in the order of their creation.
  • [0148]
    Data processing on the VPU then takes place in such a way that a task creates a VPUCALL and calls up the VPU via the operating system. The operating system creates an entry in the LINKLIST. The VPU processes the LINKLIST and executes the particular VPU call referenced. The termination of the particular data processing is indicated by a corresponding entry in the LINKLIST and/or VPUCALL table.
  • [0149]
    The VPU thus works largely independently of the CPU. The operating system and/or the particular task must only monitor the tables (LINKLIST and/or VPUCALL).
  • [0150]
    These two methods are particularly efficient in performance if the VPU used has an architecture which allows reconfiguration that is and/or may be superimposed on data processing.
  • [0151]
    It is thus possible to start a new data processing and possibly a reconfiguration associated with it, immediately after reading the last operands out of the data sources. In other words, it is no longer the termination of data processing, but instead reading the last operands is necessary for synchronization. This greatly increases the performance in data processing.
  • [0152]
    The possible use of an operating system has an additional influence on the handling of states.
  • [0153]
    Operating systems use task schedulers, for example, for managing multiple tasks to permit multitasking.
  • [0154]
    Task schedulers interrupt tasks at a certain point in time, start other tasks and, after the latter have been processed, resume processing of the interrupted task. Locally relevant states may remain unsaved if it is ensured that a configuration (which corresponds to processing of a task) will be terminated only after complete processing—i.e., when all data and states to be processed within this configuration cycle have been saved.
  • [0155]
    However, if the task scheduler interrupts configurations before they have been completely processed, local states and/or data must be stored. In addition, this is advantageous when the processing time of a configuration cannot be predicted. In conjunction with the known holding problem and the risk that a configuration will not be terminated at all (e.g., due to an error), this also seems appropriate to prevent a deadlock of the entire system.
  • [0156]
    In other words, taking into account task switching, relevant states may also be regarded as states which are necessary for task switching and correct restart of data processing.
  • [0157]
    Thus, in task switching the memory for results and, if necessary, also the memory for the operands must be saved and restored again at a later point in time, i.e., on returning to this task. This may be performed by a method comparable to the conventional PUSH/POP instructions and methods. In addition, the state of data processing, i.e., the pointer to the last operand processed completely, must be saved. Reference should be made here in particular to PACT18.
  • [0158]
    Depending on the optimization of task switching, there are two options, for example:
  • [0000]
    a) The interrupted configuration is reconfigured and only the operands are loaded. Data processing begins anew as if the processing of the configuration had not even been started. In other words, all data computations are executed from the beginning, and if necessary, computations are even performed in advance. This option is simple but not very efficient.
    b) The interrupted configuration is reconfigured, the operands and results that have already been calculated being loaded into the particular memory. Data processing is continued with the operands that have not been completely computed. This method is much more efficient, but it presupposes that additional states which occur during processing of the configuration may become relevant, if necessary; for example, at least one pointer to the last operand completely computed must be saved, so that it is possible to begin again with their successors after reconfiguration.
  • [0159]
    A particularly preferred variant for managing relevant data is made available through the context switching described below. In task switching and/or in executing and switching configurations (see, for example, patent application PACT15 (PCT/EP02/02398), which is herewith fully included for disclosure purposes) it may be necessary to save data or states, which are not typically saved together with the working data in the memories for a following configuration because they merely mark an end value, for example.
  • [0160]
    Context switching according to the present invention is implemented by removing a first configuration while the data to be saved remains in the corresponding memories (REGs) (memories, registers, counters, etc.).
  • [0161]
    A second configuration is loaded, connecting the REG in a suitable manner and in a defined order to one or more global memories.
  • [0162]
    The configuration may use address generators, for example, to access the global memory (memories). The configuration may use address generators, for example, to access REGs designed as memories. According to the configured connection between the REGs, the contents of the REGs are written into the global memory in a defined order, with the particular addresses being specified by address generators. The address generator generates the addresses for the global memory (memories) so that the memory areas containing data (PUSH AREA) of the first configuration that has been removed may be assigned unambiguously.
  • [0163]
    In other words, different address spaces are preferably provided for different configurations. This configuration corresponds to a PUSH of conventional processors.
  • [0164]
    Other configurations then use the resources.
  • [0165]
    The first configuration should be restarted. Before that, a third configuration interconnecting the REGs of the first configuration in a defined order is started.
  • [0166]
    The configuration may use address generators, for example, to access the global memory (memories).
  • [0167]
    The configuration may use address generators, for example, to access REGs configured as memories.
  • [0168]
    An address generator generates addresses so that correct access to the PUSH AREA assigned to the first configuration is achieved. The generated addresses and the configured order of the REGs are such that the data of the REGs is output from the memories and into the REGs in the original order. The configuration corresponds to that of a POP of conventional processors.
  • [0169]
    The first configuration is restarted.
  • [0170]
    In summary, a context switch is performed so that by loading particular configurations which operate like PUSH/POP of conventional processor architectures, the data to be saved is exchanged with a global memory.
  • [0171]
    The function is to be illustrated in an example. A function adds up two rows of numbers, where the length of the rows is not known at translation time, but instead is known only at run time.
  • [0000]
    proc example
      while i<length do
        x[i] = a[i] + b[i]
  • [0172]
    This function is now interrupted during execution, e.g., by a task switch, or because the memory provided for x is full. At this point in time, a, b and x are in memories according to the present invention; i and optionally length must be saved, however.
  • [0173]
    To do so, the configuration “example” is terminated, with the register content being saved and a configuration push being started, reading i and length out of the registers and writing them into a memory.
  • [0000]
    proc push
      mem[<push_adr_example>] = i
      push_adr_example++
      mem{<push_adr_example>] = length
  • [0174]
    According to this embodiment, push is terminated and the register content may be deleted.
  • [0175]
    Other configurations are executed. After a period of time, the example configuration is restarted.
  • [0176]
    Before that, a configuration pop is started, and it reads the register contents out of the memory again.
  • [0000]
    proc pop
      i = mem[<push_adr_example>]
      push_adr_example++
      length = mem[<push_adr_example>]
  • [0177]
    After execution, pop is terminated and the register contents remain unchanged. The configuration “example” is restarted.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0178]
    FIG. 1 shows an example of a possible system structure.
  • [0179]
    FIG. 2 shows an example compilation sequence.
  • [0180]
    FIG. 3 shows the structure of an example VPU.
  • [0181]
    FIG. 4 shows an example CPU.
  • [0182]
    FIG. 5 shows an example abstract system definition.
  • [0183]
    FIG. 6 shows an example interface.
  • [0184]
    FIG. 7 shows data transfers between VPU and CPU.
  • [0185]
    FIG. 8 shows a memory area of the operating system.
  • DETAILED DESCRIPTION
  • [0186]
    FIG. 1 illustrates an example of, in accordance with the present invention, an example method and shows a possible system structure, a PROCESSOR (0101) being connected to a VPU (0103) via a suitable interface (0102) for data exchange and status exchange.
  • [0187]
    A PROGRAM code (0110) is broken down (e.g., by a preprocessor for a compiler) into a portion (0111) suitable for the PROCESSOR and a VPU-suitable portion (0112), for example, according to the extraction methods described here.
  • [0188]
    Portion 0111 is translated by a standard compiler (0113) corresponding to the PROGRAM code, the additional code from a database (0114) for description and management of the interface (0102) between the PROCESSOR and a VPU being previously inserted. Sequential code executable on 0101 is generated (0116) and the corresponding programming (0117) of the interface (0102) is generated if necessary. The standard compiler may be of a type that is available as a conventional commercially available tool or as a portion of a development environment that is commercially available. The preprocessor and/or possibly the VPU compiler and/or possibly the debugger and additional tools may be integrated into an existing commercially available development environment, for example.
  • [0189]
    Portion 0112 is translated by a VPU compiler (0115), additional code for description and management of the interface (0102) being inserted from a database (0114). Configurations executable on 0103 are generated (0118) and, if necessary, the corresponding programming (0119) of the interface (0102) is also generated. It should be pointed out explicitly that in principle, compilers as described in DE 101 39 170.6 may also be used for 0115.
  • [0190]
    FIG. 2 shows a basic compilation sequence as an example. In the extraction unit (0202), a PROGRAM (0201) is broken down into VPU code (0203) and PROCESSOR code (0204) according to different methods. Different methods may be used in any combination for extraction, e.g., instructions in the original PROGRAM (0205) and/or subprogram calls (0206) and/or analytical methods (0207) and/or utilization of object-oriented class libraries (0206 a). The code extracted is translated, if necessary, and checked for its suitability for the particular target system (0208), if necessary. Feedback (0209) to the extraction is possible to obtain improvements due to modified allocation of the codes to a PROCESSOR or a VPU and/or a plurality of same.
  • [0191]
    Thereafter (0211) VPU code 0203 is expanded (0212) using the interface code from a database (0210) and/or (0204) is expanded using the interface code from 0210 to 0213.
  • [0192]
    The resulting code is analyzed for its performance (0214) and, if necessary, feedback (0215) to the extraction is possible to obtain improvements due to modified allocation of the codes to the PROCESSOR or a VPU.
  • [0193]
    The resulting VPU code (0216) is forwarded for further translation to a downstream compiler suitable for the VPU. For further translation, the resulting PROCESSOR code (0217) is processed further in any downstream compiler suitable for the PROCESSOR.
  • [0194]
    It should be pointed out that individual steps may be omitted, depending on the method. Generally, however, at least largely complete code, which is directly translatable without significant intervention by the programmer, or at least without any significant intervention, is output to the particular downstream compiler systems.
  • [0195]
    It is thus proposed that a preprocessor means be provided with a code input for supplying code to be compiled, with code analyzing means, in particular code structure and/or data format and/or data stream recognition and/or evaluation units, and with a segmenting evaluation unit for evaluating a code segmentation performed in response to signals from the code analyzing unit and, if necessary, with an iteration means for repeating a code segmentation until stable and/or sufficiently acceptable values are achieved, and with at least two partial code outputs, a first partial code output outputting partial code for at least one conventional processor, and at least one additional partial code output outputting code intended for processing by means of reconfigurable logic units, in particular multidimensional units having cell structures, in particular register means which process coarse-grained data and/or logic cells (PAEs) having arithmetic units and the like plus allocated register units, if necessary, and/or a fine-grained control means and/or monitoring means, such as state machines, RDY/ACK trigger lines and communication lines, etc. Both partial code outputs may be located at one physical output as serial multiplex outputs.
  • [0196]
    The database for the interface codes (0210) is constructed independently of and prior to the compiler run. For example, the following sources for the database are possible: predefined by the supplier (0220), programmed by the user (0221) or generated automatically by a development system (0222).
  • [0197]
    FIG. 3 shows the structure of a particularly preferred VPU. Preferably hierarchical configuration managers (CTs) (0301) control and manage a system of reconfigurable elements (PACs) (0302). The CTs are assigned a local memory for the configurations (0303). The memory also has an interface (0304) to a global memory which makes the configuration data available. The configuration runs in a controllable manner via an interface (0305). An interface of the reconfigurable elements (0302) to sequence control and event management (0306) is present, as is an interface to the data exchange (0307). An interface of the reconfigurable elements (0302) for sequence control and event management (0306) is present as is an interface for data exchange (0307).
  • [0198]
    FIG. 4 shows details of an exemplary CPU system, e.g., a DSP of the C6000 type (0401) by Texas Instruments. This shows the program memory (0402), data memory (0403), any peripheral device (0404) and EMIF (0405). A VPU is integrated (0408) as a coprocessor via a memory bus (0406) and a peripheral bus (0407). A DMA controller (EDMA) (0409) may perform any DMA transfers, e.g., between the memory (0403) and the VPU (0408) or the memory (0403) and the peripheral device (0404).
  • [0199]
    FIG. 5 shows a more abstract system definition. A CPU (0501) is assigned a memory (0502) to which it has reading access and/or writing access. A VPU (0503) is connected to the memory. The VPU is subdivided into a CT portion (0509) and the reconfigurable elements for data processing (0510).
  • [0200]
    To increase the memory accesses, the memory may have a plurality of independent access buses (multiport). In a particularly preferred embodiment, the memory is segmented into a plurality of independent segments (memory banks), each bank being independently accessible. All the segments are preferably located within a uniform address space. One segment is preferably available mainly for the CPU (0504) and another segment is mainly available for data processing by the VPU (0505) while yet another segment is mainly available for the configuration data of the VPU (0506).
  • [0201]
    Typically and preferably, a fully configured VPU will have its own address generators and/or DMAs to perform data transfers. Alternatively and/or additionally, it is possible for a DMA (0507) to be provided within the system (FIG. 5) for data transfers with the VPU.
  • [0202]
    The system includes IO (0508) which may be accessible by the CPU and VPU.
  • [0203]
    The CPU and VPU may each have dedicated memory areas and IO areas to which the other has no access.
  • [0204]
    A data record (0511) which may be in the memory area and/or in the IO area and/or partially in one of the two is used for communication between the CPU and the VPU, e.g., for exchanging basic parameters and control information. The data record may contain the following information, for example:
      • 1. Basic address(es) of the CT memory area in 0506 for localizing the configurations.
      • 2. Basic address(es) of data transfers with 0505.
      • 3. IO address(es) of data transfers with 0508.
      • 4. Synchronization information, e.g., resetting, stopping, starting the VPU.
      • 5. Status information on the VPU, e.g., errors or states of data processing.
  • [0210]
    The CPU and the VPU are synchronized by data polling and/or preferably by interrupt control (0512).
  • [0211]
    FIG. 6 shows one possible embodiment of the interface structure of a VPU for tying into a system similar to that shown in FIG. 5. To do so, a memory/DMA interface and/or an IO interface is assigned (0601) to the VPU for data transfer; another system interface (0602) is responsible for sequence control such as managing interrupts, starting and stopping the processing, exchange of error states, etc.
  • [0212]
    The memory/DMA interface and/or IO interface is connected to a memory bus and/or an IO bus.
  • [0213]
    The system interface is preferably connected to an IO bus, but alternatively or additionally, it may also be connected to a memory according to 0511.
  • [0214]
    The interfaces (0601, 0402) may be designed for adaptation of different working frequencies of the CPU and/or the VPU and/or the system; for example, the system and/or the CPU may currently operate at 500 MHz and the VPU at 200 MHz.
  • [0215]
    The interfaces may perform a translation of the bus protocols, e.g., the VPU-internal protocol may be converted to an external AMBA bus protocol. They thus trigger bus protocol translation means and/or are designed for bus protocol translation, in particular bus protocol translation between an internal VPU protocol and a known bus protocol. It is also possible to provide for conversion directly to CPU-internal bus protocols.
  • [0216]
    The memory/DMA interface and/or the IO interface supports memory access by the CT to an external memory, which is preferably performed directly (memory mapped). The data transfer of the CT(s) and/or PAC(s) may be buffered, e.g., via FIFO stages. External memories may be addressed directly; in addition, DMA-internal and/or external DMA transfers are also performed.
  • [0217]
    Data processing, e.g., the initialization, i.e., the start of configurations, is controlled via the system interface. In addition, status and/or error states are exchanged. Interrupts for the control and synchronization between the CTs and a CPU may be supported.
  • [0218]
    The system interface is capable of converting VPU-internal protocols so that they are converted to external (standard) protocols (e.g., AMBA).
  • [0219]
    A preferred method of code generation for the system described here is described herein. This method describes a compiler which breaks down program code into code for a CPU and code for a VPU. The breakdown is performed by different methods on different processors. In a particularly preferred embodiment, the particular codes broken down are expanded by adding the interface routines for communication between CPU and VPU. The expansion may be performed automatically by the compiler.
  • [0220]
    The following tables show examples of communication between a CPU and a VPU. The columns are assigned to the particular active function units: CPU, system DMA and DMA interface (EDMA) and/or memory interface (memory I/F), system interface (system I/F, 0602), CTs and the PAC. The individual cycles are entered into the cells in the order of their execution. K1 references a configuration 1 that is to be executed.
  • [0221]
    The first table shows as an example a sequence when using the system DMA (EDMA) for data transfer:
  • [0000]
    CPU EDMA System I/F CTs PAC
    Initiate
    K1
    Load
    K1
    Start Configure
    K1 K1
    Initiate Start Wait for
    loading of K1 data
    data by EDMA
    Initiate Data transfer Data
    reading of read data processing
    data by EDMA
    Data transfer Signal the end
    write data of the operation
  • [0222]
    It should be pointed out that synchronization between the EDMA and the VPU is performed automatically via interface 0401, i.e., DMA transfers take place only when the VPU is ready.
  • [0223]
    A second table shows a preferred optimized sequence as an example. The VPU itself has direct access to the configuration memory (0306). In addition, data transfers are executed by
  • [0224]
    DMA circuit within the VPU, which may be fixedly implemented, for example, and/or formed by the configuration of configurable parts of the PAC.
  • [0000]
    CPU EDMA System I/F CTs PAC
    Initiate
    K1
    Start Read the Configure
    K1 configuration K1
    Data transfer Start Read data
    read data K1
    Data
    processing
    Data transfer Signal the end Write data
    write data of the operation
  • [0225]
    The complexity for the CPU is minimal.
  • [0226]
    In summary, the present invention relates to methods that permit translation of a traditional high-level language such as Pascal, C, C++, Java, etc., onto a reconfigurable architecture. This method is designed so that only those portions of the program that are to be translated and are suitable for the reconfigurable target architecture are extracted. The remaining portions of the program are translated onto a conventional processor architecture.
  • [0227]
    For reasons of simplicity, FIG. 7 shows only the relevant components (in particular the CPU), although a significant number of other components and networks would typically be present.
  • [0228]
    A preferred implementation such as that in FIG. 7 may provide different data transfers between a CPU (0701) and a VPU (0702). The configurations to be executed on the VPU are selected by the instruction decoder (0705) of the CPU, which recognizes certain instructions intended for the VPU and triggers the CT (0706), so that it loads the corresponding configurations out of a memory (0707) assigned to the CT—which may be shared with the CPU in particular or may be the same as the working memory of the CPU—into the array of PAEs (PA, 0108).
  • [0229]
    CPU registers (0703) are provided to obtain data in a register connection, to process the data and to write it back to a CPU register. A status register (0704) is provided for data synchronization. In addition, a cache is also provided, so that when data that has just been processed by the CPU is to be exchanged, it is still presumably in the cache (0709) of the CPU and/or will be processed immediately thereafter by the CPU.
  • [0230]
    The external bus is labeled as (0710) and through it, data is read out of a data source (e.g., memory, peripheral device) connected to it, for example, and/or is written to the external bus and the data sink connected to it (e.g., memory, peripheral device). This bus may in particular be the same as the external bus of the CPU (0712 & dashed line).
  • [0231]
    A protocol (0711) between cache and bus is implemented, ensuring the correct contents of the cache. An FPGA (0713) may be connected to the VPU to permit fine-grained data processing and/or to permit a flexible adaptable interface (0714) (e.g., various serial interfaces (V24, USB, etc.), various parallel interfaces, hard drive interfaces, Ethernet, telecommunications interfaces (a/b, TO, ISDN, DSL, etc.)) to additional modules and/or the external bus system (0712).
  • [0232]
    According to FIG. 8, the memory area of the operating system contains a table or an interlinked list (LINKLIST, 0801) which points to all VPUCALL tables (0802) in the order in which they are created.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US10450 *24 Jan 1854 Thomas peossbr
US566597 *20 Jun 189625 Aug 1896 James a
US3564506 *17 Jan 196816 Feb 1971IbmInstruction retry byte counter
US3681578 *13 Nov 19701 Aug 1972Marconi Co LtdFault location and reconfiguration in redundant data processors
US3753008 *14 Jun 197114 Aug 1973Honeywell Inf SystemsMemory pre-driver circuit
US3754211 *30 Dec 197121 Aug 1973IbmFast error recovery communication controller
US4498134 *26 Jan 19825 Feb 1985Hughes Aircraft CompanySegregator functional plane for use in a modular array processor
US4498172 *26 Jul 19825 Feb 1985General Electric CompanySystem for polynomial division self-testing of digital networks
US4566102 *18 Apr 198321 Jan 1986International Business Machines CorporationParallel-shift error reconfiguration
US4571736 *31 Oct 198318 Feb 1986University Of Southwestern LouisianaDigital communication system employing differential coding and sample robbing
US4646300 *14 Nov 198324 Feb 1987Tandem Computers IncorporatedCommunications method
US4686386 *18 Mar 198511 Aug 1987Oki Electric Industry Co., Ltd.Power-down circuits for dynamic MOS integrated circuits
US4720778 *31 Jan 198519 Jan 1988Hewlett Packard CompanySoftware debugging analyzer
US4720780 *17 Sep 198519 Jan 1988The Johns Hopkins UniversityMemory-linked wavefront array processor
US4761755 *11 Jul 19842 Aug 1988Prime Computer, Inc.Data processing system and method having an improved arithmetic unit
US4860201 *2 Sep 198622 Aug 1989The Trustees Of Columbia University In The City Of New YorkBinary tree parallel processor
US4870302 *19 Feb 198826 Sep 1989Xilinx, Inc.Configurable electrical circuit having configurable logic elements and configurable interconnects
US4891810 *27 Oct 19872 Jan 1990Thomson-CsfReconfigurable computing device
US4901268 *19 Aug 198813 Feb 1990General Electric CompanyMultiple function data processor
US4959781 *16 May 198825 Sep 1990Stardent Computer, Inc.System for assigning interrupts to least busy processor that already loaded same class of interrupt routines
US4992933 *4 May 199012 Feb 1991International Business Machines CorporationSIMD array processor with global instruction control and reprogrammable instruction decoders
US5041924 *30 Nov 198820 Aug 1991Quantum CorporationRemovable and transportable hard disk subsystem
US5043978 *21 Sep 198927 Aug 1991Siemens AktiengesellschaftCircuit arrangement for telecommunications exchanges
US5081375 *2 Jan 199114 Jan 1992National Semiconductor Corp.Method for operating a multiple page programmable logic device
US5142469 *29 Mar 199025 Aug 1992Ge Fanuc Automation North America, Inc.Method for converting a programmable logic controller hardware configuration and corresponding control program for use on a first programmable logic controller to use on a second programmable logic controller
US5233539 *30 Oct 19893 Aug 1993Advanced Micro Devices, Inc.Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
US5237686 *14 Sep 199217 Aug 1993Mitsubishi Denki Kabushiki KaishaMultiprocessor type time varying image encoding system and image processor with memory bus control table for arbitration priority
US5276836 *10 Jan 19914 Jan 1994Hitachi, Ltd.Data processing device with common memory connecting mechanism
US5287472 *22 Aug 199015 Feb 1994Tandem Computers IncorporatedMemory system using linear array wafer scale integration architecture
US5287511 *15 Oct 199115 Feb 1994Star Semiconductor CorporationArchitectures and methods for dividing processing tasks into tasks for a programmable real time signal processor and tasks for a decision making microprocessor interfacing therewith
US5287532 *14 Nov 199015 Feb 1994Amt (Holdings) LimitedProcessor elements having multi-byte structure shift register for shifting data either byte wise or bit wise with single-bit output formed at bit positions thereof spaced by one byte
US5336950 *8 Feb 19939 Aug 1994National Semiconductor CorporationConfiguration features in a configurable logic array
US5339840 *26 Apr 199323 Aug 1994Sunbelt Precision Products Inc.Adjustable comb
US5343406 *28 Jul 198930 Aug 1994Xilinx, Inc.Distributed memory architecture for a configurable logic array and method for using distributed memory
US5379444 *7 Jun 19943 Jan 1995Hughes Aircraft CompanyArray of one-bit processors each having only one bit of memory
US5386154 *23 Jul 199231 Jan 1995Xilinx, Inc.Compact logic cell for field programmable gate array chip
US5386518 *12 Feb 199331 Jan 1995Hughes Aircraft CompanyReconfigurable computer interface and method
US5392437 *6 Nov 199221 Feb 1995Intel CorporationMethod and apparatus for independently stopping and restarting functional units
US5440245 *9 Mar 19938 Aug 1995Actel CorporationLogic module with configurable combinational and sequential blocks
US5440538 *23 Sep 19938 Aug 1995Massachusetts Institute Of TechnologyCommunication system with redundant links and data bit time multiplexing
US5442790 *9 Mar 199415 Aug 1995The Trustees Of Princeton UniversityOptimizing compiler for computers
US5444394 *8 Jul 199322 Aug 1995Altera CorporationPLD with selective inputs from local and global conductors
US5483620 *9 Mar 19959 Jan 1996International Business Machines Corp.Learning machine synapse processor system apparatus
US5485103 *15 Dec 199416 Jan 1996Altera CorporationProgrammable logic array with local and global conductors
US5485104 *18 Jan 199516 Jan 1996Advanced Micro Devices, Inc.Logic allocator for a programmable logic device
US5489857 *3 Aug 19926 Feb 1996Advanced Micro Devices, Inc.Flexible synchronous/asynchronous cell structure for a high density programmable logic device
US5491353 *31 Mar 199513 Feb 1996Xilinx, Inc.Configurable cellular array
US5493239 *31 Jan 199520 Feb 1996Motorola, Inc.Circuit and method of configuring a field programmable gate array
US5493663 *22 Apr 199220 Feb 1996International Business Machines CorporationMethod and apparatus for predetermining pages for swapping from physical memory in accordance with the number of accesses
US5544336 *11 Apr 19956 Aug 1996Fujitsu LimitedParallel data processing system which efficiently performs matrix and neurocomputer operations, in a negligible data transmission time
US5548773 *30 Mar 199320 Aug 1996The United States Of America As Represented By The Administrator Of The National Aeronautics And Space AdministrationDigital parallel processor array for optimum path planning
US5550782 *18 May 199427 Aug 1996Altera CorporationProgrammable logic array integrated circuits
US5596742 *2 Apr 199321 Jan 1997Massachusetts Institute Of TechnologyVirtual interconnections for reconfigurable logic systems
US5600265 *20 Dec 19954 Feb 1997Actel CorporationProgrammable interconnect architecture
US5600845 *27 Jul 19944 Feb 1997Metalithic Systems IncorporatedIntegrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5602999 *30 Apr 199011 Feb 1997Hyatt; Gilbert P.Memory system having a plurality of memories, a plurality of detector circuits, and a delay circuit
US5603005 *27 Dec 199411 Feb 1997Unisys CorporationCache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed
US5606698 *7 Mar 199525 Feb 1997Cadence Design Systems, Inc.Method for deriving optimal code schedule sequences from synchronous dataflow graphs
US5649176 *10 Aug 199515 Jul 1997Virtual Machine Works, Inc.Transition analysis and circuit resynthesis method and device for digital circuit modeling
US5649179 *19 May 199515 Jul 1997Motorola, Inc.Dynamic instruction allocation for a SIMD processor
US5652529 *2 Jun 199529 Jul 1997International Business Machines CorporationProgrammable array clock/reset resource
US5652894 *29 Sep 199529 Jul 1997Intel CorporationMethod and apparatus for providing power saving modes to a pipelined processor
US5655069 *7 Aug 19965 Aug 1997Fujitsu LimitedApparatus having a plurality of programmable logic processing units for self-repair
US5655124 *7 Jun 19955 Aug 1997Seiko Epson CorporationSelective power-down for high performance CPU/system
US5656545 *26 Feb 199612 Aug 1997Taiwan Semiconductor Manufacturing Company, LtdElimination of tungsten dimple for stacked contact or via application
US5656950 *26 Oct 199512 Aug 1997Xilinx, Inc.Interconnect lines including tri-directional buffer circuits
US5657330 *15 Jun 199512 Aug 1997Mitsubishi Denki Kabushiki KaishaSingle-chip microprocessor with built-in self-testing function
US5659785 *10 Feb 199519 Aug 1997International Business Machines CorporationArray processor communication architecture with broadcast processor instructions
US5659797 *9 Jun 199219 Aug 1997U.S. Philips CorporationSparc RISC based computer system including a single chip processor with memory management and DMA units coupled to a DRAM interface
US5705938 *5 Sep 19956 Jan 1998Xilinx, Inc.Programmable switch for FPGA input/output signals
US5706482 *29 May 19966 Jan 1998Nec CorporationMemory access controller
US5713037 *7 Jun 199527 Jan 1998International Business Machines CorporationSlide bus communication functions for SIMD/MIMD array processor
US5717890 *1 Mar 199510 Feb 1998Kabushiki Kaisha ToshibaMethod for processing data by utilizing hierarchical cache memories and processing system with the hierarchiacal cache memories
US5717943 *5 Jun 199510 Feb 1998International Business Machines CorporationAdvanced parallel array processor (APAP)
US5778237 *14 Dec 19957 Jul 1998Hitachi, Ltd.Data processor and single-chip microcomputer with changing clock frequency and operating voltage
US5778439 *18 Aug 19957 Jul 1998Xilinx, Inc.Programmable logic device with hierarchical confiquration and state storage
US5781756 *1 Apr 199414 Jul 1998Xilinx, Inc.Programmable logic device with partially configurable memory cells and a method for configuration
US5784313 *18 Aug 199521 Jul 1998Xilinx, Inc.Programmable logic device including configuration data or user data memory slices
US5784630 *3 Jan 199521 Jul 1998Hitachi, Ltd.Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory
US5784636 *28 May 199621 Jul 1998National Semiconductor CorporationReconfigurable computer architecture for use in signal processing applications
US5794059 *28 Jul 199411 Aug 1998International Business Machines CorporationN-dimensional modified hypercube
US5794062 *17 Apr 199511 Aug 1998Ricoh Company Ltd.System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
US5844422 *13 Nov 19961 Dec 1998Xilinx, Inc.State saving and restoration in reprogrammable FPGAs
US5857097 *10 Mar 19975 Jan 1999Digital Equipment CorporationMethod for identifying reasons for dynamic stall cycles during the execution of a program
US5857109 *11 Apr 19955 Jan 1999Giga Operations CorporationProgrammable logic device for real time video processing
US5859544 *5 Sep 199612 Jan 1999Altera CorporationDynamic configurable elements for programmable logic devices
US5860119 *25 Nov 199612 Jan 1999Vlsi Technology, Inc.Data-packet fifo buffer system with end-of-packet flags
US5862403 *16 Feb 199619 Jan 1999Kabushiki Kaisha ToshibaContinuous data server apparatus and data transfer scheme enabling multiple simultaneous data accesses
US5867691 *15 Mar 19932 Feb 1999Kabushiki Kaisha ToshibaSynchronizing system between function blocks arranged in hierarchical structures and large scale integrated circuit using the same
US5867723 *5 Aug 19962 Feb 1999Sarnoff CorporationAdvanced massively parallel computer with a secondary storage device coupled through a secondary storage interface
US5870620 *30 May 19969 Feb 1999Sharp Kabushiki KaishaData driven type information processor with reduced instruction execution requirements
US5924119 *27 Jan 199413 Jul 1999Xerox CorporationConsistent packet switched memory bus for shared memory multiprocessors
US5926638 *17 Jan 199720 Jul 1999Nec CorporationProgram debugging system for debugging a program having graphical user interface
US5933023 *3 Sep 19963 Aug 1999Xilinx, Inc.FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines
US5933642 *9 Apr 19973 Aug 1999Ricoh CorporationCompiling system and method for reconfigurable computing
US5936424 *14 Oct 199710 Aug 1999Xilinx, Inc.High speed bus with tree structure for selecting bus driver
US5943242 *17 Nov 199524 Aug 1999Pact GmbhDynamically reconfigurable data processing system
US5966534 *27 Jun 199712 Oct 1999Cooke; Laurence H.Method for compiling high level programming languages into an integrated processor with reconfigurable logic
US5978583 *7 Aug 19952 Nov 1999International Business Machines Corp.Method for resource control in parallel environments using program organization and run-time support
US6011407 *13 Jun 19974 Jan 2000Xilinx, Inc.Field programmable gate array with dedicated computer bus interface and method for configuring both
US6014509 *24 Sep 199711 Jan 2000Atmel CorporationField programmable gate array having access to orthogonal and diagonal adjacent neighboring cells
US6020758 *11 Mar 19961 Feb 2000Altera CorporationPartially reconfigurable programmable logic device
US6020760 *16 Jul 19971 Feb 2000Altera CorporationI/O buffer circuit with pin multiplexing
US6021490 *8 Oct 19971 Feb 2000Pact GmbhRun-time reconfiguration method for programmable units
US6023564 *19 Jul 19968 Feb 2000Xilinx, Inc.Data processing system using a flash reconfigurable logic device as a dynamic execution unit for a sequence of instructions
US6023742 *18 Jul 19978 Feb 2000University Of WashingtonReconfigurable computing architecture for providing pipelined data paths
US6026478 *23 Dec 199715 Feb 2000Micron Technology, Inc.Split embedded DRAM processor
US6026481 *4 Nov 199715 Feb 2000Xilinx, Inc.Microprocessor with distributed registers accessible by programmable logic device
US6075935 *1 Dec 199713 Jun 2000Improv Systems, Inc.Method of generating application specific integrated circuits using a programmable hardware architecture
US6077315 *9 Jan 199820 Jun 2000Ricoh Company Ltd.Compiling system and method for partially reconfigurable computing
US6084429 *24 Apr 19984 Jul 2000Xilinx, Inc.PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays
US6085317 *15 Aug 19974 Jul 2000Altera CorporationReconfigurable computer architecture using programmable logic devices
US6086628 *17 Feb 199811 Jul 2000Lucent Technologies Inc.Power-related hardware-software co-synthesis of heterogeneous distributed embedded systems
US6088795 *8 Oct 199711 Jul 2000Pact GmbhProcess for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like)
US6092174 *1 Jun 199818 Jul 2000Context, Inc.Dynamically reconfigurable distributed integrated circuit processor and method
US6096091 *24 Feb 19981 Aug 2000Advanced Micro Devices, Inc.Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip
US6105105 *4 May 199915 Aug 2000Xilinx, Inc.Data processing system using configuration select logic, an instruction store, and sequencing logic during instruction execution
US6105106 *31 Dec 199715 Aug 2000Micron Technology, Inc.Computer system, memory device and shift register including a balanced switching circuit with series connected transfer gates which are selectively clocked for fast switching times
US6108760 *31 Oct 199722 Aug 2000Silicon SpiceMethod and apparatus for position independent reconfiguration in a network of multiple context processing elements
US6170051 *23 Dec 19972 Jan 2001Micron Technology, Inc.Apparatus and method for program level parallelism in a VLIW processor
US6172520 *12 Feb 19999 Jan 2001Xilinx, Inc.FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA
US6173419 *14 May 19989 Jan 2001Advanced Technology Materials, Inc.Field programmable gate array (FPGA) emulator for debugging software
US6173434 *22 Jan 19979 Jan 2001Brigham Young UniversityDynamically-configurable digital processor using method for relocating logic array modules
US6175247 *9 Apr 199916 Jan 2001Lockheed Martin CorporationContext switchable field programmable gate array with public-private addressable sharing of intermediate data
US6178494 *23 Sep 199623 Jan 2001Virtual Computer CorporationModular, hybrid processor and method for producing a modular, hybrid processor
US6185256 *20 Apr 19986 Feb 2001Fujitsu LimitedSignal transmission system using PRD method, receiver circuit for use in the signal transmission system, and semiconductor memory device to which the signal transmission system is applied
US6185731 *11 Sep 19956 Feb 2001Mitsubishi Electric Semiconductor Software Co., Ltd.Real time debugger for a microcomputer
US6188240 *4 Jun 199913 Feb 2001Nec CorporationProgrammable function block
US6188650 *19 Oct 199813 Feb 2001Sony CorporationRecording and reproducing system having resume function
US6191614 *13 Aug 199920 Feb 2001Xilinx, Inc.FPGA configuration circuit including bus-based CRC register
US6219833 *11 Dec 199817 Apr 2001Hewlett-Packard CompanyMethod of using primary and secondary processors
US6256724 *4 Feb 19993 Jul 2001Texas Instruments IncorporatedDigital signal processor with efficiently connectable hardware co-processor
US6260114 *30 Dec 199710 Jul 2001Mcmz Technology Innovations, LlcComputer cache memory windowing
US6260179 *5 May 199810 Jul 2001Fujitsu LimitedCell arrangement evaluating method, storage medium storing cell arrangement evaluating program, cell arranging apparatus and method, and storage medium storing cell arranging program
US6262908 *28 Jan 199817 Jul 2001Elixent LimitedField programmable processor devices
US6263430 *29 Jul 199917 Jul 2001Xilinx, Inc.Method of time multiplexing a programmable logic device
US6266760 *15 Apr 199924 Jul 2001Massachusetts Institute Of TechnologyIntermediate-grain reconfigurable processing device
US6279077 *21 Mar 199721 Aug 2001Texas Instruments IncorporatedBus interface buffer control in a microprocessor
US6282627 *29 Jun 199828 Aug 2001Chameleon Systems, Inc.Integrated processor and programmable data path chip for reconfigurable computing
US6282701 *30 Jul 199828 Aug 2001Mutek Solutions, Ltd.System and method for monitoring and analyzing the execution of computer programs
US6321373 *30 Oct 199920 Nov 2001International Business Machines CorporationMethod for resource control in parallel environments using program organization and run-time support
US6338106 *18 Jun 19998 Jan 2002Pact GmbhI/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
US6339424 *13 Nov 199815 Jan 2002Fuji Xerox Co., LtdDrawing processor
US6341318 *10 Aug 199922 Jan 2002Chameleon Systems, Inc.DMA data streaming
US6347346 *30 Jun 199912 Feb 2002Chameleon Systems, Inc.Local memory unit system with global access for use on reconfigurable chips
US6349346 *23 Sep 199919 Feb 2002Chameleon Systems, Inc.Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit
US6421808 *22 Apr 199916 Jul 2002Cadance Design Systems, Inc.Hardware design language for the design of integrated circuits
US6421809 *23 Jul 199916 Jul 2002Interuniversitaire Micro-Elektronica Centrum (Imec Vzw)Method for determining a storage bandwidth optimized memory organization of an essentially digital device
US6421817 *3 Apr 200016 Jul 2002Xilinx, Inc.System and method of computation in a programmable logic device using virtual instructions
US6425054 *10 Oct 200023 Jul 2002Samsung Electronics Co., Ltd.Multiprocessor operation in a multimedia signal processor
US6425068 *8 Oct 199723 Jul 2002Pact GmbhUnit for processing numeric and logic operations for use in central processing units (cpus), multiprocessor systems, data-flow processors (dsps), systolic processors and field programmable gate arrays (epgas)
US6426649 *29 Dec 200030 Jul 2002Quicklogic CorporationArchitecture for field programmable gate array
US6427156 *21 Jan 199730 Jul 2002Xilinx, Inc.Configurable logic block with AND gate for efficient multiplication in FPGAS
US6430309 *4 Mar 19986 Aug 2002Monogen, Inc.Specimen preview and inspection system
US6434642 *7 Oct 199913 Aug 2002Xilinx, Inc.FIFO memory system and method with improved determination of full and empty conditions and amount of data stored
US6434695 *23 Dec 199813 Aug 2002Apple Computer, Inc.Computer operating system using compressed ROM image in RAM
US6434699 *1 Jun 200013 Aug 2002Mosaid Technologies Inc.Encryption processor with shared memory interconnect
US6437441 *10 Jul 199820 Aug 2002Kawasaki Microelectronics, Inc.Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure
US6438737 *15 Feb 200020 Aug 2002Intel CorporationReconfigurable logic for a computer
US6438747 *20 Aug 199920 Aug 2002Hewlett-Packard CompanyProgrammatic iteration scheduling for parallel processors
US6496971 *7 Feb 200017 Dec 2002Xilinx, Inc.Supporting multiple FPGA configuration modes using dedicated on-chip processor
US6504398 *16 Oct 20007 Jan 2003Actel CorporationIntegrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure
US6507898 *18 Feb 199814 Jan 2003Canon Kabushiki KaishaReconfigurable data cache controller
US6507947 *20 Aug 199914 Jan 2003Hewlett-Packard CompanyProgrammatic synthesis of processor element arrays
US6513077 *25 Jul 200128 Jan 2003Pact GmbhI/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
US6516382 *25 Jun 20014 Feb 2003Micron Technology, Inc.Memory device balanced switching circuit and method of controlling an array of transfer gates for fast switching times
US6518787 *21 Sep 200011 Feb 2003Triscend CorporationInput/output architecture for efficient configuration of programmable input/output cells
US6519674 *18 Feb 200011 Feb 2003Chameleon Systems, Inc.Configuration bits layout
US6523107 *11 Dec 199818 Feb 2003Elixent LimitedMethod and apparatus for providing instruction streams to a processing device
US6525678 *5 Oct 200125 Feb 2003Altera CorporationConfiguring a programmable logic device
US6526520 *29 Mar 200025 Feb 2003Pact GmbhMethod of self-synchronization of configurable elements of a programmable unit
US6539438 *15 Jan 199925 Mar 2003Quickflex Inc.Reconfigurable computing system and method and apparatus employing same
US6587939 *13 Jan 20001 Jul 2003Kabushiki Kaisha ToshibaInformation processing apparatus provided with an optimized executable instruction extracting unit for extending compressed instructions
US6681388 *1 Oct 199920 Jan 2004Real World Computing PartnershipMethod and compiler for rearranging array data into sub-arrays of consecutively-addressed elements for distribution processing
US6687788 *9 Jul 20023 Feb 2004Pact Xpp Technologies AgMethod of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.)
US6694434 *23 Dec 199817 Feb 2004Entrust Technologies LimitedMethod and apparatus for controlling program execution and program distribution
US6697979 *21 Jun 200024 Feb 2004Pact Xpp Technologies AgMethod of repairing integrated circuits
US6708325 *29 Jun 199816 Mar 2004Intel CorporationMethod for compiling high level programming languages into embedded microprocessor with multiple reconfigurable logic
US6757892 *23 Jun 200029 Jun 2004Sarnoff CorporationMethod for determining an optimal partitioning of data among several memories
US6782445 *15 Jun 200024 Aug 2004Hewlett-Packard Development Company, L.P.Memory and instructions in computer architecture containing processor and coprocessor
US6785826 *17 Jul 199631 Aug 2004International Business Machines CorporationSelf power audit and control circuitry for microprocessor functional units
US6847370 *20 Feb 200225 Jan 20053D Labs, Inc., Ltd.Planar byte memory organization with linear access
US6859869 *12 Apr 199922 Feb 2005Pact Xpp Technologies AgData processing system
US6871341 *24 Mar 200022 Mar 2005Intel CorporationAdaptive scheduling of function cells in dynamic reconfigurable logic
US6928523 *6 Jun 20019 Aug 2005Renesas Technology Corp.Synchronous signal producing circuit for controlling a data ready signal indicative of end of access to a shared memory and thereby controlling synchronization between processor and coprocessor
US7000161 *11 Oct 200214 Feb 2006Altera CorporationReconfigurable programmable logic system with configuration recovery mode
US7007096 *12 May 199928 Feb 2006Microsoft CorporationEfficient splitting and mixing of streaming-data frames for processing through multiple processing modules
US7164422 *28 Jul 200016 Jan 2007Ab Initio Software CorporationParameterized graphs with conditional components
US7249351 *30 Aug 200024 Jul 2007Broadcom CorporationSystem and method for preparing software for execution in a dynamically configurable hardware environment
US7254649 *5 Aug 20057 Aug 2007Infineon Technologies AgWireless spread spectrum communication platform using dynamically reconfigurable logic
US7266725 *28 Sep 20014 Sep 2007Pact Xpp Technologies AgMethod for debugging reconfigurable architectures
US7759968 *27 Sep 200620 Jul 2010Xilinx, Inc.Method of and system for verifying configuration data
US7873811 *10 Mar 200318 Jan 2011The United States Of America As Represented By The United States Department Of EnergyPolymorphous computing fabric
US20010010074 *28 Dec 200026 Jul 2001Fuji Xerox Co., Ltd.Data processing method by programmable logic device, programmable logic device, information processing system and method of reconfiguring circuit in programmable logic
US20010018733 *23 Feb 200130 Aug 2001Taro FujiiArray-type processor
US20020004916 *11 May 200110 Jan 2002Marchand Patrick R.Methods and apparatus for power control in a scalable array of processor elements
US20020013861 *29 May 200131 Jan 2002Intel CorporationMethod and apparatus for low overhead multithreaded communication in a parallel processing environment
US20020099759 *24 Jan 200125 Jul 2002Gootherts Paul DavidLoad balancer with starvation avoidance
US20020103839 *18 Jan 20021 Aug 2002Kunihiko OzawaReconfigurable arithmetic device and arithmetic system including that arithmetic device and address generation device and interleave device applicable to arithmetic system
US20030001615 *28 Jun 20022 Jan 2003Semiconductor Technology Academic Research CenterProgrammable logic circuit device having look up table enabling to reduce implementation area
US20030014743 *29 Jun 199816 Jan 2003Cooke Laurence H.Method for compiling high level programming languages
US20030123579 *15 Nov 20023 Jul 2003Saeid SafaviViterbi convolutional coding method and apparatus
US20030135686 *5 Apr 200217 Jul 2003Martin VorbachInternal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity
US20030154349 *24 Jan 200214 Aug 2003Berg Stefan G.Program-directed cache prefetching for media processors
US20040015899 *28 Sep 200122 Jan 2004Frank MayMethod for processing data
US20040025005 *13 Jun 20015 Feb 2004Martin VorbachPipeline configuration unit protocols and communication
US20040168099 *1 Mar 200426 Aug 2004Martin VorbachUnit for processing numeric and logic operations for use in central processing units (CPUs), multiprocessor systems
US20060036988 *21 Oct 200516 Feb 2006Altera CorporationMethods and apparatus for implementing parameterizable processors and peripherals
US20090193384 *12 Jan 200930 Jul 2009Mihai SimaShift-enabled reconfigurable device
USRE34363 *24 Jun 199131 Aug 1993Xilinx, Inc.Configurable electrical circuit having configurable logic elements and configurable interconnects
USRE36839 *16 Dec 199829 Aug 2000Philips Semiconductor, Inc.Method and apparatus for reducing power consumption in digital electronic circuits
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US9384354 *20 Feb 20135 Jul 2016International Business Machines CorporationRule matching in the presence of languages with no types or as an adjunct to current analyses for security vulnerability analysis
US20140237603 *20 Feb 201321 Aug 2014International Business Machines CorporationRule matching in the presence of languages with no types or as an adjunct to current analyses for security vulnerability analysis
Classifications
U.S. Classification712/208, 712/E09.028
International ClassificationG06F9/30, G11C16/00, G06F15/76, G06F9/45, G06F7/00, G06F13/36, G06F1/32, G06F15/80, G06F11/22, G06F13/28, G06F15/177, G06F11/36, G06F9/38, G06F15/18, G06F1/04
Cooperative ClassificationG06F15/7867, G06F8/45
European ClassificationG06F8/45, G06F15/78R
Legal Events
DateCodeEventDescription
8 Feb 2014ASAssignment
Owner name: PACT XPP TECHNOLOGIES AG, GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RICHTER, THOMAS;KRASS, MAREN;REEL/FRAME:032225/0089
Effective date: 20140117