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Publication numberUS20090275266 A1
Publication typeApplication
Application numberUS 12/492,472
Publication date5 Nov 2009
Filing date26 Jun 2009
Priority date2 Oct 2006
Publication number12492472, 492472, US 2009/0275266 A1, US 2009/275266 A1, US 20090275266 A1, US 20090275266A1, US 2009275266 A1, US 2009275266A1, US-A1-20090275266, US-A1-2009275266, US2009/0275266A1, US2009/275266A1, US20090275266 A1, US20090275266A1, US2009275266 A1, US2009275266A1
InventorsPaul N. Winberg, Dung T. Duong, Matthew R. Thomas, Elliot M. Pickering, Hyunchul Ko
Original AssigneeIllumitex, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Optical device polishing
US 20090275266 A1
Abstract
Embodiments described herein provide methods for manufacturing an optical device having shaped sidewalls. A substrate material can be shaped to form a substrate portion of an optical device comprising an exit face and sidewalls positioned and shaped to reflect light to the exit face to allow light to escape the exit face. The sidewalls can be polished to a desired degree of polish. Polishing can be done using a polishing tool, etching, particle jet polishing or other polishing method.
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Claims(19)
1. A method of manufacturing an optical device comprising:
providing a substrate material shaped to form an unpolished substrate portion of an optical device;
polishing the unpolished substrate portion of the optical device to a selected degree of polish to form a substrate portion comprising:
an interface with a non-substrate layer adapted to receive light generated in a light emitting region of the optical device;
an exit face that has at least 70% of a minimum area necessary to conserve radiance for a desired half-angle of light projected from the optical device, wherein the exit face is a select distance from the interface;
a set of sidewalls, each sidewall positioned and shaped to cause at least a majority of rays having a straight transmission path from the interface to that sidewall to reflect to the exit face with an angle of incidence at the exit face at less than or equal to a critical angle at the exit face.
2. The method of claim 1, wherein polishing the set of sidewalls comprises:
providing an abrasive slurry;
vibrating a polishing tool at ultrasonic frequency to cause the abrasive slurry to remove the substrate material in multiple rows.
3. The method of claim 2, wherein the substrate material is shaped to form substrate portions of multiple optical devices arranged in rows with channels between the rows and wherein polishing the sidewalls further comprises vibrating a shaped polishing tool along the channels.
4. The method of claim 2, wherein the polishing tool comprises a polishing wand and vibrating the polishing tool comprises vibrating the polishing wand at an ultrasonic frequency.
5. The method of claim 4, wherein the substrate material is shaped to form substrate portions of multiple optical devices arranged in rows with channels between the rows and wherein polishing the sidewalls further comprises polishing the sidewalls for optical devices along a row at a set of fixed angles tangential to the sidewalls.
6. The method of claim 4, wherein the substrate material is shaped to form substrate portions of multiple optical devices arranged in rows with channels between the rows and wherein polishing the sidewalls further comprises sweeping the wand through a range of angles as the polishing wand polishes one or more select sidewalls.
7. The method of claim 1, wherein polishing further comprises removing the substrate material using a particle jet.
8. The method of claim 1, further comprising:
mounting a wafer comprising the substrate material in a tool; and
protecting portions of the wafer to prevent damage to those portions during polishing.
9. The method of claim 1, further comprising mounting the wafer comprising the substrate material to a support structure.
10. The method of claim 1, wherein polishing further comprises using reactive ion etching to polish.
11. A method of polishing an LED comprising:
providing a set of unpolished substrate portions of optical devices shaped from a wafer;
polishing the set of unpolished substrate portions with a polishing tool to desired degree of polish to form a set of substrate portions, each substrate portion comprising:
an exit face opposite from and a distance from an interface an interface with a non-substrate layer adapted to receive light generated in a light emitting region of the optical device, the exit face having at least 70% of a minimum area necessary to conserve radiance for a desired half-angle of light projected from the shaped substrate; and
a set of sidewalls, wherein each sidewall is positioned and shaped so that at least a majority of rays having a straight transmission path from the interface to that sidewall reflect to the exit face with an angle of incidence at the exit face of less than or equal to a critical angle at the exit face.
12. The method of claim 11, wherein polishing each set of unpolished sidewalls to a desired degree of polish comprises polishing each sidewall to have a roughness average of less than or equal to fifty nanometers.
13. The method of claim 11 wherein the polishing tool comprises a polishing wand, the method further comprising:
(a) vibrating the polishing wand tangential to one or more sidewalls at a select angle to polish the one or more sidewalls;
(b) moving the polishing wand to a number of additional positions along the channel to polish one or more additional sidewalls at the same angle; and
(c) repeating steps (a)-(b) at a select number of additional angles to polish the one or more sidewalls and one or more additional sidewalls at the additional angles.
14. The method of claim 11, wherein the polishing tool comprises a polishing wand, the method further comprising:
(a) positioning the polishing wand at a position along a select channel;
(b) vibrating the polishing wand to polish one or more sidewalls;
(c) sweeping the polishing wand through a range of angles as the polishing wand polishes the one or more sidewalls;
(d) repeating steps (a)-(c) at a select number of additional positions along the selected channel.
15. The method of claim 11, further comprising introducing an abrasive slurry between the polishing tool and the substrate material.
16. The method of claim 15, wherein introducing the abrasive slurry comprises coating each unpolished substrate portion with the abrasive slurry.
17. The method of claim 15, wherein the abrasive slurry comprises abrasive particles having an average size of less than 10 micrometers.
18. The method of claim 17, wherein the abrasive particles are 5-30% of the abrasive slurry.
19. The method of claim 11, wherein the polishing tool is at least partially formed from a liquid crystal polymer.
Description
RELATED APPLICATIONS

This application claims the benefit of priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 61/075,972, entitled “SYSTEM AND METHODS FOR OPTICAL DEVICE SHAPING AND POLISHING” by inventor Winberg, filed Jun. 26, 2008. This application also claims the benefit of priority under 35 U.S.C. 120 as a continuation-in-part of U.S. patent application Ser. No. 11/906,194, entitled “LED SYSTEM AND METHOD” by inventors Duong et al., filed Oct. 1, 2007, and as a continuation-in-part of U.S. patent application Ser. No. 11/906,219, entitled “LED SYSTEM AND METHOD”, by inventors Duong et al., filed Oct. 1, 2007, each of which claim priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 60/827,818, entitled “SHAPED LIGHT EMITTING DIODES”, by inventors Duong et al., filed Oct. 2, 2006, and to U.S. Provisional Patent Application No. 60/881,785, entitled “SYSTEM AND METHOD FOR A SHAPED SUBSTRATE LED”, by inventors Duong et al., filed Jan. 22, 2007. Each of the above referenced applications is hereby fully incorporated by reference herein.

TECHNICAL FIELD OF THE INVENTION

This disclosure regards optical devices and in particular light emitting diodes (“LEDs”). More particularly, this disclosure relates to polishing optical devices.

BACKGROUND

Light emitting diodes (“LEDs”) are ubiquitous in electronics. They are used in digital displays, lighting systems, computers and televisions, cellular telephones and a variety of other devices. Developments in LED technology have led to methods and systems for the generation of white light using one or more LEDs. Developments in LED technology have led to LEDs that generate more photons and thus more light than previously. The culmination of these two technological developments is that LEDs are being used to supplement or replace many conventional lighting sources, e.g. incandescent, fluorescent or halogen bulbs, much as the transistor replaced the vacuum tube in computers.

LEDs are produced in a number of colors including red, green and blue. One method of generating white light involves the use of red, green and blue LEDs in combination with one another. A lighting source that is made of combinations of red, green and blue (RGB) LEDs will produce what is perceived as white light by the human eye. This occurs because the human eye has three types of color receptors, with each type sensitive to either blue, green or red colors.

A second method of producing white light from LED sources is to create light from a single-color (e.g. blue), short wavelength LED, and impinge a portion of that light onto phosphor or similar photon conversion material. The phosphor absorbs the higher energy, short wavelength light waves, and re-emits lower energy, longer wavelength light. If a phosphor is chosen that emits light in the yellow region (between green and red), for example, the human eye perceives such light as white light. This occurs because the yellow light stimulates both the red and green receptors in the eye. Other materials, such as nano-particles or other similar photo-luminescent materials, may be used to generate white light in much the same way.

White light may also be generated utilizing an ultraviolet (UV) LED and three separate RGB phosphors. White light may also be generated from a blue LED and a yellow LED and may also be generated utilizing blue, green, yellow and red LEDs in combination.

Current industry practice for construction of LEDs is to use a substrate (typically either single-crystal Sapphire or Silicon Carbide), onto which is deposited layers of materials such as GaN or InGaN. One or more layers (e.g. GaN or InGaN) may allow photon generation and current conduction. Typically, a first layer of Gallium Nitride (GaN) is applied to the surface of the substrate to form a transition region from the crystal structure of the substrate to the crystal structure of doped layers allowing for photon generation or current conduction. This is typically followed by an N-doped layer of GaN. The next layer can be an InGaN, AlGaN, AlInGaN or other compound semiconductor material layer that generates photons and that is doped with the needed materials to produce the desired wavelength of light. The next layer is typically a P doped layer of GaN. This structure is further modified by etching and deposition to create metallic sites for electrical connections to the device.

During the operation of an LED, as in a traditional diode, extra electrons move from an N-type semiconductor to electron holes in a P-type semiconductor. In an LED, photons are released in the compound semiconductor layer to produce light during this process.

In a typical manufacturing process, the substrate is fabricated in wafer form and the layers are applied to a surface of the wafer. Once the layers are doped or etched and all the features have been defined using the various processes mentioned, the individual LEDs are separated from the wafer. The LEDs are typically square or rectangular with straight sides. This can cause significant efficiency losses and can cause the emitted light to have a poor emission pattern. A separate optical device, such as a plastic dome, is often placed over the LED to achieve a more desirable output.

SUMMARY

This disclosure relates to polishing optical devices to increase light extraction. In particular, the optical device can include sidewalls shaped to direct more light to the exit face of the optical device using total internal reflection while preventing or minimizing total internal reflection at the exit face. Additionally, the optical device can include an exit face with sufficient area to conserve radiance. Various methods can be used to polish the sidewalls of the optical device to a desired degree of polish to promote internal reflection at the sidewalls.

According to one embodiment, a method can comprise providing an unpolished substrate portion of an optical device and polishing the unpolished substrate portion to form a polished substrate portion. According to one embodiment, the exit face of the substrate portion of the optical device can have at least 70% of a minimum area necessary to conserve radiance for a desired half-angle of light projected from the optical device. The set of sidewalls of the shaped substrate portion of the optical device can be positioned and shaped to cause at least a majority of rays having a straight transmission path from the interface to that sidewall to reflect to the exit face with an angle of incidence at the exit face at less than or equal to a critical angle at the exit face. It should be noted that while the sidewalls can be shaped to cause a particular percentage of light to reflect to the interface, such reflection, in some cases, may not occur without adequate polishing. While the degree of polishing can be selected to maximize internal reflection at the sidewalls, the degree of polishing can also be selected to allow for some loss of light at the sidewalls. In one embodiment, the sidewalls are polished to have a roughness average of less than 100 nanometers, even more particularly less than 50 nanometers and even more particularly less than 20 nanometers.

BRIEF DESCRIPTION OF THE FIGURES

A more complete understanding of the embodiments and the advantages thereof may be acquired by referring to the following description, taken in conjunction with the accompanying drawings in which like reference numbers indicate like features and wherein:

FIGS. 1A-1B are diagrammatic representations of embodiments of LEDs;

FIG. 2 is a diagrammatic representation of a set of rays traveling from a point to surfaces at different distances from the point;

FIG. 3 provides a diagrammatic representation of a top view of an embodiment of an LED;

FIG. 4A is a diagrammatic representation of a cross-section of a model of an LED for determining sidewall shapes;

FIG. 4B is a diagrammatic representation of an embodiment of a portion of a sidewall of an LED;

FIG. 4C is a diagrammatic representation illustrating that the facets for a sidewall can be defined using a computer program;

FIG. 4D is a diagrammatic representation of one embodiment of an LED with sidewalls shaped to cause TIR so that rays are reflected from the sidewalls to the exit surface;

FIG. 5 is a diagrammatic representation of one embodiment for estimating effective solid angle;

FIGS. 6A-6E are diagrammatic representations describing another embodiment for estimating effective solid angle;

FIG. 7 is a diagrammatic representation of one embodiment of a LED;

FIGS. 8A-8B are diagrammatic representations of embodiments of an array of LEDs;

FIG. 9 is a diagrammatic representation of polishing substrate material;

FIGS. 10A-B are diagrammatic representations of additional embodiments of polishing substrate material;

FIGS. 11A-C are diagrammatic representations of embodiments of polishing wands;

FIG. 12 is a diagrammatic representation of an embodiment of particle jet polishing; and

FIG. 13 is a diagrammatic representation of an embodiment of reactive ion etching.

DETAILED DESCRIPTION

The disclosure and various features and advantageous details thereof are explained more fully with reference to the exemplary, and therefore non-limiting, embodiments illustrated in the accompanying drawings and detailed in the following description. Descriptions of known starting materials and processes may be omitted so as not to unnecessarily obscure the disclosure in detail. It should be understood, however, that the detailed description and the specific examples, while indicating the preferred embodiments, are given by way of illustration only and not by way of limitation. Various substitutions, modifications, additions and/or rearrangements within the spirit and/or scope of the underlying inventive concept will become apparent to those skilled in the art from this disclosure.

As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a process, product, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such process, process, article, or apparatus. Further, unless expressly stated to the contrary, “or” refers to an inclusive or and not to an exclusive or. For example, a condition A or B is satisfied by any one of the following: A is true (or present) and B is false (or not present), A is false (or not present) and B is true (or present), and both A and B are true (or present).

Additionally, any examples or illustrations given herein are not to be regarded in any way as restrictions on, limits to, or express definitions of, any term or terms with which they are utilized. Instead these examples or illustrations are to be regarded as being described with respect to one particular embodiment and as illustrative only. Those of ordinary skill in the art will appreciate that any term or terms with which these examples or illustrations are utilized encompass other embodiments as well as implementations and adaptations thereof which may or may not be given therewith or elsewhere in the specification and all such embodiments are intended to be included within the scope of that term or terms. Language designating such non-limiting examples and illustrations includes, but is not limited to: “for example,” “for instance,” “e.g.,” “in one embodiment,” and the like. Furthermore, while the example of an LED with a sapphire substrate is used, embodiments can apply to other optical devices that utilize a substrate to guide or gather light and use other substrate materials including, but not limited to, silicon carbide, glass, diamond or other substrate material known or developed in the art.

Reference is now made in detail to the exemplary embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, like numerals will be used throughout the drawings to refer to like and corresponding parts (elements) of the various drawings.

Various methods can be used to shape a substrate material into in the substrate portion of an optical device or the substrate portions of multiple optical devices. Each substrate portion can be shaped to be within an acceptable tolerance of the desired shape. However, many shaping methods leave the sidewalls with small defects, a frosted glass appearance or other features that scatter light, cause refraction or otherwise reduce reflection. Accordingly, the substrate material can be polished using various polishing methods.

The substrate material can be provided for polishing as a portion of a wafer that has been shaped into substrate portions for multiple optical devices or as a substrate portions for a single optical device. In one embodiment, the unpolished substrate portion of each optical device corresponds to a substrate portion having an exit face, a set of sidewalls and an interface. The exit face can have a select size and the sidewalls can be shaped and positioned to cause at least a majority of rays having a straight transmission path from the interface to that sidewall to reflect to the exit face with an angle of incidence at the exit face at less than or equal to a critical angle at the exit face. However, the unpolished sidewalls may reduce reflection so that the desired amount of reflection is not achieved by the unpolished sidewalls. Various polishing methods can be applied to polish the sidewalls to a desired degree of polish. Additionally, the polishing methods can shape the sidewalls to bring the substrate material to within a closer tolerance of the desired shape.

Thus, shaping and polishing methods can thus be applied to bring a substrate material to within a manufacturing tolerance of a select substrate shape with a select degree of polish. FIGS. 1-8B and the accompanying discussion describe various embodiments of optical devices with shaped substrates. Once the desired substrate shape is determined, the shaping and polishing methods can shape the substrate accordingly.

Embodiments of shaped substrate LEDs may be shaped so as to increase or shape the light emission from the LED. According to one embodiment, the substrate is shaped so that all or a supermajority of the light generated by the quantum well region of the LED is transmitted out the exit face of the substrate of the LED. To this end, the exit face can be sized to take into account principles of conservation of radiance. In one embodiment, the exit face may be the minimum size that allows all or a supermajority of the light entering the substrate through the interface between the quantum well region and the substrate (that is, the interface to a non-substrate layer that receives light generated in the light emitting region) to exit the exit face, thereby combining the desire to conserve radiance with the desire to reduce size, particularly the size of the exit face. Additionally, the sidewalls of the substrate may be shaped so that reflection or total internal reflection (“TIR”) causes light beams incident on substrate sidewalls to reflect towards the exit face and be incident on the exit face with an angle less than or equal to the critical angle. Consequently, light loss due to TIR at the exit face is reduced or eliminated. In a further embodiment, to insure that light striking a sidewall is reflected within the substrate and does not pass through the sidewall, a sidewall or sidewalls of a substrate may also be coated with a reflective material that reflects light to prevent the exitance of light through the sidewall.

While the etendue equation shows that theoretically 100% of the light that passes from the quantum well region of the LED into the substrate of the LED can exit the substrate through the exit face, various embodiments may cause lesser amounts of light to exit the exit face while still providing significant improvements over prior LED light emissions. For example, light emitted from the exit surface of the LED may be emitted from the exit surface with a cone half angle of 10-60 degrees with approximately 79% efficiency (there is approximately a 21% efficiency loss due to fresnel losses for a silicon carbide substrate material of 2.73 index of refraction) with a desired intensity profile, exitance profile or other light output profile.

Fresnel losses (e.g. losses at the interface between two mediums such as at the exit face of an LED and air or other medium) occur when light traverses from a medium of higher index to a medium of lower index. Normal incident fresnel losses are described by the equation:


(N1−N2)2)/((N1+N2)2),

wherein N1 and N2 are the indices of refraction of the two mediums. As an example, for an LED having a silicon carbide substrate, N1=2.73 (approximate IOR of silicon carbide), N2=1 (approximate IOR of air), yielding Fresnel losses of approximately 21.5%. If the LED utilizes GaN in the quantum well region, Fresnel losses at the interface between the quantum well region (N1=2.49) and the silicon carbide substrate (N2=2.73) will be 0%. Fresnel losses at the exit face to air interface may be reduced or overcome with anti-reflective coatings.

The size of the exit face of an LED substrate can be selected to conserve radiance. The passage of light along an optic path, either within a single medium or from one medium to another, is governed by the law of Conservation of Radiance, also referred to as the Brightness Theorem, which is expressed by the Etendue equation:

Etendue Equation : Φ 1 N 1 2 A 1 Ω 1 = Φ 2 N 2 2 A 2 Ω 2 [ EQN . 1 ]

Φ1=light flux (lumens) of region 1
N1=IOR of medium of region 1
A1=area of entrance to region 1
Ω1=solid angle (steradians) that fully contains the light of region 1
Φ2=light flux (lumens) of region 2
N2=IOR of medium of region 2
A2=area of entrance to region 2
Ω2=solid angle (steradians) that fully contains the light of region 2

The area of the exit face of a shaped substrate can be selected to conserve radiance of light entering the substrate from the quantum wells for a desired half angle. Consequently, light can be emitted in a desired half angle with high efficiency. This is unlike traditional LEDs that both emit light with a half angle that is undesirable for many applications, therefore requiring additional optical devices to shape the light; and, emit a significant percentage of light through the sidewalls because the exit face is not large enough to conserve radiance; while also suffering absorption losses due to the light never escaping the substrate.

Furthermore, the passage of light from a medium of one index of refraction to a medium of a different IOR is governed by Snell's Law. Snell's law defines the relationship between the angle of approach of a light ray as measured from the normal to the interface surface, and the angle of departure of that ray from the interface, as a function of the indices of refraction of both media.


Snell's Law:N 1 sin(Θ1)=N 2 sin(Θ2)  [EQN. 2]

Θ1=angle of incidence of ray approaching interface surface
N1=IOR of medium 1
Θ2=angle of refraction of ray departing interface surface
N2=IOR of medium 2

In the case of the passage of light from a medium of higher IOR to a medium of lower IOR, the maximum angle at which a light ray may strike the interface surface between the media and still pass through the interface is called the critical angle. Fundamentally, light originating from the medium of higher IOR must approach the media interface at angles not exceeding the critical angle if the light is to pass through the interface and into the medium of lower IOR. For example, in an LED comprised of a substrate and a quantum well region, the substrate medium and the quantum well medium may form an interface that light generated by the quantum well regions traverses. Rays that approach at angles greater than the critical angle will be reflected back within the medium of higher IOR at the interface between the media and will not pass into the medium of lower IOR. This is referred to as total internal reflection (“TIR”).

In a typical GaN LED, the quantum well region has an IOR of approximately 2.49. When these layers are constructed on a sapphire substrate with an IOR of 1.77, the light that can be transmitted into the sapphire is inherently limited by the application of Snell's law and the Brightness Theorem. For LEDs with a substrate of silicon carbide, which may have an IOR of approximately 2.73, the quantum well region has a lower IOR (e.g. approximately 2.49) than the silicon carbide, and therefore Snell's law does not prohibit any of the generated light from passing into the silicon carbide.

In traditional LEDs, a significant portion of light encountering a substrate to air interface will be trapped in the substrate due to TIR. In some cases, a separate optical device (e.g. a solid plastic dome or lens) is used to increase the IOR of the medium into which light passes from the substrate, reducing TIR in the substrate. These separate optical devices may still suffer from losses due to TIR, and the extraction efficiency of domes remains relatively low. Moreover, the use of a dome requires additional steps in manufacturing after the LED is formed. Embodiments of shaped substrate LEDs, on the other hand, can be shaped to minimize or eliminate light loss due to TIR at the exit face of the substrate. According to one embodiment, the exit face of the substrate can be spaced from the interface with the quantum well region by a distance so that none of the rays with a direct transmission path to the exit face experience TIR at the exit face. Additionally, the sidewalls can be shaped to reflect rays encountering the sidewalls to the exit face with an angle of incidence at the exit face that is not greater than the critical angle, thus allowing all internally reflected rays to exit the exit face of the LED substrate as well.

FIG. 1A is a diagrammatic representation of one embodiment of a LED 20 including a substrate 10 and quantum well region 15 (that may comprise one or more layers or regions of doping). Quantum well region 15 includes a light emitting region 25, typically a compound semiconductor such as InGaN or AlInGaP or GaN, or other quantum well composition. Photons from quantum well region 15 may enter substrate 10 through interface 50. LED 20 can be a wire bond, flip chip or other LED known or developed in the art. In FIG. 1A, both substrate 10 and quantum well region 15 form sidewall 60, sidewall 65 or other sidewalls. In other words, quantum well region 15 is shaped in conformance with substrate 10. In other embodiments, quantum well region 15 may not be shaped but, instead, have straight sidewalls. LED 20 further includes exit face 55 that may be substantially the same shape as, substantially parallel to and substantially rotationally aligned with interface 50 within the tolerance of the manufacturing process. The area of exit face 55 can be chosen to conserve brightness for a desired half angle according to the conservation of radiance (sometimes called the conservation of brightness) equation:

Φ 2 n 1 2 A 1 Ω 1 Φ 1 n 2 2 Ω 2 = A 2 [ EQN . 1 ]

Φ1=light flux traversing interface 50;
Φ2=light flux exiting exit face 55, Φ12 for conservation of brightness;
Ω1=effective solid angle whereby light traverses interface 50;
Ω2=effective solid angle whereby light leaves exit face 55;
A1=area of interface 50;
A2=area of exit face 55;
n1=refractive index of material of substrate 10;
n2=refractive index of substance external to substrate 10 (e.g. air or other medium).

A2 represents the minimum surface area of exit face 55 such that light is conserved per the above equation.

Assume, for example: quantum well region 15 forms a 1 mm square so that interface 50 has an area approximately 1 mm square, n1=1.77, n2=1, Ω1=3, Ω2=1, then A2 must be at least 9.3987 mm2 to conserve radiance (i.e. the minimum size of exit face 55 so that all of the light traversing interface 50 can be emitted from exit face 55 for a desired half angle). While in this example the effective solid angles are given, methods for determining Ω1 and Ω2 for a desired half angle are discussed below in conjunction with FIGS. 6A-6E. It should be noted that the square profile is a rectangular profile with sides of equal length.

A2 according to EQN. 1 is the minimum possible size for a given output cone angle or Emission Half Angle to conserve radiance. Consequently, to conserve radiance, A2 should be at least the size determined from EQN. 1, but may be larger. For example, A2 may be made slightly larger to compensate for tolerances in the manufacturing process, errors in the size or shape of quantum well region 15 or other factors.

In the case where A2 is made larger than the value determined by equation 1, flux will be conserved, but exitance (defined as flux per unit area) may be reduced from the maximum attainable value.

To reduce the area of the exit face, however, it may be preferable that A2 be as small as possible. For example, A2 may be within 5% of the minimum area needed to conserve radiance. If some light power (luminous flux) may be sacrificed, A2 can be smaller than the size dictated by the conservation of radiance. As one example, for one embodiment having a 1 mm by 1 mm square interface 50, exit face 55 can be 2.5 mm2 to 5 mm2 (e.g., 4.62 mm2). As another example, for an embodiment having 0.3 mm×0.3 mm interface 50, exit face 55 can be 0.2 mm2 to 0.5 mm2 (e.g., 0.42 mm2). It should be noted, however, the size ranges provided in the previous examples are provided by way of example only, and various embodiments can have a variety of sizes smaller than or greater than the example ranges. In one embodiment, however, A2 is at least 70% of the value as determined by EQN. 1. Furthermore, the shape of exit face 55 may be different than that of interface 50.

The distance between interface 50 and exit face 55 of substrate 10—referred to as the “height” herein, though the distance may extend in other directions than the vertical—may be selected to reduce or minimize TIR of light rays traveling directly from interface 50 to exit surface 55. TIR occurs when light is incident on the surface with an angle of incidence greater that critical angle, which is defined by:


n 1 sin(θc)=n 2 sin(90)  [EQN. 2]

where n1=IOR of substrate 10;
n2=IOR of the medium external to the exit face of substrate 10 (e.g., air or other substance); and
θc=the critical angle.

For example, if n1=1.77 and n2=1, then θc=34.4 degrees. Accordingly, the height of substrate 10 can be selected to limit the critical angle of rays incident on exit surface 55 to a range between normal to exit surface 55 and less than or equal to the critical angle.

Referring to FIGS. 2 and 3, FIG. 2 is a diagrammatic representation of a set of rays traveling from point 57 incident on a surface 55 (represented as surfaces 55 a, 55 b and 55 c at different distances from point 57). In the example of surface 55 a, some rays (e.g., ray 56) are incident on surface 55 a at greater than the critical angle, causing loss of light due to TIR. In the example of surface 55 b, conversely, some rays that would be incident on surface 55 b at the critical angle or somewhat less than the critical angle (e.g., ray 57) will instead be incident on the sidewalls. Preventing loss of these rays, if desired, can cause the complexity of the sidewall design to increase. Moreover, the additional height requires more room to accommodate the LED (i.e., because the LED is taller). Finally, in the case of surface 55 c, rays at or less than the critical angle are incident on surface 55 c while rays that would be greater than the critical angle on exit surface 55 c instead are incident on the sidewalls. TIR or reflection can be used to direct the rays incident on the sidewalls to exit surface 55 c as discussed below.

The limiting ray for selecting height, according to one embodiment, is the ray that travels the longest straight line distance from interface 50 to exit face 55 and is incident on exit face 55 at the critical angle. There may be more than one ray that can be selected as the limiting ray. In a square or rectangular configuration this is the ray that enters substrate 10 at a corner of interface 50 and travels in a straight line to the diagonally opposite corner of exit face 55 such that the ray would be incident on exit face 55 at the critical angle.

FIG. 3 provides a diagrammatic representation of a top view of substrate 10 and of limiting ray 59 for a square configuration. While in one embodiment the height of substrate 10 is selected to limit the critical angle of rays incident on exit face 55 to a range of between normal to exit face 55 and to less than or equal to the critical angle, other heights can be selected, though the use of other heights may decrease the efficiency of LED 20. In one embodiment, the distance between the interface between the non-substrate layers and the substrate and the exit face of the substrate may be within 5% of the minimum height that causes all rays with a straight transmission path from the interface to the exit face to have an angle of incidence on the exit face at less than or equal to the critical angle.

Returning to FIG. 1A, with selected boundary conditions of the size and shape of interface 50, size and shape of exit face 55, distance between interface 50 and exit face 55, the sidewalls (e.g., sidewall 60, sidewall 65 and other sidewalls) of substrate 10 can be shaped to direct light incident on the inner side of the sidewalls to exit face 55 to produce a desired light output profile (e.g., an intensity profile, exitance profile or other light output profile). While for most applications the desired intensity profile is uniform or close to uniform, other distribution profiles can be achieved by varying the height and shapes of the sidewalls.

Broadly speaking, the sidewall shapes are determined so that any ray incident on a sidewall is reflected to exit face 55 and is incident on exit face 55 at the critical angle or less (i.e., so that there is no loss due to internal reflection at exit face 55). This is shown in FIG. 1A by ray 70 that has angle of incidence 75 relative to sidewall 65 that is greater than θc so that ray 70 is reflected to exit face 55 and has an angle of incidence 80 that is less than or equal to θc. While, in one embodiment, the sidewalls are shaped so that all rays that encounter the inner surface of the sidewalls experience total internal reflection to exit face 55 and are incident on exit face 55 at the critical angle or less, other sidewall shapes that allow some loss can be used.

Turning to FIG. 1B, FIG. 1B is a diagrammatic representation of another embodiment of a LED 20. LED 20 comprises a substrate 10 and a quantum well region 15. Quantum well region 15 includes a light emitting region 25, typically a compound semiconductor such as InGaN or AlInGaP or GaN. Photons from quantum well region 15 may enter substrate 10 through interface 50. In FIG. 1B there may be more losses due to TIR in the quantum well region because the quantum well region is not shaped to appropriately direct light to interface 50 and/or exit face 55. While in the embodiments of FIGS. 1A and 1B, some sidewall shapes may not direct all the light generated by LED 20 out exit face 55, the portion of light not exiting exit face 55 will be emitted from sidewalls 65 and may be emitted near exit face 55, thus allowing for the light generated by LED 20 to be captured usefully.

FIG. 4A is a diagrammatic representation of a cross-section of a model of a LED or a substrate of a LED for determining sidewall shapes. Sidewall shapes can be determined using computer-aided design. A model of the sidewall can be created in a computer-aided design package and simulations run to determine an appropriate sidewall shape.

According to one embodiment, each sidewall can be divided into n facets with each facet being a planar section. For example, sidewall 100 is made of fifteen planar facets 102 a-102 o rather than a continuous curve. The variables of each facet can be iteratively adjusted and the resulting distribution profiles analyzed until a satisfactory profile is achieved as described below. While the example of fifteen facets is used, each sidewall can be divided into any number of facets, including twenty or more facets. In another embodiment, the sidewall can be divided into as few as three facets as described below.

Each facet can be analyzed with respect to reflecting a certain subset of rays within a substrate. This area of interest can be defined as an “angular subtense.” The angular subtense for a facet may be defined in terms of the angles of rays emanating from a predefined point. The point selected can be one that will give rays with the highest angles of incidence on the facet because such rays are the least likely to experience TIR at the facet. In a substrate with a square shaped interface area, for example, this will be a point on the opposite edge of the interface.

According to one embodiment, for a selected A1, A2, and height, the maximum of angle 95 of any ray that will be incident on a given sidewall (e.g., sidewall 100) without being previously reflected by another sidewall can be determined. In this example, ray 110 emanating from point 115 establishes the maximum angle 95 for sidewall 100. If the maximum of angle 95 is 48 degrees and there are 15 facets for sidewall 100, each facet (assuming an even distribution of angular subtenses) will correspond to a 3.2 degree band of angle 95 (e.g., a first facet will be the area on which rays emanating from point 115 with an angle 95 of 0-3.2 degrees are incident, the second facet will be the area on which rays emanating at point 115 with an angle 95 of 3.2-6.4 degrees are incident, and so on).

For each facet, the exit angle, facet size, tilt angle, or other parameter of the facet can be set so that all rays incident on the facet experience TIR and are reflected to exit surface 55 such that they are incident on exit surface 55 with an angle of incidence of less than or equal to the critical angle. The sidewalls can also be shaped so that a ray viewed in a cross-sectional view only hits a side wall once. However, there may be additional reflection from a sidewall out of plane of the section. For a full 3D analysis, a ray that strikes a first sidewall near a corner, may then bounce over to a second side wall, adjacent to the first, and from there to the exit face. A curve fit or other numerical analysis may be performed to create a curved sidewall shape that best fits the desired facets. In FIG. 4A, for example, sidewall 105 is curved rather than a set of planar facets.

To optimize the variables for each facet, a simulated detector plane 120 can be established. Detector plane 120 can include x number of detectors to independently record incident power. A simulation of light passing through the substrate may be performed and the intensity and irradiance distributions as received by detector plane 120 analyzed. If the intensity and irradiance distributions are not satisfactory for a particular application, the angles and angular subtenses of the facets can be adjusted, a new curved surface generated and the simulation re-performed until a satisfactory intensity profile, exitance profile or other light output profile is reached. Additional detector planes can be analyzed to ensure that both near field and far field patterns are satisfactory. Alternatively, the simulation(s) can be performed using the facets rather than curved surfaces and the surface curves determined after a desired light output profile is reached. In yet another embodiment, the sidewalls can remain faceted and no curve be generated.

According to another embodiment, the sidewall shape can be selected based on multiple parabolas with each planer facet representing a linear approximation of a portion of a parabola. For example, FIG. 4B is a diagrammatic representation of a portion 400 of a LED. In FIG. 4B, a hypothetical ray 410 is depicted that emanates from the focus 412 of a parabola 415 and intersects sidewall 420 such that it is reflected off sidewall 420 due to TIR and traverses the substrate to intersect exit face 430 at an exit angle 440 that is less than the critical angle and exits the substrate into air or other medium. As can be seen from FIG. 4B, at the transition from the substrate to air, ray 410 bends as described by Snell's law. Since the tangent point of the sidewall is determined from a parabola and because the ray incident and reflected off the sidewall is in the same medium, the ray will be parallel to the optical axis of the parabola. Thus, light is projected with a half-angle 450. Angular subtenses defining the shape of sidewall 420 may be adjusted such that hypothetical ray 410 reflects off sidewall 420 such that ray 410 traverses exit face 430 with a desired exit angle 440 or projects light with a desired half angle 450.

In one embodiment, when fabricating a sidewall or calculating the angular substense of a sidewall, finer substenses may be used towards the base of the sidewall (i.e. nearer the quantum well region) because the effects of the substense are greater or more acute upon reflection near the base, and thus finer subtenses allow for a sidewall with better TIR properties, whereas further from the base, where the effects of the subtenses are less, the subtenses may be coarser. Thus, facets of a sidewall may be numerically greater towards the base of a shaped substrate LED. In one embodiment, a sidewall may have 20 or more facets, with finer facets at the base of the sidewall, wherein the facets approximate one or more subtenses.

A facet can be a linear approximation of a portion 417 of parabola 415. The parameters of parabola 415 can be adjusted until portion 417 achieves the desired goal of all rays incident on portion 417 reflecting to exit face 430 such that the rays have an exit angle 440 of less than the critical angle. Each facet can be formed from a parabola having different parameters. Thus, a facet for one angular subtense may be based on a parabola rather than an adjoining facet. A 20-facet sidewall, for example, may be based on 20 different parabolas.

FIG. 4C is a diagrammatic representation illustrating that the facets for a sidewall can be defined using a computer program such as Microsoft Excel (Microsoft and Excel are trademarks of Redmond, Wash.-based Microsoft Corporation). The graphing feature in Microsoft Excel can be used to create a graph, shown at 125, of a sidewall shape. The same general shape can be used for each sidewall or different shapes for different sidewalls. A shaped substrate with the specified sidewall shape (or with a curved sidewall shape based on the specified facets) can be analyzed in, for example, Zemax optical design program (Zemax is a trademark of Zemax Development Corporation of Bellevue, Wash.). A computer simulation can be conducted in Zemax to generate a ray trace and an intensity and irradiance distribution profile. If the resulting intensity and irradiance profile has an unsatisfactory distribution or the transmission efficiency of the shaped substrate is too low, the variables of the various facets can be adjusted and the simulations performed again. This process can be automated through the use of a computer program to automatically adjust facet variables.

More specifically, FIG. 4C depicts a spreadsheet 500 that can be utilized to design a sidewall shape as shown in graph 510 through the specification of angular subtenses. Projected half angle column 550 contains a plurality of angles that correspond to projected half angle 450 of FIG. 4B. Exit angle columns 540 a (in radians) and 540 b (in degrees) contain a plurality of exit angles corresponding to exit angle 440 of FIG. 4B. More particularly, all or a subset of the angles in column 540 a may be angles that are less than the critical angle such that light rays intersecting the exit face at those angles traverse the exit face, exiting the substrate. Columns 540 a and 540 b may be utilized to develop parabola focus column 560, containing a plurality of foci defining different parabolas. Angular subtense column 565 contains a plurality of angles (in radians) that define the limits of an angular subtense that can be used in conjunction with parabola focus column 560 to define the shape of a sidewall such that a ray from the quantum well region reflects off the sidewall to exit the exit face at less than the critical angle. Using the values contained in parabola focus column 560 and angular subtense column 565, theta column 570 and radius column 575 can be developed wherein corresponding values in columns 570 and 575 correspond to points on a desired parabola for the angular subtense. In turn, theta column 570 and radius column 575 can be utilized to develop Cartesian coordinates for points on a sidewall (e.g. coordinate transformation columns 577) that approximate the parabola for the angular subtense.

For example, a user can specify the LED size (i.e., the area of the interface between the substrate and quantum well region) and the material index. Using the example of an LED having a size of 1, and an index of refraction 1.77, a row in screen 500 can be completed as follows. The user can specify an exit angle in air (assuming air is the medium in which the LED will operate) in column 550. In the example of the first row, the user has selected 55.3792 degrees. The exit angle in the substrate can be calculated as sin(55.3792/180*π)/1.77 or 0.4649323 radians, column 540 a. Column 540 b can be calculated as a sin(0.4649323)/π*180=27.2058407. The focus of the parabola can be calculated as 1(size)/2* (1+cos(π/2−27.2058407/180*π))=0.732466. Angular subtense column 565 can be calculated based on the number in the next column (representing the relative size of a particular facet) as (90−27.7058047)/20=3.114708. Theta column 570 can calculated using a selected number of facets (in this example 20). For example, in the first row theta is calculated as (90−27.7058407)+3,114708*20=124.5883. The radius of the parabola (column 575) for the first facet can be calculated as 2*0.732466/(1+cos(124.5883/180*π)). The contents of coordinate transformation columns 577 can be calculated as follows for the first row:x=−3.3885* cos(124.5883/180*π)=1.923573; y=−3.3885* sin(124.5883/180*π)=2.789594, X=1.923573*cos(27.7058407/180*π)+2.789594* sin(27.7058407/180*π); Y=2.789594*cos(27.7058407/180*π)−1.923573*sin(27.7058407/180*π)−1(size)/2=1.075452 and Y′=−Y. The X, Y coordinates can then be used as data point inputs for a shape fitting chart in Excel. For example graph 510 is based on the data points in the X and Y columns (with the Y column values used as x-axis coordinates and the X column values used as y-axis coordinates in graph 510). In addition to the X and Y values a starting value can be set (e.g., 0.5 and 0). The shape from graph 510 can be entered into an optical design package and simulations run. If a simulation is unsatisfactory, the user can adjust the values in spreadsheet 500 until a satisfactory profile is achieved.

In one embodiment, when a satisfactory light transmission efficiency and irradiance and intensity profiles are achieved, a LED with a substrate having the specified parameters can be produced. An example of such a LED is shown in FIG. 4D which provides a diagrammatic representation of one embodiment of a LED having a substrate with sidewalls shaped to cause TIR so that rays are reflected from the sidewalls to the exit surface. The shape of each sidewall, in this embodiment, is a superposition of multiple contoured surfaces as defined by the various facets. While a curve fit may be performed for ease of manufacturability, other embodiments can retain faceted sidewalls. While in FIG. 4D, the area of the quantum well region is shown as being square or rectangular, this is by way of illustration and not limitation. For example, the shape of the area of the quantum well region can be any of a variety of shapes, e.g. circular, rectangular, triangular. Likewise, the shape of the exit face of a LED can be any of a variety of shapes, e.g. circular, rectangular, triangular.

Returning to FIGS. 1A and 1B, as described above with regard to FIGS. 1A and 1B, various boundary conditions, particularly the area of exit face 55 of substrate 10, are determined for substrate 10 so that light is conserved. The minimum area of exit face 55 can be determined from EQN. 1 above, which relies on various effective solid angles. Typically, the effective solid angle of light is determined based on equations derived from idealized sources that radiate as Lambertian emitters, but that are treated as points because the distances of interest are much greater than the size of the source. The observed Radiant Intensity (flux/steradian) of a Lambertian emitter varies with the angle to the normal of the source by the cosine of that angle. This occurs because although the radiance (flux/steradian/m2) remains the same in all directions, the effective area of the emitter decreases to zero as the observed angle increases to 90 degrees from normal. Integration of this effect over a full hemisphere results in a projected solid angle value equal to π steradians.

Turning to FIG. 5, assume a sphere 130 of given radius (R) surrounds point source 132 (in this example, point source 132 approximates a Lambertian source at a significant distance). The projected area of a hemisphere of the sphere is πR2 and the projected area of the full sphere is 2πR2. This model can be used to design a LED because an interface between a quantum well region and a substrate can be modeled as a Lambertian emitter such that from any point on a hypothetical hemisphere centered over the interface, a given point on the interface will have the same radiance. The area A3 can be calculated as the flat, circular surface (e.g., surface 136) that is subtended by the beam solid angle of interest using a radius of the circle 134 (Rc) that is the distance from the normal ray to the intersection of the spherical surface. For a given half angle 137 of θ of the beam, Rc is the product of R (the radius of the sphere) and the sine of the angle θ, such that


R c =R*Sin(θ)  [EQN. 3]

The area equals:


A 3 =πR c 2=π(R*Sin(θ))2  [EQN. 4A]

The area A3 is the projected area of the solid angle as it intersects the sphere. The area A3 is divided by the projected area of the hemisphere (Ah=πR2) and the quotient is multiplied by the projected solid angle of the full hemisphere (equal to π) to obtain the projected solid angle Ω, such that:


Ω=π*{projected area of desired solid angle}/(projected area of hemisphere)  [EQN. 4B]

Ω = ( π ) * [ { π ( R * Sin ( θ ) ) 2 } / π R 2 ) ] [ EQN . 4 C ] = π * Sin 2 ( θ ) [ EQN . 5 ]

For interface 50 of FIG. 1, for example, θ is 90 degrees, leading to a projected solid angle of π*Sin2(90)=π, and for the desired half angle of 30 degrees, the projected solid angle is π*Sin2(30)=π/4. Using these values for Ω1 and Ω2 for EQN. 1, A2 can be determined for any half angle.

In the above example, the solid angle is determined using equations derived from a Lambertian source modeled as a point source. These equations do not consider the fact that light may enter a substrate from a quantum well region through an interface that may be square, rectangular, circular, oval or otherwise shaped. While the above-described method can give a good estimate of the solid angle, which can be later adjusted if necessary based on empirical or computer simulation testing, other methods of determining the effective solid angle can be used.

FIGS. 6A-6E describe another method for determining the effective solid angle for a substrate of an LED. FIG. 6A is a diagrammatic representation of one embodiment of an interface 150 and an exit face 155 of a shaped substrate 160 (shown in FIG. 6B) and a hypothetical target plane 156 onto which light is projected. FIG. 6A illustrates examples for a position of an effective source origin 152, central normal 153 and effective output origin 154. For purposes of further discussion, it is assumed that the center of interface 150 is at 0,0,0 in a Cartesian coordinate system. Target plane 156 represents the parameters of the resulting pattern (e.g., size and half angle used by other optics). According to one embodiment, the half angle at the diagonal (shown as α1 in FIG. 6B) is the starting point. For example, if the desired light at target plane 156 has a maximum half angle of 30 degrees, α1 for a square- or rectangular-faced substrate is 30 degrees. The half-angle within shaped substrate 160 (labeled β1 and also shown in FIG. 6C) can then be determined according to:


n 2 Sin(α1)=n 1 Sin(β1)  [EQN. 6]

where n1 is the IOR of shaped substrate 160;
n2 is the IOR of the material (typically air) into which the light is projected from shaped substrate 160;
α1 is the half angle at the exit face in the medium external to the substrate (typically air);
β1 is the desired half angle in the substrate.

For example, if the desired half-angle α1 is 30 degrees, and a shaped substrate having an IOR of 1.77 is projecting into air having an IOR of 1, then β1=16.41 degrees. A similar calculation can be performed for a ray projecting from a point on the long and short sides of entrance face 150. For example, as shown in FIGS. 6B and 6C, α2 and β2 can be determined for a ray traveling from the center of one edge on interface 150 to the center of the opposite edge of exit face 155. (The critical angle is the same at 16.41, but β1 is not the same as β2 β2 is determined by the geometry of the sides and the height of the shaped substrate.)

Using the angles calculated, the location of an effective point source can be determined. For a square interface 150, of length l1, the effective point source will be located X=0, Y=0 and

Z eps = l 1 2 * tan ( β 1 ) [ EQN . 7 ]

Where Zeps is the distance the effective point source is displaced from entrance face 150 of shaped substrate 160.

The X, Y and Z distances from the effective point source to points F1 and F2 can be calculated assuming F1 intersects a sphere of unity radius according to:


X F1=cos(ψ1)sin(β1)  [EQN. 8]


Y F1=sin(ψ1)sin(β1)  [EQN. 9]


Z F1=cos(β1)  [EQN. 10]


XF2=0  [EQN. 11]


Y F2=cos(ψ2)*sin(β1)  [EQN. 12]


Z F2=cos(β1)  [EQN. 13]

where ψ1 is the angle of the diagonal ray in the X-Y plane (45 degrees for a square) and where ψ2=90 degrees for a ray projecting from the middle of a side parallel to the X axis as shown in FIG. 6C. As shown in FIG. 6A, because 156 intersects the spherical surface at four points and the magnitude of angle β2 is less than the magnitude of critical angle β1, the values for point F2 are calculated based on the projection of a diagonal with an angle β1 onto the plane of the side ray. A similar methodology based on the geometries previously calculated can be used to determine other points (e.g., for example, the location of points T1 and T2 can be determined based on the location of points F1 and F2 and the desired half angle of light at target plane 156.)

FIG. 6D illustrates the diagonal rays and one ray from the short side projected onto a sphere 159 for exit face 155 and sphere 161 for target plane 156. For exit face 155, the projection of the intersection of the edge rays at the sphere 159 onto the plane of the exit face 155, forms elliptical segments. Likewise, the projection of the refracted exit rays at the edge of the target face intersects the sphere 161. FIG. 6E, for example, points out the circular intersection of the rays lying in the plane formed by the edge 163 of target face 156 intersecting sphere 161 (shown at 162), and the projection of that intersection onto the target plane 156 (shown at 164). By calculating the area of each of the elliptical segments surrounding the square of the target face and adding that to the area of the target face, we find the total projected area of the target face. The effective solid angle can be determined for the target plane using EQN. 4B Similarly, by using sphere 159 and the elliptical segments formed thereon by rays, the effective solid angle for the LED can be determined. For example, the total projected area is determined as described above and inserted as “projected area of desired solid angle” in EQN. 4B.

As one illustrative example, using the above method to project light with a half-angle of 30 degrees using a LED having a substrate with a square shaped interface and exit face yields an effective solid angle of 0.552 steradians to the target in air. By contrast, the use of the traditional circular projected area with a 30 degree half angle projection specification would yield an effective solid angle of 0.785 steradians. When these values are then used in EQN. 1, for given IORs and flux, the traditional (circular) calculation yields a required exit area that is undersized by about 30%. If one were to design a system using this approach, the applicable physics (i.e. the conservation of radiance) would reduce the light output by 30% over the optimum design. Conversely, using the corrected effective solid angle described above calculates an exit face area that will produce 42% more light output than is achievable with the circular calculation.

Although particular methods of determining the effective solid angle for a LED are described above, any method known or developed in the art can be used.

Alternatively, the minimum surface area to conserve light can be determined empirically. Moreover, while the minimum surface area calculations above assume light is entering the substrate across the entire surface of the interface between the non-substrate layer and the substrate, in physical devices, light may not enter the substrate in an even distribution across the entire surface of the interface. The calculations of the minimum area of the exit face can be adjusted to account for the actual distribution of light traversing the interface, rather than being based entirely on the size of the area of the interface. In one embodiment, the actual area of the interface through which light enters the substrate can be used as A1.

Embodiments of LEDs can project light into a desired cone angle of 10-60 degrees with a theoretical efficiency of up to 89% (meaning that 89% of the light entering the substrate is emitted in the desired half-angles with 11% fresnel loss) depending on substrate material and Fresnel losses. The efficiency can be 100% without fresnel losses. Even at only 70% efficiency, embodiments of LEDs provide greater efficiency than other LED technologies, while also allowing for uniform or near uniform intensity distributions at both near and far fields.

Fresnel losses at the substrate to air (or other medium) interface can be overcome by the application of anti-reflective coatings to the exit face of the substrate. Anti-reflective coatings that can be used are any that would be known to one of ordinary skill in the art and include single layer MgO or MgF, multilayer coating or other anti-reflective coatings. Through the utilization of anti-reflective coatings, Fresnel losses can be reduced or eliminated, increasing the light output efficiency of a LED.

An embodiment of a LED may have more than one exit face. For example, a shaped substrate may allow substantially all the light generated by the LED to exit the LED, but through more than a single exit face. FIG. 7 is a diagrammatic representation of an example of a LED 700 with more than one exit face. In FIG. 7, exit faces 710 a and 710 b of LED 700 are shown. A LED having more than one exit face might emit light into a solid angle greater than a hemisphere. To maximize the light exiting the exit faces, the sidewalls of a substrate with more than a single exit face may have multiple curved or faceted surfaces.

For a LED with two or more exit faces, it is possible for the solid angle of emission of the LED to be greater than a hemisphere (and the projected solid angle to be greater than pi). An example of this would be if instead of a single planar exit face, the LED had a four sided pyramidal set of exit faces. If the sidewalls of the substrate of the LED are shaped to direct light entering the substrate through the interface to one of the four exit faces so as to strike the exit face at an angle not greater than the critical angle, then all the light entering the substrate may exit the LED through one of the four exit faces.

Since the faces of the pyramid are not in a plane, but rather are at angles to each other, any ray that strikes an exit face at the critical angle to that exit face will refract to an exit angle of 90 degrees. The total solid angular space defined this way would then be a function of the angular relationship of the four exit faces. To satisfy the etendue equation, the four exit faces in this example would have to have a total surface area at least equal to the calculated value using the effective solid angle for that construction.

This multi-exit face construction may still be constructed in such a way as to conserve radiance. That is, by making the total projected exit face area equal to the calculated value, and by designing the sidewalls to provide uniform distribution of the light to each portion of the exit faces, radiance can be conserved. If the exit faces are made larger than the required value, then light entering the substrate may exit through the exit faces, with a corresponding reduction in luminous intensity.

A further embodiment of a shaped substrate with multiple exit faces is one in which the sidewalls of the shaped substrate are themselves exit faces. Depending on a point of entrance of a given light ray, it may strike a given sidewall at an angle not greater than the critical angle, and pass through that sidewall, or it may strike at an angle greater than the critical angle and be internally reflected to another face or sidewall.

If the sidewall exit faces and sidewalls are designed such that any ray entering the substrate from any point on the interface passes through a sidewall exit face, then all of the light entering the substrate will exit the substrate.

Shaped substrate LEDs with multiple exit faces may be appropriate for use in general lighting applications where broad area emission is desired. Such LEDs may be used in conjunction with additional lens or reflector elements that will direct light produced by the LED into a smaller solid angle.

The potential benefit of a shaped substrate with multiple exit faces or in which sidewalls act as exit faces is that the LED may have a smaller volume or may have a shape that is more readily manufactured—such as planar faces instead of curved surfaces.

LEDs can be arranged in an array of LEDs. An array of LEDs can be used to produce a desired amount of light and a desired light pattern. For example, LEDs may be arranged in a square or other shape. Using an array of LEDs to produce the desired amount of light may be more efficient or may consume less space than using a single LED. An array of LEDs can be formed during manufacture. For example, an array of LEDs can be formed from the same wafer. In FIG. 8A, LED array 800 comprises LEDs 810 a-810 c that are formed from the same wafer. Wafer material 820 is removed to form LEDs 810 a-810 c. LED 810 a remains attached to LED 810 b at point 830 a. Likewise, LED 810 b remains attached to LED 810 c at point 830 b. Thus, through the selective removal of substrate material, arrays of LEDs may be formed. FIG. 8 represents one method of forming arrays of LEDs and is illustrative and not limiting: other methods for forming arrays of LEDs as would be known to one skilled in the art are within the scope of the invention.

One advantage of using an array of LEDs is that the shaped substrates of the multiple LEDs in the array may be thinner than the shaped substrate for a single LED having the same amount of light output. Additionally, an array of smaller LEDs may be more efficient than a single LED; that is, an array of smaller LEDs that consume a certain amount of input power may produce more light than a single large LED of the same exit face size and input power.

One or more methods may be used to shape or form an LED or the substrate of an LED (or other optical device). The methods can be used on various substrate materials including sapphire, silicon carbide, glass, or other substrate materials. Prior to shaping or polishing a substrate material, a wafer or die including the substrate material can be prepared for shaping. Generally, preparing the die for shaping can include mounting the substrate to a support structure that can act to hold the various optical devices together once formed, provide structural support during manufacturing and/or act as sacrificial layer that can be damaged during manufacture. The support structure can be made on any suitable material, which can depend on the shaping method used. Examples of support structures include glass, epoxy, sapphire, silicone or other material layer bonded to the substrate with epoxy or other adhesive materials. Examples of adhesives include, but are not limited to, Valtron AD4010-A/AD4015-B Heat Release Epoxy System (MP4010A/1015B-50) by Valtech Corporation of Sanatoga, Pa., Liofol UR 9640 by Henkel Corporation of Rocky Hill, Conn. or other adhesive. The addition of a metalized layer to either the substrate material or support structure can improve adhesion strength. For example, a 1 micron thick coating of evaporated Ti may be applied to either the substrate material or support structure to promote adhesion. Other metal layers include, but are not limited to, Titanium-Tungsten (TiW) or other layer of material that can promote adhesion.

Preparation can also include adding one or more layers of protective material to protect any metal or electric layers from damage by abrasives, chemicals, or tools. The protective layer can be selected so that the shaping process can shape the substrate material through the protective layer. According to one embodiment, the protective layer can be a resilient thermoplastic that will adhere to the outermost layer of the wafer. The material of the protective layer can be chosen based on the manufacturing methods to be employed, time constraints, and other factors. For example, a relatively tacky protective layer may be suitable for a wire saw shaping method, but may gum up an ultrasonic shaping tool. Examples of materials that can be used as protective layer include Cookson Staystik 393 bonding adhesive and other thermoplastics. The thickness of the protective layer can depend on material used in the protective layer and manufacturing process parameters. In other embodiments, the wafer can be prepared in other manners or be left unprepared.

As described in U.S. patent application Ser. No. ______, entitled “Optical Device Shaping”, by Winberg, filed on the same date as this application, which is hereby fully incorporated by reference herein, various methods can be used to shape a substrate material to within an acceptable tolerance of a desired shape. While the sidewalls of a substrate portion of an optical device may be positioned and shaped to reflect a select amount of light to the exit face, the shaping methods may leave the sidewalls of the optical device with an unpolished surface having the look of frosted glass or other characteristic that causes light to scatter and reduces or prevents reflection. Consequently, the sidewalls may require polishing to promote internal reflection. Consequently, the sidewalls can be polished to a selected degree of polish that can depend on the amount of light loss that is acceptable. As some examples, the sidewalls can be polished to have roughness average of approximately 100 nanometers, approximately 50 nanometers or approximately 20 nanometers.

According to one embodiment, the sidewalls can be polished using ultrasonic polishing. FIG. 9 is a diagrammatic representation of one embodiment of polishing a set of optical devices formed from a die 900. In the embodiment of FIG. 9, the wafer is mounted to a support layer 902 using, for example, an adhesive layer 904. Support layer 902 can provide structural support during shaping and polishing and can be comprised of any suitable material including glass, epoxy or other material. In other embodiments the support layer is not used.

A polishing tool 910 can be inserted in a channel 914 between substrate sidewalls 916 and 918. Additional polishing tools or sections of the same polishing tool can also be inserted in parallel channels to allow for parallel polishing. Polishing tool 910 can be formed of a suitable material such as wood, polymer, liquid crystal polymer (such as Vectra liquid crystal polymer), metal or metal alloys (e.g., tin, brass or other metal or metal alloy) or other material. Polishing tool 910 can be shaped corresponding to the sidewall on one or both sides of channel 914 and, if inflection points are present, shaped to fit into the inflection points. Polishing tool can be sized to allow sufficient room for abrasive slurry 922 to fit between polishing tool 910 and the substrate material.

Abrasive slurry can be introduced between tool 910 and the sidewalls. Abrasive slurry 922 can include any appropriate slurry of liquid and abrasive particles. By way of example, but not limitation, abrasive slurry 922 can be deionized water, deionized water and glycol mix or other carrier material with abrasive particles, such as diamond or other material. According to one embodiment, the particles have an average size of less than 20 microns. For example, abrasive slurry 922 can include particles that are approximately 4 microns or less in size. In other embodiments, the particles can be as small as 1 micron or less. The abrasive particles can make up a selected percentage of abrasive slurry 922. In various embodiments, the percentage of abrasive particles can range from 5 to 30% of abrasive slurry 922.

To prevent abrasive slurry 922 from removing electrical or metal layers from the wafer, a cover 924 or other structure can be placed over portions of the optical devices to protect those layers during polishing. Cover 924 can include guide channel 926 for polishing tool 910. In other embodiments, the metal or electrical layers of the optical devices can be protected by a protective coating as discussed above. Cover 924 can also act to restrain die 900 during polishing.

In operation, polishing tool 910 is vibrated on the channel 904 at a selected frequency, typically in the ultrasonic domain. For example, polishing tool 910 can be vibrated at approximately 20 kHz with a peak-to-peak amplitude of approximately 10-20 microns. It should be noted, however, that the cited frequency and amplitude are provided by way of example and not limitation and other frequencies and amplitudes can be used. In other embodiments the frequency can be on the order of 60-100 Hz and the amplitude of several millimeters. When multiple polishing tools are used, the multiple tools can be vibrated en masse to polish along multiple channels at a time.

Flushing steps to remove abrasive particles and particles of substrate material can occur during polishing or can interrupt polishing. In other embodiments, flushing does not occur. Abrasive and removed particles can flow along the base of channel 914 if there is adequate space during polishing and flushing.

When polishing is complete in one direction, either the wafer or tool can be rotated and polishing completed in the perpendicular direction (or other direction if the LEDs are not square or rectangular). Polishing can occur in multiple passes using the same or different grits of abrasive particles and tools.

FIGS. 10A and B are diagrammatic representation of another embodiment of polishing a set of shaped optical devices formed from die 1000. In the embodiment of FIG. 10A, the wafer from which the optical devices are formed is mounted to a support layer 1002 using, for example, an adhesive layer 1004. Support layer 1000 can be formed of any suitable material. Support layer 1000 provides structural support during shaping and polishing. In other embodiments a support layer is not used.

An ultrasonic driver 1005 can be coupled to a polishing wand 1012. Ultrasonic driver 1005 can be any suitable driver that can vibrate polishing wand 1012 to reciprocate with a selected frequency, including, for example, commercially available ultrasonic oscillators used in metal cleaning tools. In one embodiment, ultrasonic driver 1005 can be mounted to a frame that allows translation and rotation of ultrasonic driver 1005. Linear actuators and servos can be used to control the motion of driver 1005. Die 1000 can also be placed on a work surface that can translated and rotated. In one embodiment, linear motion of the work surface and of driver 1005 is controlled by actuators or motors with a resolution of 0.0005 inches and a precision of 0.0001 inches and rotation is controlled to a desired resolution.

Polishing wand 1012 can be made of any suitable material including, but not limited to wood, polymer, liquid crystal polymer (such as VECTRA liquid crystal polymer), tin, metal alloy or other material. The portion of polishing wand 1012 that contacts the sidewalls of an optical device (e.g. sidewall 1014) can be straight, tapered, shaped to match the sidewalls or otherwise shaped. The width of polishing wand 1012 can be selected to cover a portion of a side of a single optical device, the entire side of a single optical device or to span multiple optical devices.

In the embodiment of FIG. 10 a, abrasive slurry 1016 is introduced to channel 1018. By way of example, but not limitation, abrasive slurry 1016 can be deionized water, deionized water and glycol mix or other carrier material with abrasive particles, such as diamond or other material, having a size of less than 20 microns, including abrasive particles on order of 10 microns or less. Other embodiments the particles can be as small as 1 micron or less. The abrasive particles can make up a selected percentage of abrasive slurry 1016. In various embodiments, the percentage of abrasive particles can range from 5 to 30% of abrasive slurry 1016. The percentage of abrasive particles and fluids can be based on process parameters such as substrate material, particle material, wand material, frequency, amplitude and other factors.

By way of example but not limitation, four examples of abrasive slurry 1016 can be 1) 50% by weight of 6 micron diamond powder in a carrier fluid of 65-90% Water and 10-35% Propylene Glycol; 2) 20% by weight of 6 micron diamond powder in a carrier fluid of 70-90% Propylene Glycol and 5-30% Methyl Alcohol; 3) 25% by weight of 3 micron diamond powder in a carrier fluid of 70-90% Propylene Glycol and 5-30% Methyl Alcohol; 4) 25% by weight of 1 micron diamond powder in a carrier fluid of 70-90% Propylene Glycol and 5-30% Methyl Alcohol. Different slurries can be used at different stages of polishing. According to one embodiment, for example, examples 1 and 2 can be used for coarse polishing and example can be used for medium polishing and example 4 for fine polishing. According to a particular embodiment, coarser example 1 can be used further away from the quantum well layers of the wafer and example 2 can be used closer to the quantum well layers. One example of a slurry having 65-90% water and 10-35% propylene glycol is, for example, Allied 90-30025 Polycrystalline Diamond Suspension by Allied High Tech. Products, Inc. (Allied) of Rancho Dominguez California. One example of a carrier material having 70-95% propylene glycol and 5-30% methyl alcohol is Red Lube by Allied. One example of diamond powders are Hyprez diamond powders by Engis Corporation of Wheeling, Ill.

The manner in which abrasive slurry 1016 is introduced can depend on thickness of abrasive slurry 1016. For example, wafer 1000 can be submerged in abrasive slurry 1016, abrasive slurry be sprayed on wafer 1000 or allowed to flow down channel 1018 as wand 1012 polishes, abrasive slurry 1016 can be applied as a coat to the sidewalls to be polished, or applied in another manner.

According to one embodiment, a cover 1024 or other structure can be placed over portions of the optical devices to protect the metallic layers during polishing. Cover 1024 can include a slot 1026 or other opening to allow polishing slurry 1012 access to channel 1018. The opening 1026 in cover 1024 can be tapered to allow the wand to pivot in channel 1018. In other embodiments, the metal or electrical layers of the optical devices can be protected by a protective coating as discussed above. Cover 1024 can also act to restrain die 1000 during polishing.

In operation, polishing wand 1012 can be aligned relative die 1000. This can be done, for example, using a camera 1028 that locates marks at known locations on die 1000 to determine the position and orientation of the die relative to wand 1012. This can be done by a human operator or with the assistance of image processing software. Camera 1028 can provide any desired resolution, and in particular embodiments provides a resolution of 1 micron per pixel or better. As an example, camera 1028 can be a Basler ½, C-Mount 1392×1040, 18.7 fps, Mono, CCD from Basler Inc. of Exton, Pa. Once in a desired location and orientation, driver 1005 and/or wafer 1000 can be moved so that wand 1012 is at a location in channel 1018. Wand 1012 can also be rotated and moved relative to wafer 1000 so that wand 1012 presses against a sidewall at a selected angle.

The rate of polishing can be affected by various factors including the substrate material, abrasive slurry 1016 composition, wand 1012 material, the force applied by wand 1012, operating characteristics of wand 1012 such as stroke, and other factors. In general, the force applied should be enough to allow polishing but not dislodge the devices being polished and can vary depending on the angle of wand 1012. According to one example embodiment, approximately 50-200 grams can be applied for a VECTRA wand that contacts between 5 and 15 mm of surface length (not including gaps). In a particular embodiment, 100 g of force is applied to press wand 1012 against a sidewall. It should be noted, however, that an amount of force outside of the range noted above can be used as needed or desired to achieve a desired polishing rate and can be adjusted for the contact length, material of the wand and substrate, composition of slurry 1016, operating characteristics of wand 1012 or other factors.

Polishing wand 1012 is vibrated in channel 1018 at a selected frequency, such as a frequency in the ultrasonic domain. By way of example, but not limitation, the wand can move at a frequency of 20-30 kHz with a travel of 10 to 20 microns. It should be noted, however, that the cited frequency and amplitude are provided by way of example and not limitation and other frequencies and amplitudes can be used.

Polishing wand 1012 can polish a section of sidewall 1014 and then move along channel 1018 to polish corresponding sections of other devices. Polishing wand 1012 can then be repositioned at a different angle and again moved along channel 1018 to polish additional sections of 1014 and the sidewalls of other optical devices. Polishing wand 1012 can be repositioned at any number of increments through a desired number of degrees. For example, polishing wand 1012 can be angled every 0.25 degrees, 0.5 degrees, 1 degree or multiple of degrees or other increment through a desired range of angles. If the range of angles is, for example, 0 degree to 27 degrees from the vertical, the polishing wand can be angled at each degree (0, 1, 2, 3, 4 . . . 27) resulting in 28 passes along channel 1018 to polish sidewall 1014 and the corresponding sidewalls of other optical devices along channel 1018. While the example of 0-27 degrees is used, the range of angles can be any range based on the desired shape of the substrate material.

In another embodiment, polishing wand 1012 can be swept through a range of angles in one position. Using and example in which range of angles is 1-35 degrees, polishing wand 1012 can sweep through the entire range of angles degrees as it polishes sidewall 1014 and then move down channel 1018 to polish the corresponding sidewall of other optical devices. In other cases, polishing wand 1012 can sweep through a subset of the range. For example, polishing wand 1010 can make one pass down channel 1010 sweeping through 1-10 degrees, another pass sweeping through 10-25 degrees and another pass sweeping through 25-35 degrees. The angle of polishing wand 1012 can be controlled through a pivoting connection, flexible connection or other connection with ultrasonic driver 1005 or by pivoting ultrasonic driver 1005.

According to one embodiment, when the polishing for channel 1018 is complete, the next street can be polished. This may require movement of cover 1024. In other cases, cover 1024 may have opening to expose multiple channels 1024 and have multiple sections as needed. According to one embodiment all the streets in a given direction will be polished, then the wafer or wand 1012 rotated 90 degrees (for square or rectangular optical devices) and the orthogonal streets polished.

The embodiment of FIGS. 10A and 10B shows a single exposed channel and single polishing wand. In another embodiment multiple streets may be exposed at the same time and multiple wands may be used to polish multiple streets at the same time. If cover 1024 is used in such an embodiment, it can include openings for multiple channels. Ultrasonic driver 1005 can be coupled to any number of wands 1012 or separate drivers 1005 can be used for each wand 1012.

The embodiment of FIGS. 10A and 10B also indicates the polishing wand being vibrated in a direction tangent to the curved surface of the sidewall. When the shapes are being created with either a grinding wheel, wire saw or other shaping method, artifacts of the cutting action are typically produced that run mostly in a direction parallel to the street direction (like strata in geologic formations). Using a polishing direction as shown in FIGS. 10A and 10B, the wand polishes across these artifacts, tending to reduce the height of them and producing a polished surface with a curve more accurately made to the desired substrate shape. In other embodiments, the wand can vibrate in the direction along the rows (into and out of the page of FIGS. 10A and 19B), in an orbital pattern (in circles against the sidewall) or other pattern to polish the sidewalls.

FIGS. 11A-C are diagrammatic representations of embodiments various wand shapes for wand 1012. Wand 1012 can have an end proximate to driver 1005 and a distal end used for polishing the sidewalls. The proximal end can have any suitable shape and features to allow wand 1012 to couple to driver 1005. Wand 1012 can have the same thickness along the majority of its length as shown in FIG. 11A. In another embodiment, wand 1012 can have a tapered profile as shown, for example, in FIG. 11B. While both surfaces 1104 and 1106 are angled in this embodiment. In other embodiments only a single surface is angled. Furthermore, the taper may not extend to the tip of wand 1012, but may terminate sooner to leave a tip of generally constant thickness. This may be preferable as a tip that is too thin may bend too much during polishing causing uneven polishing. FIG. 11C illustrates a side view of another embodiment of wand 1012 that has a first section 1110 of a first thickness that transitions into a polishing section 1112 of a second thickness. This embodiment provides the advantage of allowing wand 1012 to be relatively stiff while allowing some flex in the polishing section 1112. It should be noted that the foregoing are provided by way of example and any suitably shaped polishing wand 1012 can be used.

According to another embodiment, a particle jet can be used to polish substrate material. FIG. 12 is a diagrammatic representation of particle jet ablation. In the embodiment of FIG. 12, a die 1200 can be mounted to a support structure as discussed above. A source 1204 can provide a stream of particles 1206 that impinge on sidewall 1208 to polish sidewall 1208. In this embodiment, the jet velocity, jet flow rate, jet direction and cross sectional size and shape may be adjusted to achieve uniform polishing action across an area of interest. The particle stream can be directed through moving the nozzle or, in the case of magnetic particles, manipulating magnetic fields.

Multiple passes can be made to polish the sidewalls at higher angles. The size of the particles can be selected to create a sidewall shape having a specified smoothness. For example, particles can be less than 20 microns or other selected size. According to one embodiment successive passes can be made using smaller particles for finer polishing. Thus, for example, a pass can be made using particles with an average size of 10 microns, then 6 microns, then 1 micron and so on.

A cover 1240, protective layer or other mechanism can be used to protect areas of the wafer from the stream of particles 1206. Cover 1240 can have openings spaced to allow particles to impinge on wafer 1200 while protecting the electrical areas of the optical devices being polished. In addition to providing protection, cover 1240 can be used to restrain wafer 1200 in the tool.

Yet another embodiment for polishing is the use of Reactive Ion Etching. FIG. 13 is a diagrammatic representation of one embodiment of Reactive Ion Etching. As shown in FIG. 13, a wafer 1300 can be mounted to a support structure 1302 using an adhesive layer 1304. A cover 1304, protective layer or mask can protect selected regions of wafer 1300. An ion stream 1310 formed from a process gas is directed using electrical fields to flow onto the area to be polished. Any method of producing an ion stream that can etch the substrate material known or developed in the art can be employed. Depending on the various process parameters, the ion stream can polish the sidewalls of one or more rows at a time.

In other examples, the substrate may be shaped only partially down through the thickness of the wafer, leaving the optical devices connected near their exit faces. The sidewalls can be polished using any of the various methods described above to the point of connection. The devices can then be separated using, for example, a dicing saw. The final cut surface can then be polished using any of the above described methods including, for example, abrasive slurry jet. This can result in closer spacing allowing more optical devices to be shaped from a single wafer.

While this disclosure describes particular embodiments, it should be understood that the embodiments are illustrative and that the scope of the invention is not limited to these embodiments. Many variations, modifications, additions and improvements to the embodiments described above are possible. For example, while the above methods of polishing have been described individually, the above methods may be combined. As another example, the various ranges and dimensions provided are provided by way of example and methods and optical devices may be operable within other ranges using other dimensions. Moreover, while shaped substrates have been described in regard to sapphire and silicon carbide, other substrates that allow the passage of light may be used. For example, substrates may be made of glass or diamond. In one embodiment, substrates may be molded from moldable glass, providing a cost effective and easily shaped substrate. It is contemplated that these variations, modifications, additions and improvements fall within the scope of the invention as detailed in the following claims.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7789531 *1 Oct 20077 Sep 2010Illumitex, Inc.LED system and method
US8087960 *1 Oct 20073 Jan 2012Illumitex, Inc.LED system and method
WO2011091400A2 *25 Jan 201128 Jul 2011Illumitex, Inc.Method for protecting optical devices during manufacture
WO2012007392A1 *8 Jul 201119 Jan 2012Osram Opto Semiconductors GmbhRadiation-emitting component
Classifications
U.S. Classification451/36, 451/37, 451/41
International ClassificationB24B1/00, B24C1/00
Cooperative ClassificationH01L33/60, H01L33/58
European ClassificationH01L33/58
Legal Events
DateCodeEventDescription
19 Mar 2010ASAssignment
Owner name: ILLUMITEX, INC.,TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WINBERG, PAUL N.;DUONG, DUNG T.;THOMAS, MATTHEW R. AND OTHERS;SIGNED BETWEEN 20100216 AND 20100223;US-ASSIGNMENT DATABASE UPDATED:20100322;REEL/FRAME:24111/947
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WINBERG, PAUL N.;DUONG, DUNG T.;THOMAS, MATTHEW R.;AND OTHERS;SIGNING DATES FROM 20100216 TO 20100223;REEL/FRAME:024111/0947
14 Sep 2009ASAssignment
Owner name: ILLUMITEX, INC., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WINBERG, PAUL N.;DUONG, DUNG T.;THOMAS, MATTHEW R.;AND OTHERS;REEL/FRAME:023230/0866;SIGNING DATES FROM 20090821 TO 20090826