US20090212843A1 - Semiconductor device arrangement and method - Google Patents
Semiconductor device arrangement and method Download PDFInfo
- Publication number
- US20090212843A1 US20090212843A1 US12/036,823 US3682308A US2009212843A1 US 20090212843 A1 US20090212843 A1 US 20090212843A1 US 3682308 A US3682308 A US 3682308A US 2009212843 A1 US2009212843 A1 US 2009212843A1
- Authority
- US
- United States
- Prior art keywords
- power transistor
- gate
- source
- connecting point
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 238000000034 method Methods 0.000 title claims abstract description 22
- 230000003071 parasitic effect Effects 0.000 claims description 11
- 230000005669 field effect Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 4
- 230000000295 complement effect Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 description 14
- 108091006146 Channels Proteins 0.000 description 10
- 238000001465 metallisation Methods 0.000 description 6
- 230000010355 oscillation Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 5
- 238000006073 displacement reaction Methods 0.000 description 4
- 239000008186 active pharmaceutical agent Substances 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000011144 upstream manufacturing Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
- H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
- H03K17/0412—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
- H03K17/04123—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6877—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the control circuit comprising active elements different from those used in the output circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
Abstract
A semiconductor device arrangement and a method. One embodiment includes at least one power transistor and at least one gate resistor located between a gate of the power transistor and a connecting point in the drive circuit of the power transistor. The semiconductor device arrangement includes a switchable element between the connecting point and a source of the power transistor.
Description
- This disclosure relates to a semiconductor device arrangement with at least one power transistor and at least one gate resistor, the power transistor having an extremely high switching speed owing to very low device capacitances. In the turn-off process, the so-called decommutation process, however, current and voltage overlap in the power transistor. To minimize any turn-off losses resulting from this, it is possible to turn off the channel current very fast by small external gate series resistors.
- Turn-off losses can also be reduced by using the output capacitance Ca as a turn-off unloading capacitor. In this process, the load current commutates completely into the output capacitance Ca. As a result, the semiconductor device suffers virtually no heat losses in the turn-off process, but only a capacitive displacement current into the output capacitance Ca with an energy content ECa of
-
- wherein uDS represents the rising drain-source voltage in the turn-off process. From this can be derived the capacitive energy content of the semiconductor device in the off state at a voltage UDS. This energy content can be minimized by reducing the value of the output capacitance Ca while reducing the size of the component.
- In a switching process modified as described above by using the output capacitance Ca, the voltage increase during the turn-off process is however no longer controlled by the gate, but only by the load current IL to be disconnected. The voltage increase du/dt is determined by the load current IL in a linear manner and is inversely proportional to the output capacitance Ca with
-
du/dt=I L /Ca (equation 2), - Wherein IL represents the load current and Ca represents the output capacitance of the power transistor.
- By reducing the dimensions of the device, the output capacitance Ca is reduced to a very low value, so that at high current peaks the voltage increase du/dt reaches values which may significantly exceed the permissible breakdown voltage. Owing to the intrinsic structure of the semiconductor devices, the output capacitance Ca is voltage-dependent, so that, based on the
above equation 2, the value of Ca changes as du/dt increases during the turn-off process. This change causes both a change of the capacitive displacement current for the output capacitance Ca and a change of the capacitive displacement current at the gate electrode. - In a non-linear condition, i.e. if there are parasitic inductances in the drive circuit, the change of the gate current induces a reverse voltage and may result in oscillations, in particular if the exciting voltage, is amplified by the power transistor. This results in an upper limit frequency via the charge of the input capacitance of the power transistor and the through-conductivity of the power transistor. In high-voltage devices, this may be significantly lower than the inherent resonance of the serial oscillator circuit made up of the drain-gate capacitance and the gate inductance. Oscillations during the turn-off process of such power transistors are undesirable, as they affect the EMC (electromagnetic compatibility) of the power transistor.
- The fast and, with the aid of the output capacitance, nearly loss-free switching of power transistors is further limited by a very high current chopping in the power circuit. If the power transistor is turned off in a completely unloaded state, the load current completely commutates into the output capacitance Ca. In this process, the gate voltage may fall below the Miller plateau at full load current and even be reduced to zero. The Miller plateau is the potential at the insulated gate which still ensures that the channel of a field effect power transistor remains open.
- If the power transistor as a switch reaches the externally preset link voltage, the switch can supply the load current. The di/dt resulting from this will cause a voltage reduction at the power transistor via the existing source inductances and, if the gate potential remains constant, contribute to an effective biasing of the channel. It has however been found that, owing to the capacitive coupling between gate and source, the gate potential follows a steep voltage reduction to source, resulting on the one hand in an incomplete biasing of the channel and on the other hand in an excessively high voltage amplitude at the gate.
- In combination with the gate inductances, the rapid voltage change at the gate due to the capacitive coupling between gate and source also excites undesirable oscillations. Both effects are due to the inductances existing in a power transistor between the control electrode and a switching electrode. Such inductances are built up by the conductor routing to the gate connections of the power transistor within the semiconductor device and in part by the connecting elements forming induction loops between external contacts of the semiconductor device arrangement and the internal contact surfaces on the semiconductor chip of the power transistor.
- For these and other reasons, there is a need for the present invention.
- One embodiment provides a semiconductor device arrangement with at least one power transistor and at least one gate resistor located between a gate connection and a connecting point, wherein a further switchable element is provided between the connecting point and the source of the power transistor. There are parasitic inductances between the connecting point and the source of the power transistor. The switchable element is located between the connecting point and the source of the power transistor and at steep switching edges bridges the inductances between the connecting point and the source.
- The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
-
FIG. 1 illustrates the principal layout of one embodiment. -
FIG. 2 illustrates a Boolean truth table explaining the switching function of a switchable element. -
FIG. 3 illustrates a diagrammatic cross-section through a switchable element according to one embodiment. -
FIG. 4 illustrates a principal configuration according to one embodiment. -
FIG. 5 illustrates is a diagrammatic cross-section through a switchable element according to one embodiment. -
FIG. 6 illustrates a diagrammatic top view of the switchable element according toFIG. 5 . -
FIG. 7 illustrates a diagrammatic cross-section through a switchable element according to one embodiment. -
FIG. 8 illustrates the principal layout of one embodiment. -
FIG. 9 illustrates a principal equivalent circuit diagram of a semiconductor device arrangement according to one embodiment. -
FIG. 10 illustrates a diagrammatic cross-section through a switchable element of a semiconductor device arrangement according to one embodiment. -
FIG. 11 illustrates an operational amplifier as a further switchable element of one embodiment. -
FIG. 12 illustrates a schematic sketch of a semiconductor device arrangement according to one embodiment. - In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
- It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.
-
FIG. 1 illustrates a principal layout of one embodiment. This circuit includes a semiconductor device arrangement 1 with a power transistor TH and a gate resistor RG located between a gate G of the power transistor TH and a connecting point H in a drive circuit of the power transistor TH. Aswitchable element 2 is provided between the connecting point H and a source S of the power transistor TH. Thisswitchable element 2 is configured such that it meets the requirements of the Boolean truth table illustrated inFIG. 2 . -
FIG. 2 is a Boolean truth table explaining the switching function of theswitchable element 2 according toFIG. 1 . The left-hand column of the Boolean truth table lists states or phases of the power transistor TH. The second column lists the voltage values of the connecting point H, with h being high and l being low. The third column lists the corresponding conditions at the gate G of the power transistor TH, likewise with h being high and l being low. The fourth column finally lists the switching states of the switchable element for a first option, wherein the switchable element is switched on both in the turn-off phase and in the off state of the power transistor TH. The fourth column also illustrates a second option, wherein theswitchable element 2 fromFIG. 1 only completes the circuit in the turn-off phase of the power transistor TH, connecting the connecting point H to the source S of the power transistor TH. -
FIG. 3 is a diagrammatic cross-section through a switchable element according to one embodiment. This switchable element is suitable for option 1 of the Boolean truth table according toFIG. 2 . For this purpose, the switchable element has been integrated into thebody zone 7 of the power transistor TH as an n-type depletion MOSFET 41. - For this purpose, a highly doped n+-
type zone 32 is introduced into thebody zone 7 of the power transistor TH, and this n+-type zone 32 is contacted by the connecting point H according toFIG. 1 . Between this n+-type zone 32 with the contact H and an n+-type source zone 33 of the source S of the power transistor TH, a lightly doped n−-type near surface zone is implanted as adepletion channel 34. This near-surface zone of adepletion channel 34 is controlled by a gate G4 at source potential of the power transistor. - With this structure according to
FIG. 3 , an n-type depletion MOSFET is obtained in thebody zone 7 of the power transistor TH, which represents theswitchable element 2 ofFIG. 1 and corresponds to option 2 of the Boolean truth table according toFIG. 2 . This function may for example be obtained by ensuring that the n-type depletion channel MOSFET has a negative threshold voltage which is less than Vth of the power transistor TH with the configuration: source contact S4 of the switchable element at H, gate contact G4 of the switchable element at S of the power transistor TH and drain contact D4 of the switchable element at source potential. In this way, the depletion MOSFET switches off automatically as soon as the connecting point H exceeds the negative threshold voltage Vth of the depletion MOSFET 41. - When integrating the switchable element into the power transistor TH according to
FIG. 3 , is has to be taken into account that the p-n junction between thebody zone 7 of the power transistor TH and the n+-type zone 32 contacted by the connecting point H can absorb a reverse voltage of approximately 15 V, so that the limit imposed by Zener breakdown of the p-n junction is only reached at this reverse voltage. In addition, the source S of the power transistor TH contacts both the p-type body zone 7 and the n+-type source zone 33, while the gate electrode G4 of the switchable element is at source potential of the power transistor TH. -
FIG. 4 illustrates a principal configuration according to one embodiment. In this configuration, the switchable element is likewise integrated into a body zone of the power transistor and designed as a junctionfield effect transistor 42. With a configuration of this type, the first option of the Boolean truth table fromFIG. 2 can be implemented according tocolumn 5. -
FIG. 5 is a diagrammatic cross-section through aswitchable element 2 according to one embodiment. The cross-section corresponds to the embodiment illustrated inFIG. 3 , but owing to a very shallow n-implantation near the surface of thebody zone 7 of the power transistor TH, there is no need for an additional gate connection G4 as illustrated inFIG. 3 . As soon as H, during the turn-off process because of the external control component or a gate driver, converges from a positive voltage to 0 V, the lightly dopeddepletion channel 34 becomes conducting and H therefore stops at source potential. Conversely, the channel goes into a pinch-off state during the turn-on process, as soon as H goes to a positive voltage relative to the p-well contacted by the source. The next figure illustrates the implementation of such an integration of a switchable element asJFET 42 into thebody zone 7 of the power transistor TH. -
FIG. 6 is a diagrammatic top view of theswitchable element 2 according toFIG. 5 . To make the structure more clearly visible, the metallization has been omitted. This top view illustrates a section of the p-type body zone 7 of the power semiconductor, the n+-type source zone 33 in the upper region being bounded by a broken line. Individual contact holes 35 establish the contact with the source metallization not illustrated in the drawing, and the shallow n−-type implantation zone between the source zone S and the connecting point H is represented by individual strips extending from the n+-type zone 33 to the n+-type zone 32 of the connecting point H. - Contact holes 36 are also provided on the side of the connecting point H to establish a connection between the metallization of the connecting point H and the n+-type zone located below. The wider stripes illustrated in
FIG. 6 are related to the p-type body zone 7 of the power transistor and are connected to the source metallization via further contact holes 35′. This JFET structure allows for a self-cutoff characteristic, wherein in the p-type well 7 of the body zone of the power transistor, between the source S and the connecting point H, a shallow n-type implantation is introduced which, as mentioned above, is quickly depleted by the RESURF effect of the p-type well 7 located below, as soon as the connecting point H is once again restored to a voltage which may be below the threshold voltage of the power transistor. - This n−-type region connecting S and H is depleted by the small lateral p-type strips connected to S as illustrated in
FIG. 6 . The embodiments illustrated inFIGS. 5 and 6 are subject to the condition that the n-p junction from the n−-type region of the connecting point H to the surrounding p-type well 7 of the power transistor has to be designed for a reverse voltage capability which corresponds at least to the maximum permissible gate voltage of the power transistor. -
FIG. 7 is a diagrammatic cross-section through aswitchable element 2 according to one embodiment. In this case, theswitchable element 2 is integrated asJFET 42 into the gate electrode structure. For this purpose, the metallization of the connecting point H is bonded to the polysilicon of the gate supply lines throughvias 37 as illustrated inFIG. 7 . The gate resistor RG as illustrated inFIG. 1 can be created by suitable meander structures of thepolysilicon line 38. At the same time, but separate from this line to the gate resistor, the gate G4 of a JFET structure, which is electrically connected to the source S of the power transistor TH, can be contacted. - For this purpose, the gate resistor RG between the connecting point H and the gate G of the power transistor TH is ideally designed as an integrated gate resistor. As illustrated in
FIG. 7 , a connection to the connecting point H is established using a gate bond, so that the gate poly located below can be contacted from this point and meander to the gate of the power transistor TH, from where it is routed into the gate ring and the rest of the gate electrode not illustrated in the drawing. - If a
JFET 42 is to be integrated towards the source, a contact has to be established between the gate poly and the source S, which, as illustrated inFIG. 7 , can be produced on agate oxide 23 or on afield oxide 39. This however requires the separation of the gate poly around the source contacts illustrated inFIG. 6 , as there would otherwise be a short circuit to the gate electrode, which would prevent the switching-on of the transistor. In other words, the source S contacts a small piece of the n-p poly material separated from the rest of the gate electrode and only connected to the rest of the n-type gate poly structure via theJFET 42. -
FIG. 8 illustrates switchable elements for the implementation ofoption 2 incolumn 5 of the Boolean truth table according toFIG. 2 . As the connecting point H has not only to be held at source potential in the turn-off phase of the power transistor, but this bridge also has to be maintained in the off state, an additional switching transistor TS is used to take over the function of the switchable element according toFIG. 1 ; this may for example be installed into a control IC for the power transistor. -
FIG. 8 illustrates the layout of a further one embodiment of the invention, wherein the switching transistor TS is driven by an AND gate with an inverted input E1. The signals required for this purpose may for example be generated by a control IC, which offers particular advantages if the power transistor is at least partially designed as a package together with a part of the drive circuit or with the whole control IC. -
FIG. 9 is an equivalent circuit diagram of a semiconductor device arrangement 1 according to one embodiment. The semiconductor device arrangement 1 includes a power transistor TH, which may for example be used in a half bridge circuit as a low side switch (LSS). This power transistor TH has agate connection 14 as a gate G of a semiconductor chip. Between thegate connection 14 and the connecting point H, such semiconductor device arrangements are provided with a gate resistor RG, across which a voltage differential builds up while the insulated gate is loaded or unloaded. The gate is loaded or unloaded via acontrol line 16 connecting the connecting point H to theoutput 17 of adriver circuit 18. - The power transistor TH further includes a drain D, which may for example be at the potential to be switched, and a source S, which approximately adopts the potential to be switched as the power transistor TH switches through. When the power transistor TH switches off, the source S is reset to its low starting potential. Owing to a capacitive coupling between the gate G and the source S, the gate potential follows the source potential by using capacitive displacement currents, in one embodiment a turn-off phase, when the
driver output 17 applies a turn-off signal ΔV to the connecting point H. In order to suppress any oscillation in this turn-off phase, aswitchable element 2 is located between the connecting point H and the source S; this is controlled via agate connection 14 and uses the voltage differential across the gate resistor RG to bridge any parasitic inductances present in the main transistor TH between gate and source in the turn-off phase. - As a result, the parasitic inductances are virtually short-circuited in the turn-off phase of the power transistor TH and oscillations are suppressed without increasing switching losses and without affecting the switching speed of the power transistor TH.
- For this purpose, the
switchable element 2 according to one embodiment illustrated inFIG. 9 includes two n-channel MOS transistors T1 and T2 with body diodes B1 and B2 which block anti-serially, with the result that the parasitic inductances between the connecting point H and a source S are bridged as the gates G1 and G2 are triggered only in the turn-off phase at a suitable voltage differential across the gate resistor RG. The gates G1 and G2 of the transistors T1 and T2 are for this purpose connected to the gate G of the power transistor TH. - The drains D1 and D2 of the transistors T1 and T2 form a switching node K. The source S1 of the first transistor T1 is connected to the connecting point H, while the source S2 of the second transistor T2 is electrically connected to the source S of the power transistor TH. Any oscillations caused by parasitic inductances between the connecting point H and the source S of the power transistor TH are thereby prevented. For this purpose, the connecting point H is electrically connected to the switching node K via the first body diode B1, while the source S of the power transistor TH is electrically connected to the switching node K via the body diode B2 of the second transistor T2 of the
switchable element 2. - A method for the production of a semiconductor device arrangement 1 with a
switchable element 2 in the drive circuit includes the following process steps. First, a power transistor TH with parasitic inductances between a connecting point H and a source S and a gate resistor RG between the connecting point H and a gate G of the power transistor TH is provided. Aswitchable element 2 is then produced to bridge the inductances between the connecting point H and the source S in the turn-off phase of the power transistor at a steep switching edge ΔV. To produce aswitching element 2 operating like this, a first and a second n-type channel MOSFET T1 and T2 are first produced in asemiconductor body 12 with a common gate G1,2 and a common drain D1,2, their first and second body diodes B1 and B2 being anti-serially connected to one another. - The common gate G1,2 can now be connected to the gate G of the power transistor TH, the first source S1 of the first MOSFET T1 can be connected to the connecting point H and the second source S2 of the second MOSFET T2 can be connected to the source S of the power transistor TH. If the power transistor TH is a lateral FET, the first and second n-channel MOSFETs T1 and T2 can be monolithically integrated into the
semiconductor body 12 of this FET. - In power transistors TH with a vertical FET structure, a separate semiconductor device is produced as a
switching element 2, its metallization 29 on theback side 4 being mounted on the source S of the power transistor TH in the form of astacked semiconductor chip 13. In this case, theswitchable element 2 supports on a p-type substrate 5 the first and second n-channel MOSFETs T1 and T2, the common drain D1,2 of which, which consists of a n-type semiconductor material 8, being grown epitaxially on thesubstrate 5. The p-n junction 3 between the p—type substrate 5 and the n-type drain region 15 of the transistors T1 and T2 forms a large-area diode PD connected in parallel to the second body diode B2. - This advantageously creates a MOS device which conductively connects the connecting point H upstream of an internal or external gate resistor RG to the source S of the semiconductor device arrangement 1. Ideally, the voltage drop across the gate resistor RG, which results from the difference between the Miller plateau and the reference voltage of the gate control, is utilized. If the switching process is completely load-free and di/dt is limited via the source inductance, this switch does not become active, because the
switchable element 2 between the source S of the power transistor TH and the connecting point H opens as soon as the voltage at the gate G drops below the Miller plateau. This drop below the Miller plateau occurs if the threshold voltage of theswitchable element 2 equals that of the power transistor TH. - IA slightly lower value for the threshold voltage of the
switchable element 2, can be selected in order to allow a reliable closing of theswitchable element 2 at the Miller plateau. Such a configuration would noticeably pull the connecting point H upstream of the gate resistor RG to source potential at the start of the turn-off process, when the input capacitance is discharged to the level of the Miller plateau. It would then remain at source potential during the entire turn-off phase without blocking an effective limitation of di/dt via the source inductance. Implementation in thesemiconductor body 12 is based on the modification of the production masks, the gate structure level, the metal level and the contact hole level. At the end, only one additional level is required for masking the body contact. - In a further possible variant, the
driver circuit 18 would after turn-off, i.e. when thedriver output 17 switches to zero, output a further positive signal to connect the connecting point H to the source S by triggering aswitchable element 2. Such a signal may remain positive for a fixed time or be held at a positive level by the actual gate characteristic. The switchable element of a corresponding semiconductor structure is illustrated in the following figure. -
FIG. 10 is a diagrammatic cross-section through aswitchable element 6 of asemiconductor component arrangement 6 of asemiconductor device 10 according to one embodiment. Thisswitchable element 6 includes an n-channel field effect transistor T3 with a channel K3, a gate G3, a drain D3 and a source S3. While the drain D3 contacts a highly doped n+-type drain zone 27, the source S3 contacts both an n+-type source zone 26 and a p-type base zone 31. If a positive potential is applied to G3, the p-type base zone 31 forms an n-type channel K3 in the p-type well 7 below thegate oxide 23. The p-type well 7 is insulated against the surrounding n-type semiconductor material 8 of theswitchable element 6 via a body diode B3 of a p-n junction 3. - To create a temporary short-circuit between the connecting point H of a power transistor and its source as illustrated in
FIG. 1 in the turn-off phase of the power transistor, a positive signal is applied to the gate G3 of theswitchable element 6. For this purpose, the drain D3 of the power transistor TH is electrically connected to the connecting point, while the source S3 is connected to the source S of the power transistor TH. - As explained above, the driver circuit of the power transistor TH has, to achieve this, to output a further positive signal in the turn-off phase, which is connected to the gate G3 with the
switchable element 6 illustrated inFIG. 4 . Such aswitchable element 6 in the driver circuit of the power transistor TH can be located monolithically on the semiconductor chip of the power transistor, monolithic integration being possible both for lateral MOSFETs and for vertical MOSFETs. - The gate G3 is externally accessible, a complementary driver pulse controlling the gate G3 such that the
switchable element 6 for thesemiconductor device arrangement 10 bridges the inductances between the connecting point H and the source of the power transistor TH at a steep switching edge. For this purpose, a p-type well 7 of theswitchable element 6 is provided in an n-type semiconductor material 8 of thesemiconductor body 12 of thesemiconductor chip 13. - After such a MOSFET T3 has been produced in a
semiconductor body 12, its drain D3 is electrically connected to the connecting point H of the power transistor, its source S3 to the source S of the power transistor TH and its gate G3 to a driver output which supplies a complementary switching signal if there is a steep turn-off edge at the gate G. - In one embodiment, the voltage differential across the gate resistor RG between the gate and the connecting point H is evaluated by an
operational amplifier 11 acting as a switchable element 9 as illustrated inFIG. 11 . Theoperational amplifier 11 generates an amplified signal if the potential at the gate is higher than at the connecting point H. This occurs whenever the power transistor is in a turn-off phase. Theoperational amplifier 11 then outputs a positive amplified signal at its output A, wherein a structure according toFIG. 4 can once again be connected to the output A. This signal is used to connect the connecting point H to the source S of the power transistor TH illustrated inFIG. 1 . For this purpose, theoperational amplifier 11 may either be mounted as a semiconductor device on the semiconductor chip or fitted to the semiconductor chip of the control IC. -
FIG. 12 is a schematic diagram of asemiconductor device arrangement 20 according to one embodiment. Components of the same function as in the preceding figures are identified by the same reference numbers and not explained again. In this embodiment of the invention, anoperational amplifier 11 as briefly mentioned above is used to utilize the voltage differential across the gate resistor RG and apply it to the inputs E1 and E2 of theoperational amplifier 11. For this purpose, the connecting point H is connected to the first input E1 of theoperational amplifier 11 and the gate G of the power transistor TH is connected to the second input E2 of theoperational amplifier 11. - The amplified output signal A is used to drive the gate G3 as illustrated in
FIG. 4 and to connect the connecting point H of the power transistor TH to the source S of the power transistor TH, thus short-circuiting all inductances between the connecting point H and the source S of the power transistor TH in the turn-off phase of the power transistor TH. For this purpose, the connecting point H is connected to the drain D3 of the transistor T3 and the source S of the power transistor TH is connected to the source S3 of the transistor T3 of theswitchable element 6. - Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
Claims (21)
1. A semiconductor device comprising:
at least one power transistor; and
at least one gate resistor located between a gate of the power transistor and a connecting point in a drive circuit of the power transistor,
wherein a switchable element is additionally provided between the connecting point and a source of the power transistor.
2. The semiconductor device of claim 1 , wherein the switchable element maintains the connection between the connecting point and the source of the power transistor during a turn-off phase of the power transistor.
3. The semiconductor device of claim 1 , wherein the switchable element maintains the connection between the connecting point and the source of the power transistor during a turn-off phase and during an off state.
4. The semiconductor device of claim 1 , wherein the switchable element is a depletion MOSFET with its own gate connection, which is monolithically integrated into a body zone of the power transistor, wherein the gate connection of the MOSFET is electrically connected to the source of the power transistor.
5. The semiconductor device of claim 4 , wherein the drive point forms a source of the n-type depletion MOSFET and the source of the power transistor forms a drain of the n-type depletion MOSFET and the gate contact of the n-type depletion MOSFET is electrically connected to the source of the power transistor.
6. The semiconductor device of claim 1 , wherein the switchable element is a junction field effect transistor monolithically integrated into a body zone of the power transistor, its channel zone being represented by a shallow n-implantation, and wherein the channel zone can be depleted from the p-type region of the body zone.
7. The semiconductor device of claim 1 , wherein the switchable element is a junction field effect transistor structure integrated into the gate structure of the power transistor.
8. The semiconductor device of claim 1 , wherein the switchable element is a switching transistor driven by an AND gate with an inverted input, and wherein the output of the AND gate is electrically connected to the gate of the switching transistor.
9. A semiconductor device arrangement comprising:
a power transistor having a gate;
a connecting point in a drive circuit of the power transistor;
a gate resistor of the power transistor located between the connecting point and the gate; and
wherein a switchable element is located between the connecting point and a source of the power transistor and is connected to the gate such that the parasitic inductances between the connecting point and the source are bridged in the turn-off phase of the power transistor at steep switching edges.
10. The semiconductor device arrangement of claim 9 , wherein the switchable element includes two transistors, having body zones that are arranged such that they block anti-serially.
11. The semiconductor device arrangement of claim 10 , wherein the two transistors have a common gate electrically connected to the gate of the power transistor.
12. The semiconductor device arrangement of claim 10 , wherein the two transistors have drains that form a switching node.
13. The semiconductor device arrangement according to of claim 9 , wherein the switchable element is installed as a monolithically integrated component into a lateral field effect power transistor.
14. A semiconductor device arrangement comprising:
a connecting point of a power transistor;
a gate of the power transistor;
a gate resistor of the power transistor located between the connecting point and the gate; and
a drive circuit, wherein a switchable element in the drive circuit is monolithically integrated into the power transistor and comprises a gate which is externally accessible and which can be controlled by a complementary driver pulse such that the parasitic inductances between the connecting point and a source of the power transistor are bridged by means of the switchable element at a steep switching edge.
15. The semiconductor device arrangement of claim 14 , wherein the switchable element comprises a source and a drain and the drain is electrically connected to the connecting point while the source is connected to the source of the power transistor.
16. The semiconductor device arrangement of claim 14 , wherein a p-type well of the switchable element is provided in an n-type semiconductor material of the power transistor.
17. A semiconductor device arrangement comprising:
a connecting point of a power transistor;
a gate of the power transistor;
a gate resistor of the power transistor located between the connecting point and the gate; and
a drive circuit, wherein a switchable element in the drive circuit includes an operational amplifier, having first and second inputs electrically connected to the connecting point and to the gate of the power transistor respectively, and the output of which is electrically connected to the gate of the switchable element, so that parasitic inductances between the connecting point and a source of the power transistor are bridged by means of the switchable element at a steep switching edge.
18. A method for the production of a semiconductor device arrangement with a switchable element in the drive circuit, comprising:
providing a power transistor with parasitic inductances between a connecting point and a source and with a gate resistor between the connecting point and the gate;
producing a switchable element which, at a steep switching edge, bridges the inductances between the connecting point and the source in a turn-off phase of the power transistor.
19. The method of claim 18 , wherein a first and a second n-channel MOSFET are first produced in a semiconductor body with a common gate and a common drain, their first and second body diodes being connected back to back.
20. The method according to of claim 19 , further comprising:
connecting the common gate to the gate of the power transistor;
connecting the first source of the first MOSFET to the connecting point; and
connecting the second source of the second MOSFET to the gate of the power transistor.
21. The method according to of claim 18 , further comprising:
providing a lateral FET as a power transistor; and
monolithically integrating the first and second n-channel MOSFETs into the semiconductor body of the FET.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/036,823 US20090212843A1 (en) | 2008-02-25 | 2008-02-25 | Semiconductor device arrangement and method |
US12/873,902 US8427207B2 (en) | 2008-02-25 | 2010-09-01 | Semiconductor device arrangement and method |
US13/799,641 US8643406B2 (en) | 2008-02-25 | 2013-03-13 | Semiconductor device including a power transistor and switchable element |
US14/148,757 US8917120B2 (en) | 2008-02-25 | 2014-01-07 | Semiconductor device having a switchable element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/036,823 US20090212843A1 (en) | 2008-02-25 | 2008-02-25 | Semiconductor device arrangement and method |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/873,902 Division US8427207B2 (en) | 2008-02-25 | 2010-09-01 | Semiconductor device arrangement and method |
US12/873,902 Continuation US8427207B2 (en) | 2008-02-25 | 2010-09-01 | Semiconductor device arrangement and method |
Publications (1)
Publication Number | Publication Date |
---|---|
US20090212843A1 true US20090212843A1 (en) | 2009-08-27 |
Family
ID=40997694
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/036,823 Abandoned US20090212843A1 (en) | 2008-02-25 | 2008-02-25 | Semiconductor device arrangement and method |
US12/873,902 Active 2028-04-27 US8427207B2 (en) | 2008-02-25 | 2010-09-01 | Semiconductor device arrangement and method |
US13/799,641 Active US8643406B2 (en) | 2008-02-25 | 2013-03-13 | Semiconductor device including a power transistor and switchable element |
US14/148,757 Active US8917120B2 (en) | 2008-02-25 | 2014-01-07 | Semiconductor device having a switchable element |
Family Applications After (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/873,902 Active 2028-04-27 US8427207B2 (en) | 2008-02-25 | 2010-09-01 | Semiconductor device arrangement and method |
US13/799,641 Active US8643406B2 (en) | 2008-02-25 | 2013-03-13 | Semiconductor device including a power transistor and switchable element |
US14/148,757 Active US8917120B2 (en) | 2008-02-25 | 2014-01-07 | Semiconductor device having a switchable element |
Country Status (1)
Country | Link |
---|---|
US (4) | US20090212843A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110140179A1 (en) * | 2009-12-16 | 2011-06-16 | Mitsubishi Electric Corporation | Semiconductor device |
US20110260774A1 (en) * | 2010-04-27 | 2011-10-27 | Rf Micro Devices, Inc. | High power fet switch |
US20140220749A1 (en) * | 2011-08-02 | 2014-08-07 | Nxp B.V. | A vertical mosfet transistor with a vertical capacitor region |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090212843A1 (en) * | 2008-02-25 | 2009-08-27 | Infineon Technologies Ag | Semiconductor device arrangement and method |
US8455948B2 (en) * | 2011-01-07 | 2013-06-04 | Infineon Technologies Austria Ag | Transistor arrangement with a first transistor and with a plurality of second transistors |
GB2488778B (en) * | 2011-03-07 | 2013-03-20 | Amantys Ltd | Voltage balancing for power switching devices |
US8482029B2 (en) * | 2011-05-27 | 2013-07-09 | Infineon Technologies Austria Ag | Semiconductor device and integrated circuit including the semiconductor device |
US9978862B2 (en) | 2013-04-30 | 2018-05-22 | Infineon Technologies Austria Ag | Power transistor with at least partially integrated driver stage |
US9799643B2 (en) | 2013-05-23 | 2017-10-24 | Infineon Technologies Austria Ag | Gate voltage control for III-nitride transistors |
US10103258B2 (en) | 2016-12-29 | 2018-10-16 | Texas Instruments Incorporated | Laterally diffused metal oxide semiconductor with gate poly contact within source window |
US10790818B1 (en) * | 2019-09-27 | 2020-09-29 | Infineon Technologies Austria Ag | Slew rate control by adaptation of the gate drive voltage of a power transistor |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5422593A (en) * | 1992-05-12 | 1995-06-06 | Fuji Electric Co., Ltd. | Current-limiting circuit |
US20010017783A1 (en) * | 1998-08-24 | 2001-08-30 | Siemens Aktiengesellschaft | Method and device for controlling a power converter valve that can be turned off and has at least two series circuits |
US20050024122A1 (en) * | 2003-08-01 | 2005-02-03 | Christian Evers | Electronic switch |
US20080266727A1 (en) * | 2007-04-30 | 2008-10-30 | Vacon Oyj | Control of a power semiconductor switch |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4553082A (en) * | 1984-05-25 | 1985-11-12 | Hughes Aircraft Company | Transformerless drive circuit for field-effect transistors |
US4926283A (en) * | 1989-08-30 | 1990-05-15 | Motorola Inc. | Temperature protected transistor circuit and method of temperature protecting a transistor |
DE19619399A1 (en) * | 1996-05-14 | 1997-11-20 | Telefunken Microelectron | Power-FET switching arrangement for vehicle electronics |
US5751180A (en) * | 1996-09-03 | 1998-05-12 | Motorola, Inc. | Electrical device structure having reduced crowbar current and power consumption |
US5798662A (en) * | 1996-12-19 | 1998-08-25 | National Semiconductor Corporation | Low-side driver with gate leakage detection circuitry |
US6043689A (en) * | 1998-03-17 | 2000-03-28 | International Business Machines Corporation | Driver circuit for providing reduced AC defects |
KR20000000632A (en) * | 1998-06-02 | 2000-01-15 | 윤종용 | Comparator having hysteresis |
US7095266B2 (en) * | 2004-08-18 | 2006-08-22 | Fairchild Semiconductor Corporation | Circuit and method for lowering insertion loss and increasing bandwidth in MOSFET switches |
US20090212843A1 (en) * | 2008-02-25 | 2009-08-27 | Infineon Technologies Ag | Semiconductor device arrangement and method |
-
2008
- 2008-02-25 US US12/036,823 patent/US20090212843A1/en not_active Abandoned
-
2010
- 2010-09-01 US US12/873,902 patent/US8427207B2/en active Active
-
2013
- 2013-03-13 US US13/799,641 patent/US8643406B2/en active Active
-
2014
- 2014-01-07 US US14/148,757 patent/US8917120B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5422593A (en) * | 1992-05-12 | 1995-06-06 | Fuji Electric Co., Ltd. | Current-limiting circuit |
US20010017783A1 (en) * | 1998-08-24 | 2001-08-30 | Siemens Aktiengesellschaft | Method and device for controlling a power converter valve that can be turned off and has at least two series circuits |
US20050024122A1 (en) * | 2003-08-01 | 2005-02-03 | Christian Evers | Electronic switch |
US20080266727A1 (en) * | 2007-04-30 | 2008-10-30 | Vacon Oyj | Control of a power semiconductor switch |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110140179A1 (en) * | 2009-12-16 | 2011-06-16 | Mitsubishi Electric Corporation | Semiconductor device |
US8373207B2 (en) * | 2009-12-16 | 2013-02-12 | Mitsubishi Electric Corporation | Semiconductor device |
US20130105866A1 (en) * | 2009-12-16 | 2013-05-02 | Shigeru Kusunoki | Semiconductor device |
US8847290B2 (en) * | 2009-12-16 | 2014-09-30 | Mitsubishi Electric Corporation | Semiconductor device |
US20110260774A1 (en) * | 2010-04-27 | 2011-10-27 | Rf Micro Devices, Inc. | High power fet switch |
US9673802B2 (en) | 2010-04-27 | 2017-06-06 | Qorvo Us, Inc. | High power FET switch |
US10056895B2 (en) * | 2010-04-27 | 2018-08-21 | Qorvo Us, Inc. | High power FET switch |
US20140220749A1 (en) * | 2011-08-02 | 2014-08-07 | Nxp B.V. | A vertical mosfet transistor with a vertical capacitor region |
US9129991B2 (en) * | 2011-08-02 | 2015-09-08 | Nxp B.V. | Vertical MOSFET transistor with a vertical capacitor region |
Also Published As
Publication number | Publication date |
---|---|
US8427207B2 (en) | 2013-04-23 |
US8917120B2 (en) | 2014-12-23 |
US20100327942A1 (en) | 2010-12-30 |
US20140118051A1 (en) | 2014-05-01 |
US20130200939A1 (en) | 2013-08-08 |
US8643406B2 (en) | 2014-02-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8917120B2 (en) | Semiconductor device having a switchable element | |
US9912329B2 (en) | Semiconductor device and driving system | |
JP4485490B2 (en) | MOS gate transistor driver and high voltage MOSFET | |
US7777279B2 (en) | Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of floating offset voltage | |
US8319529B2 (en) | Drive circuit for a voltage control transistor | |
US10263538B2 (en) | Semiconductor device and power conversion device | |
US8093660B2 (en) | Semiconductor device | |
US8547162B2 (en) | Integration of MOSFETs in a source-down configuration | |
US20120182051A1 (en) | Driving circuit for transistor | |
KR20140114411A (en) | Semiconductor arrangement with active drift zone | |
US11522453B2 (en) | Dead-time conduction loss reduction for buck power converters | |
US20080230834A1 (en) | Semiconductor apparatus having lateral type MIS transistor | |
JP5293831B2 (en) | High voltage semiconductor device and drive circuit | |
US8796776B2 (en) | Protection component and electrostatic discharge protection device with the same | |
US7423325B2 (en) | Lateral field-effect-controllable semiconductor component for RF applications | |
US6914297B2 (en) | Configuration for generating a voltage sense signal in a power semiconductor component | |
US20110108882A1 (en) | Semiconductor device internally having insulated gate bipolar transistor | |
US7071516B2 (en) | Semiconductor device and driving circuit for semiconductor device | |
US7492208B2 (en) | MOSFET circuit having reduced output voltage oscillations during a switch-off operation | |
JP2940547B2 (en) | Moss power transistor overvoltage protection device | |
JP5195547B2 (en) | Semiconductor device | |
CN112865531A (en) | Step-down converter circuit, integrated chip, integrated circuit and step-down conversion method | |
US20160104699A1 (en) | Semiconductor apparatus |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DEBOY, GERALD;REEL/FRAME:020934/0611 Effective date: 20080325 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |