US20090200675A1 - Passivated Copper Chip Pads - Google Patents
Passivated Copper Chip Pads Download PDFInfo
- Publication number
- US20090200675A1 US20090200675A1 US12/029,127 US2912708A US2009200675A1 US 20090200675 A1 US20090200675 A1 US 20090200675A1 US 2912708 A US2912708 A US 2912708A US 2009200675 A1 US2009200675 A1 US 2009200675A1
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- Prior art keywords
- layer
- metal levels
- disposed above
- flip chip
- chip package
- Prior art date
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 47
- 239000002184 metal Substances 0.000 claims abstract description 47
- 238000002161 passivation Methods 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000001465 metallisation Methods 0.000 claims description 26
- 229910000679 solder Inorganic materials 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 16
- 239000010949 copper Substances 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 229910052718 tin Inorganic materials 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 230000005496 eutectics Effects 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 229910001316 Ag alloy Inorganic materials 0.000 claims 2
- 238000000034 method Methods 0.000 abstract description 25
- 239000010410 layer Substances 0.000 description 79
- 238000004519 manufacturing process Methods 0.000 description 12
- 230000008569 process Effects 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000004806 packaging method and process Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 239000000203 mixture Substances 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 230000008018 melting Effects 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 229910000978 Pb alloy Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 229910007116 SnPb Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910004353 Ti-Cu Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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Abstract
Description
- This invention relates generally to electronic devices, and more particularly to passivated copper chip pads.
- A flip chip package includes a direct electrical connection of face down (“flipped”) semiconductor components onto substrates or carriers, such as ceramic substrates, or circuit boards. The flip chip semiconductor components are predominantly semiconductor devices, however, components such as passive filters, detector arrays, and MEM devices are also being used in flip chip form. The use of flip chip packaging has dramatically grown as a result of the flip chips advantages in size, performance, flexibility, reliability, and cost over other packaging methods and from the widening availability of flip chip materials, equipment and services.
- Flip chips are advantageous because of their high-speed electrical performance, when compared to other assembly methods. For example, eliminating bond wires reduces the delay in inductance and capacitance of the connection, and substantially shortens the current path resulting in a high speed off-chip interconnection. Flip chips also provide the greatest input/output connection flexibility. Wire bond connections are generally limited to the perimeter of the chip or die, driving the die sizes up as a number of connections have increased over the years. Flip chip connections can use the whole area of the die, accommodating many more connections on a smaller die. Further, flip chips are amenable to 3-D integration by stacking over other flip chips or other components.
- For almost 25 years, the semiconductor industry has rolled out a new generation of technology that has delivered improved performance at lower costs. One of the challenges faced in semiconductor manufacturing relates to reduction in process costs with each subsequent technology generation. Consequently, packaging processes also need to reduce fabrication costs with each technology generation. Hence, what are needed in the art are improved structures and methods for producing flip chip packages at lower costs.
- These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by embodiments of the present invention which provide flip chip and methods of manufacture thereof.
- Embodiments of the invention include methods and structures of passivated copper chip pads. In accordance with an embodiment of the present invention, the structure includes a substrate comprising active circuitry, and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in the sidewalls of a trench disposed in the passivation layer, wherein the conductive liner is also disposed over an exposed surface of the last level of the metal levels.
- The foregoing has outlined rather broadly the features of an embodiment of the present invention in order that the detailed description of embodiments of the invention that follows may be better understood. Additional features and advantages of embodiments of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
- For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
-
FIG. 1 illustrates a chip with a flip chip package; -
FIG. 2 illustrates an embodiment of a chip with a flip chip package; -
FIG. 3 , which includesFIGS. 3 a-3 k, illustrates a flip chip package at various stages of fabrication, in embodiments of the present invention; -
FIG. 4 illustrates a flow chart of a method of formation of the flip chip package, in accordance with an embodiment of the invention illustrated inFIG. 3 ; -
FIG. 5 , which includesFIGS. 5 a-5 g, illustrates a flip chip package at various stages of fabrication, in accordance with an embodiment of the present invention; and -
FIG. 6 illustrates a flow chart of a method of formation of the flip chip package, in accordance with an embodiment of the invention illustrated inFIG. 5 . - Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.
- The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
- The present invention will be described with respect to preferred embodiments in a specific context, namely formation and design of flip chip packaging. The invention may also be applied, however, to other semiconductor components comprising, for example, other packaging such as wirebond packaging, embedded wafer level packaging, and ball grid array packaging. One of ordinary skill in the art will be able to recognize further examples as well.
- Formation of flip chip packaging requires use of many lithographic steps for formation of the different levels of the package. This requires the use of expensive masks and lithography tools that increase the cost of the process. In various embodiments, the present invention overcomes these limitations by reducing the number of mask steps or number of masks needed in the fabrication of flip chips packages. Various embodiments of the invention achieve this by avoiding pad metallization or formation of chip bonding pads over the last metal level. Avoiding this process eliminates mask steps not only in their formation, but also mask steps in forming passivation layers above these chip bonding pads.
- A structural embodiment of the invention will be first described using
FIG. 2 . Various embodiments of the method of fabrication will then be described using the flow charts ofFIGS. 4 and 6 , andFIGS. 3 and 5 . -
FIG. 1 illustrates a conventional structure comprising analuminum pad metallization 2 disposed on asubstrate 1. The aluminum pad metallization 2 (also called the chip bonding pad) is disposed above, for example, alast metal line 100 from the last level of metallization, thelast metal line 100 being disposed in adielectric layer 10. Apassivation layer 131 covers thelast metal level 100 and a portion of an exposed top surface of thealuminum pad metallization 2 to form a via over thealuminum pad metallization 2. The via forms a pad opening for subsequent formation of asolder ball 190. An underbump metallization layer 170 is disposed above thepassivation layer 131. Asolder ball 190 is disposed above the underbump metallization layer 170. - An embodiment of the invention is illustrated in
FIG. 2 . Thesubstrate 1 includes adielectric layer 10. Thesubstrate 1 may be a wafer such as a silicon wafer or other substrates such as a Ge wafer, SOI wafer, or <110> Si on <100> Si substrate. Alast metal line 100 from the last level of metallization is embedded in thedielectric layer 10. Acap layer 120 is disposed above thelast metal line 100 and thedielectric layer 10. Thecap layer 120 comprises an insulating material. Apassivation layer 130 is disposed above thecap layer 120. Thepassivating layer 130 comprises an insulating material. Anoptional insulating liner 140 is disposed above thepassivation layer 130. Atrench 150 is disposed in the stack comprising thecap layer 120, thepassivation layer 130, and the optional insulatingliner 140. Aconductive liner 160 is disposed above and on thelast metal line 100. Theconductive liner 160 also is disposed on the sidewalls of thetrench 150. A under bump metallization layer (UBM)layer 170 is disposed on theconductive liner 160. Asolder ball 190 is disposed on the underbump metallization layer 170. Compared to prior art, embodiments of the invention do not use chip bonding pads (aluminum pad metallization 2 inFIG. 1 ). Rather, theUBM layer 170 directly contacts the last level of metallization passivated by theconductive liner 160. - A method of fabricating the flip chip package is now described in
FIG. 3 and in the flow chart ofFIG. 4 , in accordance with an embodiment of the invention. Referring toFIG. 3 a, acap layer 120 is deposited over thelast metal line 100 anddielectric layer 10. Thelast metal line 100 is the top most level of the metallization on the substrate 1 (lower metal levels are not shown). The substrate 1 (e.g., a silicon wafer) includes active circuitry as well as necessary features such as isolation regions. Thelast metal line 100 preferably comprises copper. Thedielectric layer 10 preferably comprises an oxide or any other suitable materials. For example, thedielectric layer 10 may comprise FTEOS, SiN, SiCOH, or other low-k materials. Thecap layer 120 is typically a nitride, although other suitable materials (such as SiCHN, e.g., N-Blok™ from Applied Materials) may be deposited in other embodiments. Apassivation layer 130 is deposited over thecap layer 120. Thepassivation layer 130 is typically an oxide layer. In other embodiments, thepassivation layer 130 may comprise FTEOS, SiN, SiCOH, or other low-k materials. An insulatingliner 140 is disposed above thepassivation layer 130. The optional insulatingliner 140 preferably comprises a nitride layer. In various embodiments, the optional insulatingliner 140 may comprise FTEOS, SiO2, SiCOH, or other low-k materials. Thecap layer 120, thepassivation layer 130 and insulatingliner 140 form a protective layer over thelast metal line 100, and prevent environmental degradation of copper and active circuitry. - A layer of photoresist is deposited over the optional insulating liner 140 (not shown). The photoresist is exposed and etched to form a mask layer. Using the photoresist mask layer, the optional insulating
liner 140,passivation layer 130, and thecap layer 120 are etched to open a trench 150 (or a via) (FIG. 3 b). A suitable chemistry is chosen to form the trench with tapering sidewalls as illustrated inFIG. 3 b. The angle of the trench α is chosen to be between about 30° and about 90°. - Referring to
FIG. 3 c, aconductive liner 160 is deposited over thetrench 150 and over the optional insulatingliner 140. A planarising process such as a chemical mechanical polish (CMP) is used to remove theconductive liner 160 from over the optional insulating liner 140 (or over the passivation layer 130) (FIG. 3 d). Theconductive liner 160 is a diffusion barrier metal and prevents out-diffusion of copper from thelast metal line 100 as well as any intermixing with further metallic layers. Theconductive liner 160 preferably comprises TiN. In various embodiments, theconductive liner 160 is selected from a group comprising TiN, Ti/TiN, Ta, Ta/TaN, Al, Al/Cu and their combinations. In other embodiments, any other suitable metallic liner materials or their compositions may be used. Theconductive liner 160 may be deposited by a suitable deposition process such as PVD, sputtering, CVD, or ALD. - As illustrated in
FIG. 3 e, an underbump metallization layer 170 is deposited on thetrench 150. TheUBM layer 170 comprises multiple layers, although in some embodiments a single layer may be used. ThisUBM layer 170 provides a strong, stable, low resistance electrical connection to theconductive liner 160. It adheres well to the underlyingconductive liner 160. TheUBM layer 170 also provides a strong barrier to prevent the diffusion of other bump metals into the IC. TheUBM layer 170 is also readily wettable by the bump metals, for solder reflow. Hence, theUBM layer 170 typically comprises multiple layers of different metals, such as an adhesion layer, a diffusion barrier layer, and a solderable layer. TheUBM layer 170 may be deposited by electroplating, sputtering, or deposited by any other suitable process. TheUMB layer 170 preferably comprises a Ti/Cu/Ni layer. In various embodiments, the deposition ofUBM layer 170 may comprise deposition of layers of Ti, Cu, Ni, Cr, Cr—Cu, Ni—V, Ti—Cu, Ti—W, Au, or Ni—Au. - A photo resist
layer 180 is deposited over theUBM layer 170, as illustrated inFIG. 3 f. The photo resistlayer 180 is patterned using a lithographic process to expose a region above thetrench 150. Abump metal 190 is deposited over theUBM layer 170, covering thetrench 150. Thebump metal 190 is preferably electroplated onto a seed layer on theUBM layer 170, although, in other embodiments, other processes such as electroless plating or deposition processes such as vapor deposition may also be used. Thebump metal 190 may be a single layer or comprise multiple layers with different compositions. For example, in one embodiment, thebump metal 190 comprises a lead (Pb) layer followed by a tin (Sn) layer. In another embodiment, an Sn/Ag layer may be deposited as thebump metal 190. Other examples include SnPbAg, SnPb, PbAg, PbIn, and lead free materials such as SnBi, SnAgCu, SnTn, and SiZn. In various embodiments, other suitable materials may be deposited. - Referring to
FIG. 3 g, the photo resistlayer 180 is removed along with removal of the exposed UBM layer 170 (FIG. 3 h). As next illustrated inFIG. 3 i, the substrate is heated to reflow thebump metal 190 and the heating forms asolder bump 191 over theUBM layer 170. After reflow, ahomogeneous solder bump 191 is formed. For example, in the embodiment when Pb/Sb layer is deposited, after reflow, high lead alloys including 95 Pb/5 Sn (95/5) or 90 Pb/10 Sn (95/10) with melting temperatures in excess of 300° C. are formed. In a different embodiment, eutectic 63 Pb/37 Sn (63/37) with a melting temperature of 183° C. is formed. Similarly, a lead free solder bump may be formed that comprises a composition of 97.5 Sn/2.6 Ag (97.5/2.5). Thesolder bump 191 comprises a homogeneous material and has a well defined melting temperature. For example, the high melting Pb/Sn alloys are reliable bump metallurgies which are particularly resistant to material fatigue. TheUBM layer 170 may also diffuse and intermix. However, theconductive liner 160 is stable during heating and protects the inter diffusion of metal atoms into and from thelast metal line 100. - In a different embodiment, a flip chip package is formed after the removal of the exposed
UBM layer 170, as described inFIG. 3 h, the substrate 1 (wafer) is diced to formsemiconductor chips 3, as shown inFIG. 3 j. Theindividual semiconductor chips 3 with thesolder bump 191 are next flipped over and bonded to acarrier 2 such as a PC board (FIG. 3 j). Thecarrier 2 may be a circuit board or any suitable substrate. The bonding may be performed by a reflow of the solder bump 190 (FIG. 3 k). An under-fill layer 106 between thecarrier 2 and thechips 3 is added to reduce the stress in thesolder bump 191 and for supporting the structure. - An embodiment of the invention for manufacturing the package is next described using
FIG. 5 and the flow chart ofFIG. 6 . - As illustrated in
FIGS. 5 a-5 c, the method follows the method described inFIGS. 3 a-3 c. Hence, atrench 150 is formed with aconductive liner 160. Atrench 150 is formed on the stack formed by thecap layer 120, thepassivation layer 130, and the optional insulatingliner 140. Aconductive liner 160 is disposed above and on thelast metal line 100. Theconductive liner 160 also is disposed on the sidewalls of thetrench 150. A resistlayer 161 is deposited over the conductive liner 160 (FIG. 5 d). As illustrated inFIG. 5 e, the resistlayer 161 is patterned to expose theconductive liner 160. The exposed portion of theconductive liner 160 is etched away. As next illustrated inFIG. 5 f, the exposed portion of the optional insulatingliner 140 is also etched away. The patterned photo resist layer is etched and removed (FIG. 5 g). Subsequent processing follows the steps described inFIGS. 3 e-3 i. - Although embodiments of the present invention are explained for flip chip packages, the embodiments of the invention apply to other packages, in particular to wire bonding, wafer level, and embedded wafer level packages.
- Although embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present invention.
- 1 Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims (19)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/029,127 US20090200675A1 (en) | 2008-02-11 | 2008-02-11 | Passivated Copper Chip Pads |
US13/854,321 US8822324B2 (en) | 2008-02-11 | 2013-04-01 | Passivated copper chip pads |
US14/307,263 US9373596B2 (en) | 2008-02-11 | 2014-06-17 | Passivated copper chip pads |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US12/029,127 US20090200675A1 (en) | 2008-02-11 | 2008-02-11 | Passivated Copper Chip Pads |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US13/854,321 Division US8822324B2 (en) | 2008-02-11 | 2013-04-01 | Passivated copper chip pads |
Publications (1)
Publication Number | Publication Date |
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US20090200675A1 true US20090200675A1 (en) | 2009-08-13 |
Family
ID=40938206
Family Applications (3)
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---|---|---|---|
US12/029,127 Abandoned US20090200675A1 (en) | 2008-02-11 | 2008-02-11 | Passivated Copper Chip Pads |
US13/854,321 Active US8822324B2 (en) | 2008-02-11 | 2013-04-01 | Passivated copper chip pads |
US14/307,263 Active US9373596B2 (en) | 2008-02-11 | 2014-06-17 | Passivated copper chip pads |
Family Applications After (2)
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US13/854,321 Active US8822324B2 (en) | 2008-02-11 | 2013-04-01 | Passivated copper chip pads |
US14/307,263 Active US9373596B2 (en) | 2008-02-11 | 2014-06-17 | Passivated copper chip pads |
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US (3) | US20090200675A1 (en) |
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Also Published As
Publication number | Publication date |
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US20140295661A1 (en) | 2014-10-02 |
US20130224946A1 (en) | 2013-08-29 |
US9373596B2 (en) | 2016-06-21 |
US8822324B2 (en) | 2014-09-02 |
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