US20090185044A1 - Image Sensor and Method with Multiple Scanning Modes - Google Patents
Image Sensor and Method with Multiple Scanning Modes Download PDFInfo
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- US20090185044A1 US20090185044A1 US12/414,592 US41459209A US2009185044A1 US 20090185044 A1 US20090185044 A1 US 20090185044A1 US 41459209 A US41459209 A US 41459209A US 2009185044 A1 US2009185044 A1 US 2009185044A1
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- reset
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/60—Control of cameras or camera modules
- H04N23/617—Upgrading or updating of programs or applications for camera control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
- H04N25/44—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by partially reading an SSIS array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/745—Circuitry for generating timing or clock signals
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- Software Systems (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Multiple scanning modes are provided for an array of electromagnetic radiation sensors. In the preferred implementation both selectable subarrays and the overall array can be read out and reset in any desired order, including interrupting a full array scan for a subarray scan and then resuming the full array scan.
Description
- 1. Field of the Invention
- This invention relates to digital imaging devices and methods, and more particularly to multimode scanning of an image sensor.
- 2. Description of the Related Art
- Imaging sensors are used in digital cameras and camcorders, high definition televisions (HDTV), telescopes and other equipment. Two types of image sensors commonly used for these applications are charge coupled device (CCD) and complementary metal oxide semiconductor (CMOS). Each includes a detector portion, typically a two-dimensional array of pixel circuits. Each pixel circuit contains both a detector that converts photons (electromagnetic radiation) into a charge (electron-hole pairs), that accumulates at the detector, and an output circuit. Each detector has a maximum charge that it is capable of holding. When this maximum charge has accumulated, the detector saturates and cannot hold any more.
- Each pixel senses one small area within the larger image, with its circuit outputting a signal representing that portion of the image. The pixel circuits may require resetting to obtain a new image or to accommodate a bright star that has saturated the circuit.
- Image sensing for astronomy applications currently requires two image sensors to record an image of the sky. One sensor is used to fix the telescope orientation with respect to a “guide star” as the earth rotates, and another to sense the image. The guide star is typically a bright star that can be easily tracked. Because a bright star is used, the guide star sensor quickly saturates and must be reset more frequently than the image sensor. Also, for accurate tracking, a high frame rate is required for the guide star sensor.
- Most imaging sensors read out and reset rows or columns of pixels at a time. This makes it difficult to concentrate on only one portion of the overall image.
- The present invention is a method and system which overcomes the problems noted above. It provides for multiple scanning modes in an image sensor. Selected subarrays of an image sensor can be read and reset independently of the rest of the sensor. This is useful for the astronomy application mentioned above, as well as in other applications for which only a portion of an image sensor needs to be read and/or reset.
- One embodiment of the invention includes a controller configured to produce a control signal that indicates a subarray to be scanned, selection circuits connected to select the subarray, and scanning circuits connected to scan the selected subarray.
- Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.
-
FIG. 1 is a block diagram of a digital imaging system utilizing multiple mode control according to one embodiment of the invention. -
FIG. 2 is a schematic diagram of an individual pixel reset circuit used in one embodiment of the invention. -
FIG. 3 is a schematic diagram of one implementation for the digital imaging system ofFIG. 1 . - An imaging system according to one embodiment of the invention is shown in
FIG. 1 . It includes a multiplemode control circuit 12 that is configured to scan an array ofelectromagnetic radiation sensors 14 andselectable subarrays 16. The invention is most commonly applicable to photosensitive detectors which are sensitive to visible light, infrared and/or ultraviolet, but it is also applicable to other regions of the electromagnetic spectrum. -
Control circuit 12 includes acontroller 18 that controls the operation of the imaging system.Controller 18 sends control signals oncontrol lines selection circuits Selection circuits selection lines -
Scanning circuits circuits circuits circuits array 14. When activated, readcircuits lines circuits lines - Scanning is typically accomplished by reading out the voltage on an individual sensor, then resetting it. However, a scan could be a read without a reset, or a reset without a read. With the present configuration, entire rows or columns can be read or reset at one time, or selected sensors in the row or column can be read or reset.
- The sensors in
array 14 are defined and accessed by a set of coordinates. While the description above is for rows and columns, these could be interchanged, or other array geometries such as concentric circular, staggered pixels, or three-dimensional could be used. -
Controller 18 controls whether theentire array 14 or a subarray 16 is scanned. Subarrays can be read and reset independent of the entire array. The controller can pause the scanning of the full array at any time to scan a suharray. This is particularly useful when a portion of the full array becomes saturated. More than one subarray may be scanned if desired. - One possible pixel with an individual reset circuit is shown in
FIG. 2 . The pixel includes anelectromagnetic radiation sensor 42 that accumulates charge in response to received radiation, and areset transistor 44 that, when activated by alogic gate 46, connects a reset voltage onreset voltage line 48 tosensor 42 to reset its voltage level. Avoltage source 50 supplies resetvoltage line 48, and can provide enough current to reduce the voltage on the sensor to the level onreset voltage line 48. The reset voltage is typically a low voltage such as 0-500 millivolts for a p-n type sensor.Sensor 42 is typically a photodiode, but may be a phototransistor or other type of electromagnetic sensing device. - A
read transistor 52 and asource follower transistor 54 have their source-drain circuits connected in series from aread bus 56 to the source-drain circuit ofreset transistor 44.Source follower transistor 54 has its gate connected to the detector'soutput node 58. The voltage atnode 60, betweentransistors detector node 58 through the normal source follower action oftransistor 54. To read out a signal from the pixel, a voltage is applied to a read enableline 62, which is connected to the gate ofread transistor 52, sufficient to turn on the read transistor, which then applies the voltage atnode 60 to theread bus 56 through its activated source-drain circuit. -
Logic gate 46 receives logic inputs from row andcolumn reset lines row reset line 64 andcolumn reset line 66 are activated,gate 46′ activatesreset transistor 44. This causes the voltage ondetector node 58 to be set to the voltage onreset voltage line 48, as described above. -
Logic gate 46 is typically-an AND gate, but other types of logic gates that turn onreset transistor 44 when row resetline 64 and column resetline 66 are activated could be used. The reset lines can be activated by positive, zero or negative voltages, depending upon the nature of thelogic gate 46. For example, if an exclusive NOR gate is employed, resettransistor 44 would be turned on in response to an absence of voltage on both reset lines. The type of logic gate used and the nature of the signals applied to the reset lines also depend on the nature ofreset transistor 44. For example, iftransistor 44 were an nFET device rather than a pFET,gate 46 would need to provide an opposite signal in response to the same inputs from the reset lines. As an alternative tologic gate 46, a second reset transistor could be connected in series withtransistor 44, with one transistor controlled by the row resetline 64 and the other bycolumn reset line 66, so that reset occurs only when both transistors are activated. - A simplified digital imaging system with an array of
pixels 14 employing multiple mode control according to one embodiment of the invention is shown inFIG. 3 .Individual pixels 15 are shown spaced widely apart for ease of illustrating the various signal lines, but in practice they would be much closer together. -
Selection circuit 22 includes a full-array shift register 70 that is controlled by the controller 18 (not shown). When full array select circuit 72 is activated, it sends a signal to ANDgate 74, which advances the full-array shift register 70 each time a pulse is received from acolumn clock 76. This shifts all values in the shift register to the right by one place.Controller 18 applies a logic “1” to first register from the left within fullarray shift register 70. With successive clock pulses, the 1 is shifted through the register to enable a desired operation upon each column in the array in succession. The corresponding row circuitry operates in a similar fashion, except its timing is controlled by arow clock 77 that operates at a frequency that is less than that of the column clock by a factor equal to the number of columns. This allows the pixels in the first row to be operated upon in sequence at each column clock pulse. A row clock pulse is generated when the last pixel in the first row has been operated upon. Each pixel in the second row is then operated upon in sequence at each successive column clock pulse, and so on until the entire array has been scanned. - When full-array select circuit 72 is deactivated by the controller, its logic 0output is inverted to a logic 1by an
inverter 75 and applied as one input to another ANDgate 78. The other input to ANDgate 78 is supplied by thecolumn clock 76. ANDgate 78 controls asubarray shift register 80 that operates in a manner similar to full-array shift register 70. The full-array select circuit 72 thus controls whether scanning is performed by the full-array shift register 70 or thesubarray shift register 80. -
Subarray shift register 80 receives location information, including a start and stop column for the subarray to be scanned, from a subarraystart address decoder 82 and a subarraystop address decoder 84, respectively. Thedecoder controller 18. Output lines are provided from the decoders to each individual register withinsubarray shift register 80. Startaddress decoder 82 activates one output line at a time, corresponding to the column number received from the controller. For example, if the controller provided the digital number 8, the decoder would place a “1” into the eighth bit from the left in theshift register 80, causing subarray scanning to start at the eighth column from the left. The first decoder output line is activated in response to a digital zero input from the controller. A decoder with an n bit input can control 2″ outputs, allowing 2048 lines of rows and/or columns can be controlled with an 11-bit word from the controller. Other decoder configurations can be used for different size arrays. - In this manner, a “1” is placed into the
shift register 80 at the column where the subarray is to start. The “1” is shifted through the shift register to sequentially scan the pixels of a given row within the subarray. - When the stop column for the subarray is reached, a 0 is forced into the register following the stop column location by the
stop address decoder 84 to discontinue scanning. Alternatively, another logic gate (not shown) may be used between the decoders and the shift registers. When activated, the logic gate would place a “0” into the register following the last row or column of the subarray to be scanned. With this configuration, the start and stop columns may be placed into the subarray shift register and the subarray scanned. Corresponding row circuitry similarly controls the start and stop rows of the subarray to be scanned. - The
array 14 is typically read from the upper left corner to the lower right corner, row by row. There is one register in full-array shift register 70 per column. When a register has a “1” in it, a signal is sent to amultiplexer 86 for that column. An activated full-array select circuit 72 activates full-array shift register 70 at each clock pulse, andmultiplexer 86 passes the signal from full-array shift register 70. A deactivated full-array select circuit 72 activatessubarray shift register 80 at each clock pulse, andmultiplexer 86 passes the signal fromsubarray shift register 80. -
Multiplexers 86 provide one of two signals needed to activate either a read logic gate 88 or areset logic gate 90 for a particular column. The other input to activate read logic gate 88 comes from a read enable circuit 92, which is controlled by the controller. The other input to activatereset logic gate 90 comes from a reset enablecircuit 94, which is also controlled by the controller. - The reset of an
individual pixel 15 occurs in response to activation ofreset logic gate 90, which activates column resetline 66 and provides one input tologic gate 46, as described in connection withFIG. 2 . The other input needed to reset a pixel is provided from row resetline 64, which is activated in a manner similar to column resetline 66, by corresponding circuitry for each row ofarray 14. - The reading of pixels occurs when the read enable
line 62 is activated by corresponding row circuitry, which matches and sends the voltage from every sensor in a selected row to the read bus for that row, as described above. Read logic gate 88 is then enabled, sending a signal that activates a vertical read enabletransistor 96 that allows the voltage on readbus 56 for a selected column to be read out by the controller. When read enableline 62 is activated, the voltage from every sensor in the row is applied to itsrespective read bus 56. However, the only voltages read out from the read buses are from the column(s) that have their vertical read enabletransistor 96 activated. In this manner, an entire row or individual sensors can be read out. - The
row selection circuit 22 a is similar to thecolumn selection circuit 22.Row selection circuit 22 a includes subarray start and stopdecoders subarray shift register 80 a, a full-array shift register 70 a, amultiplexer 86 a, full-arrayselect circuit 72 a, read enablecircuit 92 a, reset enablecircuit 94 a, andlogic gates - The
row selection circuit 22 acontrols logic gates lines lines line 62 allows the voltage from each sensor in that row to be read byread bus 56 and applied to acommon read bus 95 when a corresponding vertical read enabletransistor 96 is activated.Row selection circuit 22 a also includeshorizontal clock 77 that is controlled as described above. A keep-alivecurrent source 98 can be connected Lo the common read bus to maintain the source follower transistors in the read out pixels in an active state, or less desirably an individual keep-alive transistor could be provided within each pixel. - With this configuration, the full array and a subarray (or more than one subarray) can be scanned in any desired order. For example, the scanning of the full array can be interrupted to scan a subarray, or the subarray can be scanned before or after the full array is scanned. When reactivated, the full-array scanning continues at the point of interruption, because full-array shift registers 70 and 70 a retain the values of the row and column at which scanning was interrupted.
- While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. For example, while FETs have been shown, other transistor types such as bipolar could be used. Accordingly, it is intended that the invention be limited only in terms of the appended claims.
Claims (22)
1. An imaging system, comprising:
a sensor array for sensing an images;
a read out circuit connected to read out sensors of said arrays; and
a control circuit connected to said read out circuit to enable a read out of the sensors in selectable subarrays of said array and integrated in the imaging sensor to facilitate read out and reset of the sensors in the imaging array, wherein said control circuit controls operation of the imaging system on chip by specifically generating multiple sensor selection and reset signals outside of the sensors and determining the specific sensors and/or sensor subarray to be read, reset or both.
2. The system of claim 1 , wherein said control circuit is also connected to selectably enable a read out of the full array.
3. The system of claim 2 , wherein said control circuit is programmable to initiate a read out of the full array, to interrupt said full array read out and enable the read out of a selected subarray, and to thereafter complete said full array read out.
4. The system of claim 1 , wherein said sensor array is arranged in rows and columns, and said control circuit enables a read out of a selected subarray by designating start and stop columns and start and stop rows for said readout.
5. The system of claim 1 , further comprising a reset circuit connected to reset the sensors of said array, said control circuit connected to said reset circuit to enable a reset of the sensors in said selectable subarrays.
6. An imaging system, comprising:
an array of electromagnetic radiation sensors; and
a multiple mode control circuit controllable to scan selectable subarrays within said array and integrated in the imaging system to facilitate read out and reset of the sensors in the array wherein said control circuit controls operation of the imaging system on chin by specifically generating multiple sensor selection and reset signals outside of the sensors and determining the specific sensors and/or sensor subarray to be read, reset or both.
7. The system of claim 6 , wherein said control circuit is also controllable to scan said array as a whole.
8. The system of claim 6 , wherein said sensors are included in respective pixels, each pixel further comprising:
a respective reset transistor connected to enable, when activated, a reset of the pixel's sensor; and
a respective logic gate connected to activate said reset transistor in response to a plurality of reset signals.
9. The system of claim 6 , wherein said sensors are included in respective pixels and said control circuit comprises:
a controller configured to produce a control signal that designates a subarray to be scanned;
a selection circuit responsive to said control signal to select a subarray to be scanned, and
a scanning circuit connected to scan the pixels in a selected subarray.
10. The imaging system of claim 9 , wherein said scanning circuit comprises:
a read circuit configured to read out pixels of said array; and
a reset circuit configured to reset pixels of said array.
11. The imaging system of claim 10 , wherein said selection circuit comprises:
a decoder connected to provide location signals to indicate a subarray to be scanned; and
a multiplexer circuit configured to enable either said read circuit or said reset circuit for each pixel in a selected subarray.
12. The imaging system of claim 11 , further comprising a shift register responsive to said decoder to enable either said read circuit or said reset circuit for the pixels of a selected subarray.
13. The imaging system of claim 10 , wherein said read circuit comprises:
a logic gate connected to transmit a sensor signal to a read bus; and
a transistor connected to said read bus to enable said sensor signal to be read out from said read bus.
14. The imaging system of claim 10 , wherein said reset circuit comprises:
an individual pixel reset circuit connected to reset a selectable pixel in response to a plurality of reset signals.
15. The imaging system of claim 14 , wherein said individual pixel reset circuit comprises:
a respective reset transistor associated with each pixel and connected to enable a reset of said pixel; and
a respective logic gate associated with each pixel and connected to activate the pixel's reset transistor in response to a plurality of reset signals.
16. A method of reading out an array of electromagnetic radiation sensors, comprising:
reading out the full array of sensors;
selecting a subarray of said sensors-;
reading out said selected subarray separate from reading out the full array; and
integrating a control circuit in each sensor to facilitate read out and reset of the sensors in the array, wherein said control circuit controls operation of the imaging system on chip by specifically generating multiple sensor selection and reset signals outside of the sensors and determining the specific sensors and/or sensor subarray to be read, reset or both.
17. The method of claim 16 , further comprising selecting a plurality of different subarrays of said sensors and reading out each of said selected subarrays separate from reading out the full array.
18. The method of claim 16 , further comprising resetting the selected subarray after the selected subarray has been read out.
19. The method of claim 16 , wherein the reading out of said full array is interrupted, said selected subarray is read out during said interruption, and said full array read out is thereafter completed.
20. The method of claim 16 , wherein said sensors are arranged in rows and columns, and the read out of a selected subarray is controlled by designating start and stop columns and start and start rows for read out.
21. An imaging system, comprising:
a pixel array for sensing an image;
a read out circuit connected to read out the pixels of said array;
a control circuit connected to said read out circuit to enable a read out of the pixels in selectable subarrays of said array;
a shift register; and
a decoder connected to provide location signals to indicate a subarray to be scanned; wherein the shift register is responsive to the decoder to enable either the read out circuit or the reset circuit for the pixels of a selected subarray.
22. An imaging system, comprising:
an array of electromagnetic radiation sensors;
a multiple mode control circuit controllable to scan selectable subarrays within said array; and
a shift register;
wherein the multiple mode control circuit comprises a read circuit configured to read out pixels of the array, and a reset circuit configured to reset pixels of the array; the selection circuit comprises a decoder connected to provide location signals to indicate a subarray to be scanned; and wherein the shift register is responsive to the decoder to enable either the read circuit or the reset circuit for the pixels of a selected subarray.
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US12/414,592 US20090185044A1 (en) | 2003-05-12 | 2009-03-30 | Image Sensor and Method with Multiple Scanning Modes |
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US10/436,947 US7525586B2 (en) | 2003-05-12 | 2003-05-12 | Image sensor and method with multiple scanning modes |
US12/414,592 US20090185044A1 (en) | 2003-05-12 | 2009-03-30 | Image Sensor and Method with Multiple Scanning Modes |
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US10/436,947 Continuation US7525586B2 (en) | 2003-05-12 | 2003-05-12 | Image sensor and method with multiple scanning modes |
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US6844896B2 (en) * | 2000-08-18 | 2005-01-18 | Stmicroelectronics Limited | Modification of column fixed pattern column noise in solid state image sensors |
US7245323B2 (en) * | 2002-02-26 | 2007-07-17 | Victor Company Of Japan, Ltd. | Transferring method of electric charge from image sensing device and the image sensing device |
Cited By (3)
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US20090316031A1 (en) * | 2008-06-19 | 2009-12-24 | Yamaha Corporation | CMOS solid state imaging device |
US20160212361A1 (en) * | 2013-10-08 | 2016-07-21 | Olympus Corporation | Imaging device |
US9942491B2 (en) * | 2013-10-08 | 2018-04-10 | Olympus Corporation | Imaging device including two substrates |
Also Published As
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US7525586B2 (en) | 2009-04-28 |
US20040227828A1 (en) | 2004-11-18 |
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