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Publication numberUS20090170241 A1
Publication typeApplication
Application numberUS 11/964,397
Publication date2 Jul 2009
Filing date26 Dec 2007
Priority date26 Dec 2007
Also published asUS7923295, US20100052135, US20110147926, US20120217634
Publication number11964397, 964397, US 2009/0170241 A1, US 2009/170241 A1, US 20090170241 A1, US 20090170241A1, US 2009170241 A1, US 2009170241A1, US-A1-20090170241, US-A1-2009170241, US2009/0170241A1, US2009/170241A1, US20090170241 A1, US20090170241A1, US2009170241 A1, US2009170241A1
InventorsIl Kwon Shim, Yaojian Lin, Seng Guan Chow
Original AssigneeStats Chippac, Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
US 20090170241 A1
Abstract
A semiconductor device is made by forming contact pads on a sacrificial carrier. The contact pads may be formed on a pillar. A semiconductor die is mounted to electrically connect to the contact pads with solder bumps or wire bonds. The semiconductor die is encapsulated with molding compound. The sacrificial carrier is removed. A backside interconnect structure has a first conductive layer formed over the molding compound to electrically connect to the contact pads. A first insulating layer is formed over the first conductive layer. A portion of the first insulating layer is removed to expose the first conductive layer. Solder material is deposited in electrical contact with the first conductive layer. The solder material is reflowed to form a solder bump. A wire bond electrically connects to a contact pad. A front-side interconnect structure can be formed through the molding compound to the contact pads.
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Claims(21)
1. A method of making a semiconductor device, comprising:
providing a first sacrificial metal carrier;
forming a photoresist layer over the first sacrificial metal carrier;
forming openings in the photoresist layer extending to the first sacrificial metal carrier;
forming conductive pillars in the openings of the photoresist layer;
forming a plurality of contact pads over the conductive pillars, the contact pads being selectively electroplated through the openings in the photoresist layer onto the conductive pillars to provide precise alignment of the contact pads for electrical interconnect, the conductive pillars and first sacrificial metal carrier providing a plating current path for electroplating the contact pads;
removing the photoresist layer;
mounting a first semiconductor die to electrically connect to the contact pads;
encapsulating the first semiconductor die, contact pads, and conductive pillars with molding compound;
removing the first sacrificial metal carrier;
mounting a second sacrificial carrier over a first side of the molding compound opposite the contact pads;
forming a first conductive layer over a second side of the molding compound opposite the first side of the molding compound, the first conductive layer being electrically connected to the contact pads;
forming a first insulating layer over the first conductive layer and molding compound;
removing a portion of the first insulating layer to expose the first conductive layer;
forming a second conductive layer over the first conductive layer and first insulating layer;
forming a second insulating layer over the first insulating layer and second conductive layer;
removing a portion of the second insulating layer to expose the second conductive layer; depositing solder material in electrical contact with the second conductive layer;
reflowing the solder material to form a solder bump;
removing the second sacrificial carrier;
forming vias through the first side of the molding compound to the contact pads, the vias having a reduced depth due to the conductive pillars;
forming a third conductive layer over the molding compound and sidewalls of the vias to electrically connect to the contact pads;
forming a third insulating layer over the molding compound and third conductive layer, the third insulating layer extending into the vias to cover the third conductive layer; and
removing a portion of the third insulating layer to expose the third conductive layer.
2. The method of claim 1, further including forming a wire bond electrically connected to one of the plurality of contact pads.
3. The method of claim 1, wherein the first semiconductor die electrically connects to the contact pads with solder bumps or wire bonds.
4-5. (canceled)
6. The method of claim 1, further including:
mounting a second semiconductor die to the solder bump; and
encapsulating the second semiconductor die with molding compound.
7. (canceled)
8. A method of making a semiconductor device, comprising:
providing a sacrificial metal carrier;
forming a photoresist layer over the sacrificial metal carrier;
forming openings in the photoresist layer extending to the sacrificial metal carrier;
forming a plurality of contact pads on the sacrificial carrier, the contact pads being selectively electroplated through the openings in the photoresist layer onto the sacrificial metal carrier to provide precise alignment of the contact pads for electrical interconnect, the sacrificial metal carrier providing a plating current path for electroplating the contact pads;
removing the photoresist layer;
mounting a first semiconductor die to electrically connect to the contact pads;
encapsulating the first semiconductor die with molding compound;
removing the sacrificial metal carrier;
mounting a second sacrificial carrier over a first side of the molding compound opposite the contact pads;
forming a first conductive layer over a second side of the molding compound opposite the first side of the molding compound, the first conductive layer being electrically connected to the contact pads;
forming a first insulating layer over the first conductive layer;
removing the second sacrificial carrier;
forming vias through the first side of the molding compound to the contact pads;
forming a second conductive layer over the molding compound and into the vias to electrically connect to the contact pads; and
forming a second insulating layer over the molding compound and second conductive layer
9. The method of claim 8, further including:
depositing solder material on the first conductive layer; and
reflowing the solder material to form a solder bump.
10. The method of claim 9, further including:
mounting a second semiconductor die to the solder bump; and
encapsulating the second semiconductor die with molding compound.
11. (canceled)
12. The method of claim 8, wherein the first semiconductor die electrically connects to the contact pads with solder bumps or wire bonds.
13-15. (canceled)
16. A method of making a semiconductor package, comprising:
providing a sacrificial metal carrier;
forming a photoresist layer over the sacrificial metal carrier;
forming openings in the photoresist layer extending to the sacrificial metal carrier;
forming a plurality of contact pads on the sacrificial carrier, the contact pads being selectively electroplated through the openings in the photoresist layer onto the sacrificial metal carrier to provide precise alignment of the contact pads for electrical interconnect, the sacrificial metal carrier providing a plating current path for electroplating the contact pads;
mounting a first semiconductor die to electrically connect to the contact pads;
encapsulating the first semiconductor die with molding compound; and
forming an interconnect structure over the molding compound and electrically connected to the contact pads.
17. The method of claim 16, wherein forming the interconnect structure includes:
forming a first conductive layer over the molding compound and electrically connected to the contact pads;
forming a first insulating layer over the first conductive layer; and
removing a portion of the first insulating layer to expose the first conductive layer.
18. The method of claim 17, further including:
forming a second conductive layer over the first insulating layer and electrically connected to the first conductive layer;
forming a second insulating layer over the second conductive layer; and
removing a portion of the second insulating layer to expose the second conductive layer.
19. The method of claim 18, further including mounting a front-side process carrier to the second insulating layer with an adhesive layer.
20. The method of claim 19, further including:
forming vias through the molding compound to the contact pads;
forming a second conductive layer in the vias to electrically connect to the contact pads;
forming a second insulating layer over the second conductive layer; and
removing a portion of the second insulating layer to expose the second conductive layer.
21. The method of claim 17, further including:
depositing solder material on the first conductive layer; and
reflowing the solder material to form a solder bump.
22. The method of claim 16, further including removing the sacrificial carrier.
23. The method of claim 16, wherein the first semiconductor die electrically connects to the contact pads with solder bumps or wire bonds.
24. The method of claim 16, further including forming a pillar under each of the plurality of contact pads.
Description
    FIELD OF THE INVENTION
  • [0001]
    The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming the device using a sacrificial carrier.
  • BACKGROUND OF THE INVENTION
  • [0002]
    Semiconductor devices are found in many products in the fields of entertainment, communications, networks, computers, and household markets. Semiconductor devices are also found in military, aviation, automotive, industrial controllers, and office equipment. The semiconductor devices perform a variety of electrical functions necessary for each of these applications.
  • [0003]
    The manufacture of semiconductor devices involves formation of a wafer having a plurality of die. Each semiconductor die contains hundreds or thousands of transistors and other active and passive devices performing a variety of electrical functions. For a given wafer, each die from the wafer typically performs the same electrical function. Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer. The finished wafer has an active side containing the transistors and other active and passive components. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation.
  • [0004]
    One goal of semiconductor manufacturing is to produce a package suitable for faster, reliable, smaller, and higher-density integrated circuits (IC) at lower cost. Flip chip packages or wafer level chip scale packages (WLCSP) are ideally suited for ICs demanding high speed, high density, and greater pin count. Flip chip style packaging involves mounting the active side of the die facedown toward a chip carrier substrate or printed circuit board (PCB). The electrical and mechanical interconnect between the active devices on the die and conduction tracks on the carrier substrate is achieved through a solder bump structure comprising a large number of conductive solder bumps or balls. The solder bumps are formed by a reflow process applied to solder material deposited on contact pads which are disposed on the semiconductor substrate. The solder bumps are then soldered to the carrier substrate. The flip chip semiconductor package provides a short electrical conduction path from the active devices on the die to the carrier substrate in order to reduce signal propagation, lower capacitance, and achieve overall better circuit performance.
  • [0005]
    In many applications, it is desirable to stack WLCSPs. Appropriate electrical interconnect must be provided for complete device integration. The interconnect typically involves formation of redistribution layers (RDL) and other conductive lines and tracks. These metal lines have limited pitch and line spacing due to etching processing. The formation of the interconnect structure requires a high degree of alignment accuracy in attaching the die to the wafer carrier for subsequent encapsulation and further RDL buildup processes.
  • [0006]
    A need exists to form the interconnect structures for WLCSPs while accounting for the interconnect alignment requirements.
  • SUMMARY OF THE INVENTION
  • [0007]
    In one embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a sacrificial carrier, forming a plurality of contact pads on the sacrificial carrier, mounting a first semiconductor die to electrically connect to the contact pads, encapsulating the first semiconductor die with molding compound, removing the sacrificial carrier, forming a first conductive layer over the molding compound in electrical contact with the contact pads, forming a first insulating layer over the first conductive layer, removing a portion of the first insulating layer to expose the first conductive layer, depositing solder material in electrical contact with the first conductive layer, and reflowing the solder material to form a solder bump.
  • [0008]
    In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a sacrificial carrier, forming a plurality of contact pads on the sacrificial carrier, mounting a first semiconductor die to electrically connect to the contact pads, encapsulating the first semiconductor die with molding compound, forming a first conductive layer over the molding compound in electrical contact with the contact pads, forming a first insulating layer over the first conductive layer, and removing a portion of the first insulating layer to expose the first conductive layer.
  • [0009]
    In another embodiment, the present invention is a method of making a semiconductor package comprising the steps of providing a sacrificial carrier, forming a plurality of contact pads on the sacrificial carrier, mounting a first semiconductor die to electrically connect to the contact pads, encapsulating the first semiconductor die with molding compound, and forming an interconnect structure over the molding compound in electrical contact with the contact pads.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0010]
    FIG. 1 is a flip chip semiconductor device with solder bumps providing electrical interconnect between an active area of the die and a chip carrier substrate;
  • [0011]
    FIGS. 2 a-2 f illustrate formation of a semiconductor package using a sacrificial carrier;
  • [0012]
    FIG. 3 illustrates the semiconductor package with solder bumps and wire bonds;
  • [0013]
    FIGS. 4 a-4 c illustrate an alternate formation of the semiconductor package with a sacrificial carrier;
  • [0014]
    FIG. 5 illustrates the semiconductor package with wire bond interconnects to the semiconductor die;
  • [0015]
    FIGS. 6 a-6 b illustrate the semiconductor package with front-side and backside interconnects;
  • [0016]
    FIG. 7 illustrates the semiconductor package with pillars under the contact pads;
  • [0017]
    FIG. 8 illustrates the semiconductor package with solder bump and wire bond interconnects to the die;
  • [0018]
    FIG. 9 illustrates the semiconductor package with underfill material disposed under the semiconductor die;
  • [0019]
    FIG. 10 illustrates the semiconductor package with secondary die mounted to the front-side interconnects;
  • [0020]
    FIG. 11 illustrates the semiconductor package with the sacrificial carrier left intact for heat dissipation; and
  • [0021]
    FIG. 12 illustrates the semiconductor package with photoresist left intact between the contact pads.
  • DETAILED DESCRIPTION OF THE DRAWINGS
  • [0022]
    The present invention is described in one or more embodiments in the following description with reference to the Figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.
  • [0023]
    The manufacture of semiconductor devices involves formation of a wafer having a plurality of die. Each die contains hundreds or thousands of transistors and other active and passive devices performing one or more electrical functions. For a given wafer, each die from the wafer typically performs the same electrical function. Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer. The finished wafer has an active side containing the transistors and other active and passive components. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and/or environmental isolation.
  • [0024]
    A semiconductor wafer generally includes an active surface having semiconductor devices disposed thereon, and a backside surface formed with bulk semiconductor material, e.g., silicon. The active side surface contains a plurality of semiconductor die. The active surface is formed by a variety of semiconductor processes, including layering, patterning, doping, and heat treatment. In the layering process, semiconductor materials are grown or deposited on the substrate by techniques involving thermal oxidation, nitridation, chemical vapor deposition, evaporation, and sputtering. Photolithography involves the masking of areas of the surface and etching away undesired material to form specific structures. The doping process injects concentrations of dopant material by thermal diffusion or ion implantation.
  • [0025]
    Flip chip semiconductor packages and wafer level packages (WLP) are commonly used with integrated circuits (ICs) demanding high speed, high density, and greater pin count. Flip chip style semiconductor device 10 involves mounting an active area 12 of die 14 facedown toward a chip carrier substrate or printed circuit board (PCB) 16, as shown in FIG. 1. Active area 12 contains active and passive devices, conductive layers, and dielectric layers according to the electrical design of the die. Analog circuits may be created by the combination of one or more passive device formed within active area 12 and may be electrically interconnected. For example, an analog circuit may include one or more inductor, capacitor and resistor formed within active area 12. The electrical and mechanical interconnect is achieved through a solder bump structure 20 comprising a large number of individual conductive solder bumps or balls 22. The solder bumps are formed on bump pads or interconnect sites 24, which are disposed on active area 12. The bump pads 24 connect to the active circuits by conduction tracks in active area 12. The solder bumps 22 are electrically and mechanically connected to contact pads or interconnect sites 26 on carrier substrate 16 by a solder reflow process. The flip chip semiconductor device provides a short electrical conduction path from the active devices on die 14 to conduction tracks on carrier substrate 16 in order to reduce signal propagation, lower capacitance, and achieve overall better circuit performance.
  • [0026]
    Further detail of forming a semiconductor package in accordance with semiconductor device 10 is shown in FIGS. 2 a-2 f. In FIG. 2 a, a dummy or sacrificial metal carrier 30 is shown. Metal carrier 30 is made with copper (Cu), aluminum (Al), or other stiff material. Carrier 30 can also be flexible tape. A photoresist layer 32 is deposited on metal carrier 30. A plurality of openings is formed by a photo patterning process to define areas for selective plating. Contact pads 34 are then selectively plated on photoresist defined opening areas. Contact pads 34 can be made with Cu, tin (Sn), nickel (Ni), gold (Au), or silver (Ag). Metal carrier 30 serves as a support member and plating current path for the electroplating process to form wettable metal contact pads 34 on the metal carrier. Part or all of photoresist 32 is removed by a resist stripper. Alternatively, a layer of photoresist 32 may remain between contact pads 34.
  • [0027]
    In FIG. 2 b, semiconductor die 36 and 40 are mounted to contact pads 34 on metal carrier 30 with solder bumps 38 and 42, respectively. Alternatively, discrete components or other semiconductor packages can be mounted to contact pads 34. An optional underfill material can be formed below semiconductor die 36 and 40. A molding compound 44 is formed around semiconductor die 36 and 40 to encapsulate the die, interconnections, and contact pads. The metal carrier is removed by an etching process to expose contact pads 34 as shown in FIG. 2 c.
  • [0028]
    In FIG. 2 d, the semiconductor die are inverted such that contact pads 34 face upward. An optional process carrier 50 is mounted to a backside of the semiconductor die using adhesive layer 48 to support the package. The adhesive layer can be made with thermally or ultraviolet (UV) light releasable temporary adhesive, typically having a glass transition temperature (Tg) of at least 150 C. A conductive layer 46 is sputtered and patterned, or selectively plated, on a surface of molded compound 44 using an adhesion layer, such as titanium (Ti). Conductive layer 46 is made with Cu, Al, Au, or alloys thereof. Conductive layer 46 electrically connects to contact pads 34 according to the electrical function and interconnect requirements of semiconductor die 36 and 40.
  • [0029]
    In FIG. 2 e, an insulating layer 51 is formed over molding compound 44 and conductive layer 46. The insulating layer 51 can be made with single or multiple layers of photosensitive polymer material or other dielectric material having low cure temperature, e.g. less than 200 C. A portion of insulating layer 51 is removed by an etching process, such as photo patterning or chemical etching, to form openings and expose conductive layer 46. A conductive layer 52 is formed over insulating layer 51 to electrically contact conductive layer 46. An insulating layer 54 is formed over conductive layer 52 and insulating layer 51. The insulating layer 54 can be made with single or multiple layers of photosensitive polymer material or other dielectric material having low cure temperature, e.g. less than 200 C. A portion of insulating layer 54 is removed by an etching process, such as photo patterning or chemical etching, to form openings and expose conductive layer 52. Conductive layers 46 and 52 and insulating layers 51 and 54 constitute a portion of an interconnect structure which routes electrical signals between semiconductor die 36 and 40, as well as external to the package. Additional insulating layers and conductive layers can be used in the interconnect structure.
  • [0030]
    In FIG. 2 f, an electrically conductive solder material is deposited over conductive layer 52 through an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The solder material can be any metal or electrically conductive material, e.g., Sn, lead (Pb), Ni, Au, Ag, Cu, bismuthinite (Bi) and alloys thereof. The solder material is reflowed by heating the conductive material above its melting point to form spherical balls or bumps 56. In some applications, solder bumps 56 are reflowed a second time to improve electrical contact to conductive layer 52. An additional under bump metallization can optionally be formed under solder bumps 56. The interconnections can be solder bumps or bond wires.
  • [0031]
    Process carrier 50 and adhesive layer 48 are removed. Alternatively, process carrier 50 and adhesive layer 48 can remain attached to the semiconductor device and operate as a heat sink for thermal dissipation or electromagnetic interference (EMI) barrier.
  • [0032]
    FIG. 3 illustrates the semiconductor device from FIGS. 2 a-2 f with semiconductor device 58 electrically connected to solder bumps 56. In addition, wire bonds 60 are electrically connected to conductive layer 52. Bond wires 62 extend from wire bonds 60 to other semiconductor devices or external electrical connections. Solder bumps 56 and bond wires 62 provide electrical interconnect for semiconductor die 36 and 40.
  • [0033]
    Another embodiment of the initial stages of making the semiconductor device is shown in FIGS. 4 a-4 c. In FIG. 4 a, a dummy or sacrificial metal carrier 70 is shown. Metal carrier or foil 70 can be circular or rectangular and made with Cu or Al. A process carrier 72 is mounted to carrier 70 with adhesive layer 74. A photoresist layer 76 is deposited on metal carrier 70. A plurality of openings is formed by a photo patterning process to define areas for selective plating. Contact pads 78 are then selectively plated on photoresist defined opening areas. Contact pads 78 can be made with Cu, Sn, Ni, Au, or Ag. Metal carrier 70 serves as a support member and plating current path for the electroplating process to form wettable metal contact pads 78 on the metal carrier. Photoresist 76 is removed by a resist stripper.
  • [0034]
    In FIG. 4 b, semiconductor die 80 and 84 are mounted to contact pads 78 on metal carrier 70 with solder bumps 82 and 86, respectively. Alternatively, discrete components or other semiconductor packages can be attached to contact pads 78. An optional underfill material can be formed below semiconductor die 80 and 84. A molding compound 88 is formed all around semiconductor die 80 and 84 to encapsulate the die, interconnections, and contact pads. Process carrier 72 and adhesive 74 are released first, followed by removal of metal carrier 70 by an etching process to expose contact pads 78 as shown in FIG. 4 c.
  • [0035]
    The interconnect structure is then formed using the steps described in FIGS. 2 d-2 f. More specifically, a first conductive layer like 46 is sputtered and patterned, or selectively plated, on a surface of molded compound 88 using an adhesion layer, such as Ti. The first conductive layer electrically connects to contact pads 78 according to the electrical function and interconnect requirements of semiconductor die 80 and 84. A first insulating layer like 51 is formed over molding compound 88 and the first conductive layer. The first insulating layer can be made with single or multiple layers of photosensitive polymer material or other dielectric material having low cure temperature, e.g. less than 200 C. A portion of the first insulating layer is removed by an etching process to form openings and expose the first conductive layer. A second conductive layer like 52 is formed over the first insulating layer to electrically contact the first conductive layer. A second insulating layer like 54 is formed over the first conductive layer and first insulating layer. The second insulating layer can be made with single or multiple layers of photosensitive polymer material or other dielectric material having low cure temperature, e.g. less than 200 C. A portion of the second insulating layer is removed by an etching process to form openings and expose the second conductive layer. Solder bumps like 56 can be formed on the exposed second conductive layer. The first and second conductive layers and first and second insulating layers constitute a portion of an interconnect structure which routes electrical signals between semiconductor die 80 and 84, as well as external to the package. Additional insulating layers and conductive layers can be used in the interconnect structure.
  • [0036]
    FIG. 5 illustrates an embodiment of the semiconductor device. Contact pads 94 are formed using a dummy or sacrificial metal carrier as described in FIG. 2 a. Semiconductor die 90 and 98 are mounted to contact pads 94 on the metal carrier with wire bonds 96 and 100, respectively. A molding compound 101 is formed all around semiconductor die 90 and 98 to encapsulate the die, wire bonds, and contact pads, similar to FIG. 2 b. The metal carrier is removed by an etching process to expose contact pads 94, in the same manner as described in FIG. 2 c.
  • [0037]
    A process carrier is applied to a backside of the semiconductor die using an adhesive layer to support the package. A conductive layer 102 is selectively plated on a surface of molded compound 101 using an adhesion layer, such as Ti. Conductive layer 102 electrically connects to contact pads 94 according to the electrical function and interconnect requirements of semiconductor die 90 and 98.
  • [0038]
    An insulating layer 103 is formed over molding compound 101 and conductive layer 102. The insulating layer 103 can be made with material having dielectric properties. A portion of insulating layer 103 is removed by an etching process to form openings and expose conductive layer 102. A conductive layer 104 is formed over insulating layer 103 to electrically contact conductive layer 102. An insulating layer 106 is formed over conductive layer 104 and insulating layer 103. The insulating layer 106 can be made with material having dielectric properties. A portion of insulating layer 106 is removed by an etching process to form openings and expose conductive layer 104. Conductive layers 104 and 106 and insulating layers 103 and 106 constitute a portion of an interconnect structure to route electrical signals between semiconductor die 90 and 98 as well as external to the package. Additional insulating layers and conductive layers can be used in the interconnect structure.
  • [0039]
    An electrically conductive solder material is deposited over conductive layer 104 through an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The solder material can be any metal or electrically conductive material, e.g., Sn, Pb, Ni, Au, Ag, Cu, Bi, and alloys thereof. The solder material is reflowed by heating the conductive material above its melting point to form spherical balls or bumps 108. In some applications, solder bumps 108 are reflowed a second time to improve electrical contact to conductive layer 104. An additional under bump metallization can optionally be formed under solder bumps 108. The interconnections can be solder bumps or bond wires.
  • [0040]
    FIGS. 6 a-6 b illustrates an embodiment of the semiconductor device using a front-side and backside process carrier. In FIG. 6 a, contact pads 124 are formed using a dummy or sacrificial metal carrier, as described in FIG. 2 a. Semiconductor die 120 and 126 are mounted to contact pads 124 on the metal carrier with solder bumps 122 and 128, respectively. A molding compound 130 is formed around semiconductor die 120 and 126 to encapsulate the die, interconnect, and contact pads, similar to FIG. 2 b. The metal carrier is removed by an etching process to expose contact pads 124, in the same manner as described in FIG. 2 c.
  • [0041]
    A process carrier is applied to a backside of the semiconductor die using an adhesive layer to support the package. A conductive layer 136 is selectively plated on a surface of molded compound 130 using an adhesion layer, such as Ti. Conductive layer 136 electrically connects to contact pads 124 according to the electrical function and interconnect requirements of semiconductor die 120 and 126.
  • [0042]
    An insulating layer 138 is formed over molding compound 130 and conductive layer 136. The insulating layer 138 can be made with materials having dielectric properties. A portion of insulating layer 138 is removed by an etching process to form openings and expose conductive layer 136. A conductive layer 140 is formed over insulating layer 138 to electrically contact conductive layer 136. An insulating layer 142 is formed over conductive layer 140 and insulating layer 138. The insulating layer 142 can be made with material having dielectric properties. A portion of insulating layer 142 is removed by an etching process to form openings and expose conductive layer 140. Conductive layers 136 and 140 and insulating layers 138 and 142 constitute a portion of a front-side interconnect structure which routes electrical signals between semiconductor die 120 and 126, as well as external to the package. Additional insulating layers and conductive layers can be used in the front-side interconnect structure.
  • [0043]
    A front-side process carrier 146 is mounted to conductive layer 140 and insulating layer 142 using adhesive layer 144. The adhesive layer 144 can be made with thermally or UV light releasable temporary adhesive, typically having a Tg of at least 150 C. The front-side process carrier can be flexible tape or stiff material. The backside process carrier is removed. Vias are formed through molding compound 130 using laser drilling or deep reactive ion etch (DRIE). The vias expose contact pads 124. Conductive material 148 is deposited in the vias and electrically connects to contact pads 124. An insulating layer 150 is formed over conductive layer 148 and molding compound 130. The insulating layer 150 can be made with material having dielectric properties. A portion of insulating layer 150 is removed by an etching process to form openings and expose conductive layer 148. Conductive layer 148 and insulating layer 150 constitute a portion of a backside interconnect structure which routes electrical signals between semiconductor die 120 and 126, as well as external to the package. Additional insulating layers and conductive layers can be used in the backside interconnect structure.
  • [0044]
    In FIG. 6 b, an electrically conductive solder material is deposited over conductive layer 140 through an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The solder material can be any metal or electrically conductive material, e.g., Sn, Pb, Ni, Au, Ag, Cu, Bi, and alloys thereof. The solder material is reflowed by heating the conductive material above its melting point to form spherical balls or bumps 152. In some applications, solder bumps 152 are reflowed a second time to improve electrical contact to conductive layer 140. An additional under bump metallization can optionally be formed under solder bumps 152. For the backside interconnects, solder bump or wire bond interconnects are formed on conductive layer 148 or the outermost layer.
  • [0045]
    The semiconductor device in FIG. 7 follows a similar construction as described in FIGS. 6 a-6 b, with the exception that metal pillars 154 are formed by selective etching, using contact pads 124 as etching mask. Pillars 154 are made with Cu, Al, or alloys thereof. Metal pillars 154 facilitate depositing molded underfill material below semiconductor die 120 and 126 due to the elevated interconnect structure. Metal pillars 154 further facilitate the formation of vias by laser drilling or DRIE process as the via depth can be reduced. The semiconductor device experiences less thermal stress or thermal strain with the higher interconnection structure.
  • [0046]
    FIG. 8 shows the semiconductor device of FIG. 7 with contact pads 124 and semiconductor die 120 elevated by metal pillars 154. Semiconductor die 158 is mounted to insulating layer 138 with die attach adhesive 160 and electrically connected to contact pads 124 and metal pillars 154 with wire bonds 162. The die attach adhesive 160 can be made with epoxy based or film based adhesive.
  • [0047]
    In FIG. 9, the semiconductor device of FIG. 6 b has underfill material 164. The underfill material can be made with resin having proper Theological and dielectric properties.
  • [0048]
    In FIG. 10, the semiconductor device of FIG. 6 b has semiconductor die 166 physically mounted to and electrically connected through solder bumps 152. Semiconductor die 168 is physically mounted to insulating layer 142 with die attach material 170 and electrically connected to conductive layer 140 with wire bonds 172. A molding compound 174 is applied over semiconductor die 166 and 168 and associated interconnect structures.
  • [0049]
    FIG. 11 shows the semiconductor device of FIG. 2 f with process carrier 176 and adhesive layer 178 remaining as a heat sink for thermal dissipation or EMI shield.
  • [0050]
    FIG. 12 shows the semiconductor device of FIG. 2 f with a layer of photoresist 180 remaining between contact pads 124.
  • [0051]
    In summary, the semiconductor device employs a copper sheet as a dummy or sacrificial carrier. A plurality of wettable contact pads is patterned on the sacrificial carrier. The individual semiconductor die are mounted to the sacrificial carrier and are electrically connected to the contact pads. The semiconductor die and contact pads are encapsulated with a molding compound. The sacrificial carrier is removed to expose the metal pads. An interconnect build-up layer is formed on the contact pads. The wettable contact pads are selectively plated on the sacrificial metal carrier to provide a highly accurate alignment of the bonding pad positions for the electrical interconnect according to the electrical function of the semiconductor die. By forming contact pads on the sacrificial carrier, a precise placement and alignment for the later formed requisite interconnect structure can be achieved. Accordingly, the semiconductor package has greater interconnect density and lower line pitch for individual traces.
  • [0052]
    While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US6344401 *9 Mar 20005 Feb 2002Atmel CorporationMethod of forming a stacked-die integrated circuit chip package on a water level
US6396153 *25 Jan 200128 May 2002General Electric CompanyCircuit chip package and fabrication method
US6838776 *18 Apr 20034 Jan 2005Freescale Semiconductor, Inc.Circuit device with at least partial packaging and method for forming
US6867471 *29 Aug 200315 Mar 2005Infineon Technologies AgUniversal package for an electronic component with a semiconductor chip and method for producing the universal package
US6902950 *10 May 20027 Jun 2005Intel CorporationMethod to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US6921975 *18 Apr 200326 Jul 2005Freescale Semiconductor, Inc.Circuit device with at least partial packaging, exposed active surface and a voltage reference plane
US7045391 *18 Aug 200416 May 2006Advanced Semiconductor Engineering, Inc.Multi-chips bumpless assembly package and manufacturing method thereof
US20040106288 *22 Sep 20033 Jun 2004Yusuke IgarashiMethod for manufacturing circuit devices
US20040262735 *24 May 200430 Dec 2004Mitsutoshi HigashiSemiconductor device and production method thereof
US20050184377 *27 Jan 200525 Aug 2005Shinko Electric Industries Co., Ltd.Semiconductor device and method of manufacturing the same
US20050287703 *28 Jun 200429 Dec 2005Semiconductor Components Industries, Llc.Multi-chip semiconductor connector assembly method
US20060208356 *10 Mar 200621 Sep 2006Shinko Electric Industries Co., Ltd.Wiring board and method of manufacturing the same
US20080138935 *8 Aug 200712 Jun 2008Siliconware Precision Industries Co., Ltd.Chip scale package structure and method for fabricating the same
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8003515 *18 Sep 200923 Aug 2011Infineon Technologies AgDevice and manufacturing method
US8143099 *5 May 200927 Mar 2012Samsung Electro-Mechanics Co., Ltd.Method of manufacturing semiconductor package by etching a metal layer to form a rearrangement wiring layer
US828820125 Aug 201016 Oct 2012Stats Chippac, Ltd.Semiconductor device and method of forming FO-WLCSP with discrete semiconductor components mounted under and over semiconductor die
US8338945 *23 Nov 201025 Dec 2012Taiwan Semiconductor Manufacturing Company, Ltd.Molded chip interposer structure and methods
US845601817 Oct 20114 Jun 2013Samsung Electronics Co., Ltd.Semiconductor packages
US8492203 *20 Jun 201123 Jul 2013Stats Chippac, Ltd.Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layers
US8497587 *30 Dec 200930 Jul 2013Stmicroelectronics Pte Ltd.Thermally enhanced expanded wafer level package ball grid array structure and method of making the same
US858140212 Dec 201212 Nov 2013Taiwan Semiconductor Manufacturing Company, Ltd.Molded chip interposer structure and methods
US8597986 *1 Sep 20113 Dec 2013Taiwan Semiconductor Manufacturing Co., Ltd.System in package and method of fabricating same
US8728929 *17 Dec 201020 May 2014Nxp B.V.Pre-soldered leadless package
US8729397 *13 Dec 201120 May 2014Unimicron Technology Corp.Embedded structure
US883611416 Nov 201216 Sep 2014Stats Chippac, Ltd.Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers
US89211634 Jun 201330 Dec 2014Samsung Electronics Co., Ltd.Semiconductor packages and methods of fabricating the same
US8928148 *12 Sep 20116 Jan 2015Stmicroelectronics (Grenoble 2) SasSemiconductor component and device provided with heat dissipation means
US895183915 Mar 201010 Feb 2015Stats Chippac, Ltd.Semiconductor device and method of forming conductive vias through interconnect structures and encapsulant of WLCSP
US8957530 *8 Feb 201117 Feb 2015Stats Chippac Ltd.Integrated circuit packaging system with embedded circuitry and post
US897511127 Jun 201110 Mar 2015Stats Chippac, Ltd.Wafer level die integration and method therefor
US9034730 *28 Jan 201119 May 2015Marvell World Trade Ltd.Recessed semiconductor substrates and associated techniques
US9129908 *15 Nov 20118 Sep 2015Cisco Technology, Inc.Manufacturing a semiconductor package including an embedded circuit component within a support structure of the package
US91535292 Apr 20146 Oct 2015Nxp B.V.Pre-soldered leadless package
US9177901 *26 Mar 20123 Nov 2015Stats Chippac, Ltd.Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars
US924038014 Dec 201219 Jan 2016Stats Chippac, Ltd.Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
US9263301 *7 Sep 201216 Feb 2016STARS ChipPAC, Ltd.Semiconductor device and method of forming Fo-WLCSP with discrete semiconductor components mounted under and over semiconductor die
US926336113 Apr 201216 Feb 2016Stats Chippac, Ltd.Semiconductor device having a vertical interconnect structure using stud bumps
US926959523 Feb 201223 Feb 2016Stats Chippac, Ltd.Semiconductor device with thin profile WLCSP with vertical interconnect over package footprint
US93850743 Jul 20135 Jul 2016STATS ChipPAC Pte. Ltd.Semiconductor package with embedded die
US939104518 May 201512 Jul 2016Marvell World Trade Ltd.Recessed semiconductor substrates and associated techniques
US940665817 Dec 20102 Aug 2016Advanced Semiconductor Engineering, Inc.Embedded component device and manufacturing methods thereof
US941449731 Jul 20159 Aug 2016Cisco Technology, Inc.Semiconductor package including an embedded circuit component within a support structure of the package
US952036527 Dec 201213 Dec 2016STATS ChipPAC Pte. Ltd.Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layers
US955896523 Feb 201231 Jan 2017STATS ChipPAC Pte. Ltd.Semiconductor device with thin profile WLCSP with vertical interconnect over package footprint
US96079499 Mar 201528 Mar 2017Kabushiki Kaisha ToshibaSemiconductor device having semiconductor chips in resin and electronic circuit device with the semiconductor device
US9607965 *25 Sep 201328 Mar 2017STATS ChipPAC Pte. Ltd.Semiconductor device and method of controlling warpage in reconstituted wafer
US964050425 Mar 20142 May 2017STATS ChipPAC Pte. Ltd.Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core
US9741688 *1 Jul 201622 Aug 2017Taiwan Semiconductor Manufacturing Company, Ltd.Method for manufacturing a semiconductor device
US20100144152 *5 May 200910 Jun 2010Samsung Electro-Mechanics Co., Ltd.Method of manufacturing semiconductor package
US20100285636 *26 Jun 200911 Nov 2010Acsip Technology Inc.Manufacturing method of a packaging structure of electronic components
US20100314746 *16 Oct 200916 Dec 2010Chueh-An HsiehSemiconductor package and manufacturing method thereof
US20110068484 *18 Sep 200924 Mar 2011Infineon Technologies AgDevice and manufacturing method
US20110127678 *8 Feb 20112 Jun 2011Il Kwon ShimIntegrated circuit packaging system with embedded circuitry and post
US20110147925 *17 Dec 201023 Jun 2011Nxp B.V.Pre-soldered leadless package
US20110156236 *30 Dec 200930 Jun 2011Stmicroelectronics Asia Pacific Pte Ltd.Thermally enhanced expanded wafer level package ball grid array structure and method of making the same
US20110186992 *28 Jan 20114 Aug 2011Albert WuRecessed semiconductor substrates and associated techniques
US20110221054 *15 Mar 201015 Sep 2011Stats Chippac, Ltd.Semiconductor Device and Method of Forming Conductive Vias Through Interconnect Structures and Encapsulant of WLCSP
US20120061849 *12 Sep 201115 Mar 2012Stmicroelectronics (Grenoble 2) SasSemiconductor component and device provided with heat dissipation means
US20120085569 *13 Dec 201112 Apr 2012Yi-Chun LiuEmbedded structure
US20120098123 *23 Nov 201026 Apr 2012Taiwan Semiconductor Manufacturing Company, Ltd.Molded Chip Interposer Structure and Methods
US20120181673 *26 Mar 201219 Jul 2012Stats Chippac, Ltd.Semiconductor Device and Method of Stacking Die on Leadframe Electrically Connected by Conductive Pillars
US20120187584 *20 Jun 201126 Jul 2012Stats Chippac, Ltd.Semiconductor Device and Method for Forming Semiconductor Package Having Build-Up Interconnect Structure Over Semiconductor Die with Different CTE Insulating Layers
US20130001771 *7 Sep 20123 Jan 2013Stats Chippac, Ltd.Semiconductor Device and Method of Forming FO-WLCSP with Discrete Semiconductor Components Mounted Under and Over Semiconductor Die
US20130015557 *13 Jul 201117 Jan 2013Zhiping YangSemiconductor package including an external circuit element
US20130122658 *15 Nov 201116 May 2013Cisco Technology, Inc.Manufacturing a semiconductor package including an embedded circuit component within a support structure of the package
US20150084213 *25 Sep 201326 Mar 2015Stats Chippac, Ltd.Semiconductor Device and Method of Controlling Warpage in Reconstituted Wafer
US20150279824 *28 Mar 20141 Oct 2015Vijay K. NairElectronic package and method of forming an electronic package
US20150325557 *11 May 201512 Nov 2015Xintec Inc.Chip package and method for forming the same
US20170133335 *27 Oct 201611 May 2017Nxp B.V.Semiconductor device and method of making a semiconductor device
US20170221863 *12 Apr 20173 Aug 2017Taiwan Semiconductor Manufacturing Company, Ltd.Semiconductor Device and Method
CN102054812A *17 Sep 201011 May 2011英飞凌科技股份有限公司Device and manufacturing method
EP2930742A3 *19 Feb 20159 Mar 2016Kabushiki Kaisha ToshibaSemiconductor device and electronic circuit device
WO2011103211A1 *16 Feb 201125 Aug 2011Cypress Semiconductor CorporationPanelized packaging with transferred dielectric
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