US20090020437A1 - Method and system for controlled material removal by electrochemical polishing - Google Patents

Method and system for controlled material removal by electrochemical polishing Download PDF

Info

Publication number
US20090020437A1
US20090020437A1 US10/902,241 US90224104A US2009020437A1 US 20090020437 A1 US20090020437 A1 US 20090020437A1 US 90224104 A US90224104 A US 90224104A US 2009020437 A1 US2009020437 A1 US 2009020437A1
Authority
US
United States
Prior art keywords
conductive layer
conductive
profile
electrode
electropolishing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/902,241
Inventor
Bulent M. Basol
Cyprian E. Uzoh
George Xinsheng Guo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Novellus Systems Inc
Original Assignee
Novellus Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/511,278 external-priority patent/US6413388B1/en
Priority claimed from US10/302,755 external-priority patent/US7204917B2/en
Application filed by Novellus Systems Inc filed Critical Novellus Systems Inc
Priority to US10/902,241 priority Critical patent/US20090020437A1/en
Assigned to ASM NUTOOL, INC. reassignment ASM NUTOOL, INC. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: NUTOOL, INC.
Assigned to ASM NUTOOL, INC. reassignment ASM NUTOOL, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GUO, GEORGE XINSHENG, BASOL, BULENT M., UZOH, CYPRIAN E.
Assigned to NOVELLUS SYSTEMS, INC. reassignment NOVELLUS SYSTEMS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ASM NUTOOL, INC.
Publication of US20090020437A1 publication Critical patent/US20090020437A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/11Lapping tools
    • B24B37/12Lapping plates for working plane surfaces
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/04Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/046Lapping machines or devices; Accessories designed for working plane surfaces using electric current
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25FPROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00Electrolytic etching or polishing
    • C25F3/16Polishing
    • C25F3/30Polishing of semiconducting materials
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25FPROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F7/00Constructional parts, or assemblies thereof, of cells for electrolytic removal of material from objects; Servicing or operating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]
    • H01L21/32125Planarisation by chemical mechanical polishing [CMP] by simultaneously passing an electrical current, i.e. electrochemical mechanical polishing, e.g. ECMP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to manufacture of semiconductor integrated circuits and, more particularly to a method for electrochemically or electrochemical-mechanically polishing of conductive layers.
  • Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric layers and conductive paths or interconnects made of conductive materials. Interconnects are usually formed by filling a conductive material in trenches etched into the dielectric layers. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in different layers can be electrically connected using vias or contacts.
  • a conductive material into features such as vias, trenches, pads or contacts
  • electrodeposition or electroplating a conductive material, such as copper is deposited over the substrate surface including into such features.
  • a material removal technique is employed to planarize and remove the excess metal from the top surface, leaving conductors only in the features or cavities.
  • CMP chemical mechanical polishing
  • electropolishing is employed to planarize and remove excess metal layers deposited on semiconductor wafers.
  • CMP Chemical mechanical polishing
  • CMP process planarizes and reduce the thickness of the copper layer to the level of the barrier layer coating the top surface so that copper is only left inside the etched features.
  • CMP can further remove all of the conductors from the top surface so that copper-filled features are electrically isolated from one another.
  • CMP process is a costly and time-consuming process that reduces production efficiency.
  • CMP can be used with the conventional interlayer dielectrics, it may create problems with porous low-k dielectrics because of the mechanical force applied on the wafer surface during the CMP process. During the CMP step, the porous low-k materials may be stressed and may delaminate or other defects may form due to the low mechanical strength of such materials.
  • Another material removal technique involves well-known electropolishing processes. During an electropolishing process, both the material to be removed and a conductive electrode remain in an electropolishing solution. Typically, an anodic (positive) voltage is applied to the material to be removed with respect to the conductive electrode. With the applied voltage, the material is electrochemically dissolved and removed from the wafer surface.
  • electropolishing process can be used to reduce the thickness of the overburden or excess copper layers deposited on the semiconductor substrates, as exemplified in FIG. 1 .
  • Copper 10 is electrodeposited on a dielectric layer 12 that is previously formed on the semiconductor substrate 14 .
  • Features 16 as well as the surface 20 of the dielectric layer 14 are filled with copper 10 .
  • a barrier layer 22 such as Tantalum layer and a copper seed layer (not shown) are coated in the features and the surface of the dielectric layer 12 .
  • the conventional method for removal of the excess copper from the surface 20 is CMP.
  • electropolishing can also be used to reduce the thickness of this copper layer to an exemplary level indicated by dashed line 24 , or even eliminate all copper from the surface as indicated by line 25 .
  • the electropolishing process needs to be highly efficient and uniform.
  • the electropolishing technique should provide capability to tune the removal rate profile to match the initial copper thickness profile on the wafer.
  • Present invention provides an electrochemical or electrochemical mechanical material removal system and an electrochemical or electrochemical mechanical material removal method employing a device made of a conductive material.
  • the device is positioned between an electrode of the system and a conductive surface of a workpiece that is being electrochemically removed.
  • the device includes openings or pores, which allow a process solution, such as an electroetching or electropolishing solution, to flow through the device.
  • the solution contacts the electrode, the device and the conductive surface when a material removal potential is applied between the conductive surface (anode) and the electrode (cathode).
  • material removal rate is controlled by adjusting the distance between the conductive surface and a device surface that faces the conductive surface.
  • material removal profile from the conductive surface can be controlled with the geometry or topography of the device surface.
  • a device surface when placed substantially parallel to the conductive surface, the electropolishing of the conductive surface is efficient and produces a substantially uniform material removal rate.
  • a device surface with a center high and edge low profile causes a material removal rate which is higher near the center of the conductive surface.
  • a device surface with an edge high and center low profile causes a material removal rate which is lower near the center of the conductive surface.
  • FIG. 1 is a schematic illustration of a substrate having an electroplated copper layer
  • FIG. 2 is a schematic illustration of an embodiment of an electropolishing system of the present invention
  • FIG. 3 is a graph shoving a conventional electropolishing removal profile and an electropolishing removal profile of the present invention
  • FIG. 4 is a schematic illustration of another embodiment of an electropolishing system of the present invention.
  • FIG. 5A is a schematic illustration of an embodiment of a conductive element of the present invention.
  • FIG. 5B is a graph shoving an electropolishing removal profile obtained using the conductive element shown in FIG. 5A ;
  • FIG. 6A is a schematic illustration of another embodiment of a conductive element of the present invention.
  • FIG. 6B is a graph shoving an electropolishing removal profile obtained using the conductive element shown in FIG. 6A ;
  • FIG. 7A is a schematic plan view of an embodiment of a conductive element of the present invention.
  • FIG. 7B is a schematic side view of an embodiment of the conductive element of the present invention shown in FIG. 7A ;
  • FIGS. 8A-8C are schematic illustrations of a conductive element with movable sections
  • FIGS. 9A-9B are schematic illustrations of embodiments of various conductive elements.
  • FIG. 10 is a schematic illustration of a switch system for electrochemically cleaning the conductive element at process intervals.
  • the Present invention provides an electropolishing system and a method using a conductive member positioned between an electrode and a workpiece surface that is being electropolished.
  • the conductive member may be a perforated or porous plate, which allows a process solution to flow through it.
  • the electropolishing solution contacts the electrode, the conductive member and the workpiece surface while an electropolishing potential is applied between the workpiece surface (anode) and the electrode (cathode).
  • Material removal rate may be controlled by adjusting the distance between the conductive member surface and the workpiece surface as well by the adjustment of the voltage applied between (or current passing through) the workpiece surface and the electrode. In this respect, as the conductive member surface gets closer to the workpiece surface, the material removal rate is increased.
  • material removal profile from the workpiece surface can be controlled with the geometry or topography of the conductive member surface that faces the workpiece surface. For example, if the conductive member surface is flat and parallel to the workpiece surface, the electropolishing of the workpiece surface produces a substantially uniform removal rate. If the conductive member surface has a center high and edge low profile, material removal rate at the center of the workpiece surface is higher than the edge of the workpiece. As a result, electropolishing process results in a center low profile for the removal rate. Similarly, if the conductive member has an edge high and center low profile, the material etching or polishing rate at the center of the workpiece surface will be lower than the edge of the workpiece. This, in turn, results in a removal rate profile, which is edge low.
  • the profile of the conductive member surface refers to three dimensional shape of the surface or topography of the surface.
  • FIG. 2 shows an exemplary electropolishing system 100 to perform process of the present invention.
  • the system 100 comprises a carrier 102 to hold a workpiece 104 or a wafer, an electrode 106 placed across the wafer 104 and a conductive member 108 positioned between a front surface 110 of the wafer 104 and the electrode 106 .
  • the conductive member 108 may be a conductive perforated plate and, in this embodiment, is not connected to any power source. Since the described process is an electrochemical removal or electropolishing process, the electrode 106 becomes cathode of the system 100 while the front surface 110 of the wafer 104 becomes the anode. In other words, the front surface 110 may be defined as anodic compared to the cathode electrode 106 .
  • the conductive member 108 although not connected to any power source, is electrically more cathodic compared to the front surface 110 of the wafer and more anodic compared to the cathode electrode 106 . Further, since the conductive member 108 is between the front surface 110 and the electrode 106 , which is a cathode, its voltage is expected to be positive but lower than the front surface voltage of the wafer 104 .
  • the front surface 110 and the electrode 106 are connected to a power supply 112 through electrical contacts (not shown).
  • the electrical contacts may be conductive brushes contacting the perimeter of the wafer 104 while the wafer is moved or rotated. Such electrical contacts are described in U.S.
  • the wafer 104 may be a semiconductor wafer and the front surface 110 may include a previously deposited copper layer to be electropolished, such as exemplified in FIG. 1 .
  • the carrier 102 is able to rotate and move wafer 104 vertically and laterally during the process.
  • the conductive member 108 includes a first surface 114 and a second surface 116 and a plurality of openings 118 extending between the first and the second surfaces.
  • the first surface 114 faces the front surface 110 of the wafer 104
  • the second surface 116 is placed across the electrode 106 .
  • the first surface 114 is flat and placed parallel to the front surface 110 to facilitate uniform electropolishing of the front surface.
  • the first surface 114 of the conductive member 108 may have different geometrical profiles to shape removal profile of the front surface 110 of the wafer 104 .
  • a plurality of openings 118 extends between the first surface 114 and the second surface 116 of the conductive member 108 .
  • a process solution 120 such as an electropolishing solution flow through the openings 118 .
  • the conductive member 108 divides system 100 into two sections, namely a cathodic section 122 and an anodic section 124 . Openings 118 allow the electropolishing solution 120 to flow between the cathodic section 122 and the anodic section 124 of the system 100 .
  • the electropolishing solution 120 is in contact with the cathode electrode 106 and the conductive member 108
  • the solution 120 is in contact with the front surface 110 (conductive surface) of the wafer 104 and the conductive member 108 .
  • FIG. 2 exemplifies the cathode electrode 106 , the conductive member 108 and the wafer 104 in a lateral configuration, they can be aligned vertically or in upside down geometry and this is within the scope of this invention.
  • the conductive member 108 is made of a conductive material, such as a metal or metal alloy, or coated with a conductive material.
  • the conductive member 108 can also be a conductive porous material or a mesh, instead of having openings 118 which are well defined, as shown in FIG. 2 . However, in any case the conductive member should allow solution flow between the anodic section and the cathodic section.
  • the conductive member 108 is separated from the front surface of the wafer 104 by a distance d 1 and from the electrode 106 by a distance d 2 .
  • the distance d 1 is smaller than the distance d 2 .
  • the distance between the front surface 110 of the wafer 104 and the electrode is d 3 .
  • d 2 may be larger than 50 millimeters (mm) and d 1 is smaller than 5 mm.
  • the front surface of the wafer 104 is moved closer to the first surface 114 of the conductive member 108 while the electropolishing solution 120 is flowed through the conductive member 108 .
  • a potential difference is applied between the front surface and the electrode 106 to electropolish the copper of the front surface 110 .
  • the distance d 1 is 2-4 mm.
  • the front surface 110 of the wafer 104 may get very close to the first surface of the conductive member 108 but it never touches the conductive member.
  • the front surface 110 of the wafer may be occasionally or continuously swept with a pad material (not shown) during the electrochemical removal process.
  • the sweeping process may be used to planarize the front surface 110 as it is electropolished.
  • An example of use of pad material during electrochemical mechanical processes can be found in U.S. application Ser. No. 09/607,567 entitled Method and Apparatus for Electrochemical Mechanical Deposition, filed Jun. 29, 2000, which is owned by the assignee of the present application and which is incorporated herein by reference. This process is sometimes referred to as electrochemical mechanical etching (ECME) or electrochemical mechanical polishing (ECMP).
  • the pad material may be mounted on the first surface 114 of the conductive member itself.
  • the pad material may have openings to let the process solution flow through or it may be made of a porous pad material.
  • the pad material may also be attached on the first surface 114 of the conductive member 108 as pad pieces or strips.
  • the electropolishing solution 120 is shown to flow from the cathode electrode 106 towards the front surface 110 of the wafer 104 . This is the preferred process solution flow direction.
  • the present invention can be also performed by reversing the direction of the process solution.
  • the process solution does not flow but forms a process solution pool in which electropolishing is carried out.
  • the electropolishing solution 120 may be re-circulated after filtering and cleaning.
  • the curve 132 shows material removal profile across the diameter of the wafer 104 when the electropolishing process of the present embodiment is applied. Removal profile depicted in curve 132 shows a flat removal profile with less than 2% non-uniformity. As shown in FIG. 3 for comparison reasons, when the same electropolishing process is repeated after replacing the conductive member 108 with a non-conductive member or by taking it out of the process solution altogether, the removal profile depicted with curve 134 is non-uniform and consequently non-repeatable. It should be appreciated that when the electrochemical removal process is applied to a large numbers of wafers, copper removed from the wafer surface is mostly deposited on the electrode surface.
  • this copper may be porous or powdery and as it deposits on the electrode it may change the shape of the electrode and its surface conductance. Consequently, in time, as more and more wafers are processed, electric field lines between the electrode and the substrate are expected to change. This causes changes in the material removal profiles. In other words, the removal profile may not be repeatable for processing large number of wafers. This is not acceptable in a semiconductor IC production environment. Presence of the conductive element, which is positioned very close to the front surface of the wafer, assures uniform copper removal rate irrespective of the number of wafers processed.
  • FIG. 4 shows another exemplary system to perform the electropolishing process of the present invention.
  • a conductive member 202 encloses a solution chamber 203 including a cathode electrode 204 in a process solution 205 .
  • the process solution 205 may be an electropolishing solution or electrolyte.
  • the cathode electrode 204 does not have to be in the solution chamber 203 . It may be placed at a different location as long as there is fluid communication between it and the solution chamber 203 through the process solution 205 .
  • a wafer carrier 206 holds a conductive surface 208 of a workpiece 209 or wafer close to an upper surface 210 of the conductive member 202 .
  • Process solution 205 is delivered into the solution chamber 203 through a delivery port 214 and flowed through openings 216 of the conductive member 202 towards the conductive surface 208 of the wafer 204 .
  • wafer 209 is rotated and/or laterally moved above the upper surface 210 of the conductive member 202 while a potential difference is applied between the conductive surface 208 and the cathode electrode 204 from a power source 218 .
  • sidewalls 220 of the solution chamber 203 are made of a non-conductive, isolating material to prevent electrical shorting between the cathode electrode 204 and the conductive member 202 .
  • a filter element may be attached to a lower surface 222 of the conductive member 202 to reduce or eliminate particles that may come to the front surface 208 of the wafer 209 .
  • Another filter element may be placed over the cathode electrode 204 confining particles generated on the electrode during the process to the region close to the electrode.
  • the conductive members can be shaped depending on desired removal profile of the conductive surface of the wafer.
  • FIG. 5A shows a conductive member 300 with center high design with openings 302 extending between a first surface 304 and a second surface 306 .
  • the first surface 304 has a convex shape.
  • the conductive surface 310 of the wafer 312 faces the first surface 304 .
  • the center high shape of the first surface 304 is exaggerated.
  • the height ‘h’ of the convex surface may be in the range of 0.5-3 mm or less.
  • electropolishing process with the conductive member 300 yields a center high material removal profile.
  • FIG. 6A shows another example of a conductive member 400 with edge high design with openings 402 extending between a first surface 404 and a second surface 406 .
  • the first surface 404 has a concave shape.
  • the conductive surface 410 of the wafer 412 faces the first surface 404 .
  • depth ‘d’ of the surface may be in the range of 0.5-3 mm or less.
  • electropolishing process with the conductive member 400 yields a center low and edge high material removal profile.
  • the second surfaces 306 , 406 are shown flat in FIGS. 5A and 6A . It should be understood that shapes of these surfaces may be different. What is most effective in determining removal profile is the shape of the first surfaces 304 and 404 .
  • conductive member may have insulating or high resistivity portions juxtaposed with the conductive portions. Shape, geometry and the location of the insulating portions shape the removal profile.
  • a conductive member 500 having insulated regions 502 , 504 and conductive region 505 is shown in FIGS. 7A-7B .
  • the conductive member 500 has a first surface 506 and a second surface 508 . Openings 510 extend between the first and the second surfaces.
  • the insulated regions 502 , 504 of the conductive member 500 may be made of an electrical insulation material or may just be an electrically insulating film or layer partially coated or attached on the first surface of the conductive member 500 .
  • Insulated regions 502 , 504 as well as the conductive region 505 may not be co-planar but they may be formed as recesses or raised regions.
  • the insulated regions 502 , 504 may form the recessed regions and the conductive region 505 may form the raised region.
  • edge region of the front surface 512 is partially exposed to the insulated regions 502 , 504 and material removal from the edge region will be less than the center of the front surface 512 which is exposed to the conductive region 505 of the conductive member 500 .
  • This electropolishing process yields a center high removal profile similar to the one shown in FIG. 5B .
  • electrical contact to the front surface may be made along the edge of the wafer using conductive brush or other type contacts. Such contacts are described in the above mentioned U.S. application Ser. No. 10/282,930 which is incorporated herein by reference.
  • FIGS. 8A-8C exemplifies a conductive member 600 having movable sections 602 , 604 and 606 and openings 608 .
  • various configurations of the conductive member 600 may be obtained.
  • Such configurations can be used to obtain different material removal profiles that have been described above.
  • conductive member configuration shown in FIG. 8A can be used to obtain uniform material profiles.
  • Conductive member configuration shown in FIG. 8B can be used to obtain center high-edge low material removal profile and the configuration in FIG. 8C can be used to obtain center low-edge high material removal profile.
  • Conductive members may have discontinuous surface profiles including raised and recessed portions. Raised or recessed portions may be aligned along certain profiles.
  • FIG. 9A shows a conductive member 700 having raised portions 702 and recessed portions 704 formed along a primary surface 705 of the conductive member 700 . Openings 706 may be formed through the raised portions 702 and recessed portions 704 .
  • a plurality of raised portions 704 form a center high profile, which in turn enables center high material removal profile during the electropolishing.
  • the surface to be electropolished must face the raised and recessed portions, or primary surface 705 of the conductive member 700 , during the process.
  • FIG. 9B shows another conductive member 800 having raised portions 802 and recessed portions 804 formed along a primary surface 805 of the conductive member. Openings 806 are formed through the portions 802 and 804 .
  • raised portions 804 have the same height, which enables uniform material removal profile during the electropolishing.
  • the surface to be electropolished must face the raised and recessed portions, or primary surface of the conductive member, during the process.
  • the recessed portions may be coated with an insulating material leaving only the raised portions conductive and active during the process.
  • FIG. 10 illustrates a method for cleaning a conductive member 900 .
  • a conductive material accumulation may occur on the conductive member 900 since the conductive member is more cathodic compared to a conductive surface 902 of a wafer 904 . Therefore, conductive member needs to be cleaned with certain intervals.
  • One possible way of cleaning may be done by anodically polarizing the conductive member 900 and dissolving the accumulated material at certain intervals.
  • FIG. 10 shows one embodiment of the cleaning process. In this embodiment, when a switch 905 is connected position “A”, power source 906 applies a potential difference between the conductive surface 902 and the cathode electrode 907 .
  • the switch 905 For cleaning the conductive member 900 , the switch 905 is turned to position “B” and a potential difference, which may or may not be the same as the one applied when switch 905 was in “A” position, is applied between the conductive member 900 and the electrode 907 making the conductive member an anode. This action cleans the accumulated material on the conductive member 900 . After the cleaning, electropolishing process may continue on other wafers by moving the switch 905 to position “A”.

Abstract

A method and apparatus for electropolishing a conductive layer on a wafer is provided. The apparatus includes an electrode and a conductive member having openings permitting an electropolishing solution to flow through it. Surface of the conductive member includes a surface profile. During the electropolishing process, the surface of the conductive element is placed across from the conductive layer and a potential difference is applied between the conductive layer and the electrode. The process forms a conductive layer profile of the conductive layer.

Description

    RELATED APPLICATIONS
  • This application claims priority from Provisional Application Ser. No. 60/491,470 filed Jul. 30, 2003 (NT-305 P). This application is a continuation in part of U.S. patent application Ser. No. 10/302,755 filed Nov. 21, 2002 (NT-205); and U.S. patent application Ser. No. 10/152,793 filed May 23, 2002 (NT-102 D) which is a divisional application of U.S. patent application Ser. No. 09/511,278 filed Feb. 23, 2000 (NT-102), now U.S. Pat. No. 6,413,388, all incorporated herein by reference.
  • FIELD
  • The present invention relates to manufacture of semiconductor integrated circuits and, more particularly to a method for electrochemically or electrochemical-mechanically polishing of conductive layers.
  • BACKGROUND
  • Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric layers and conductive paths or interconnects made of conductive materials. Interconnects are usually formed by filling a conductive material in trenches etched into the dielectric layers. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in different layers can be electrically connected using vias or contacts.
  • The filling of a conductive material into features such as vias, trenches, pads or contacts, can be carried out by electrodeposition or electroplating. In electrodeposition method, a conductive material, such as copper is deposited over the substrate surface including into such features. Then, a material removal technique is employed to planarize and remove the excess metal from the top surface, leaving conductors only in the features or cavities. Conventionally, chemical mechanical polishing (CMP) and electropolishing is employed to planarize and remove excess metal layers deposited on semiconductor wafers.
  • Chemical mechanical polishing (CMP) process planarizes and reduce the thickness of the copper layer to the level of the barrier layer coating the top surface so that copper is only left inside the etched features. CMP can further remove all of the conductors from the top surface so that copper-filled features are electrically isolated from one another. However, CMP process is a costly and time-consuming process that reduces production efficiency. Furthermore, although CMP can be used with the conventional interlayer dielectrics, it may create problems with porous low-k dielectrics because of the mechanical force applied on the wafer surface during the CMP process. During the CMP step, the porous low-k materials may be stressed and may delaminate or other defects may form due to the low mechanical strength of such materials.
  • Another material removal technique involves well-known electropolishing processes. During an electropolishing process, both the material to be removed and a conductive electrode remain in an electropolishing solution. Typically, an anodic (positive) voltage is applied to the material to be removed with respect to the conductive electrode. With the applied voltage, the material is electrochemically dissolved and removed from the wafer surface.
  • In interconnect manufacturing, electropolishing process can be used to reduce the thickness of the overburden or excess copper layers deposited on the semiconductor substrates, as exemplified in FIG. 1. Copper 10 is electrodeposited on a dielectric layer 12 that is previously formed on the semiconductor substrate 14. Features 16 as well as the surface 20 of the dielectric layer 14 are filled with copper 10. Before the copper deposition, a barrier layer 22 such as Tantalum layer and a copper seed layer (not shown) are coated in the features and the surface of the dielectric layer 12. The conventional method for removal of the excess copper from the surface 20 is CMP. As mentioned above, electropolishing can also be used to reduce the thickness of this copper layer to an exemplary level indicated by dashed line 24, or even eliminate all copper from the surface as indicated by line 25. However, to be able to achieve these results without removing any copper from the features, the electropolishing process needs to be highly efficient and uniform. In cases where the thickness of copper on the wafer surface is not uniform but has a profile, the electropolishing technique should provide capability to tune the removal rate profile to match the initial copper thickness profile on the wafer.
  • SUMMARY
  • Present invention provides an electrochemical or electrochemical mechanical material removal system and an electrochemical or electrochemical mechanical material removal method employing a device made of a conductive material. The device is positioned between an electrode of the system and a conductive surface of a workpiece that is being electrochemically removed. The device includes openings or pores, which allow a process solution, such as an electroetching or electropolishing solution, to flow through the device.
  • The solution contacts the electrode, the device and the conductive surface when a material removal potential is applied between the conductive surface (anode) and the electrode (cathode).
  • In one aspect of the present invention, material removal rate is controlled by adjusting the distance between the conductive surface and a device surface that faces the conductive surface.
  • In another aspect of the present invention, material removal profile from the conductive surface can be controlled with the geometry or topography of the device surface.
  • A device surface, when placed substantially parallel to the conductive surface, the electropolishing of the conductive surface is efficient and produces a substantially uniform material removal rate.
  • A device surface with a center high and edge low profile causes a material removal rate which is higher near the center of the conductive surface.
  • A device surface with an edge high and center low profile causes a material removal rate which is lower near the center of the conductive surface.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic illustration of a substrate having an electroplated copper layer;
  • FIG. 2 is a schematic illustration of an embodiment of an electropolishing system of the present invention;
  • FIG. 3 is a graph shoving a conventional electropolishing removal profile and an electropolishing removal profile of the present invention;
  • FIG. 4 is a schematic illustration of another embodiment of an electropolishing system of the present invention;
  • FIG. 5A is a schematic illustration of an embodiment of a conductive element of the present invention;
  • FIG. 5B is a graph shoving an electropolishing removal profile obtained using the conductive element shown in FIG. 5A;
  • FIG. 6A is a schematic illustration of another embodiment of a conductive element of the present invention;
  • FIG. 6B is a graph shoving an electropolishing removal profile obtained using the conductive element shown in FIG. 6A;
  • FIG. 7A is a schematic plan view of an embodiment of a conductive element of the present invention;
  • FIG. 7B is a schematic side view of an embodiment of the conductive element of the present invention shown in FIG. 7A;
  • FIGS. 8A-8C are schematic illustrations of a conductive element with movable sections;
  • FIGS. 9A-9B are schematic illustrations of embodiments of various conductive elements; and
  • FIG. 10 is a schematic illustration of a switch system for electrochemically cleaning the conductive element at process intervals.
  • DETAILED DESCRIPTION
  • Present invention provides an electropolishing system and a method using a conductive member positioned between an electrode and a workpiece surface that is being electropolished. The conductive member may be a perforated or porous plate, which allows a process solution to flow through it. The electropolishing solution contacts the electrode, the conductive member and the workpiece surface while an electropolishing potential is applied between the workpiece surface (anode) and the electrode (cathode). Material removal rate may be controlled by adjusting the distance between the conductive member surface and the workpiece surface as well by the adjustment of the voltage applied between (or current passing through) the workpiece surface and the electrode. In this respect, as the conductive member surface gets closer to the workpiece surface, the material removal rate is increased. Further, material removal profile from the workpiece surface can be controlled with the geometry or topography of the conductive member surface that faces the workpiece surface. For example, if the conductive member surface is flat and parallel to the workpiece surface, the electropolishing of the workpiece surface produces a substantially uniform removal rate. If the conductive member surface has a center high and edge low profile, material removal rate at the center of the workpiece surface is higher than the edge of the workpiece. As a result, electropolishing process results in a center low profile for the removal rate. Similarly, if the conductive member has an edge high and center low profile, the material etching or polishing rate at the center of the workpiece surface will be lower than the edge of the workpiece. This, in turn, results in a removal rate profile, which is edge low. Here, the profile of the conductive member surface refers to three dimensional shape of the surface or topography of the surface.
  • FIG. 2 shows an exemplary electropolishing system 100 to perform process of the present invention. The system 100 comprises a carrier 102 to hold a workpiece 104 or a wafer, an electrode 106 placed across the wafer 104 and a conductive member 108 positioned between a front surface 110 of the wafer 104 and the electrode 106. The conductive member 108 may be a conductive perforated plate and, in this embodiment, is not connected to any power source. Since the described process is an electrochemical removal or electropolishing process, the electrode 106 becomes cathode of the system 100 while the front surface 110 of the wafer 104 becomes the anode. In other words, the front surface 110 may be defined as anodic compared to the cathode electrode 106. The conductive member 108, although not connected to any power source, is electrically more cathodic compared to the front surface 110 of the wafer and more anodic compared to the cathode electrode 106. Further, since the conductive member 108 is between the front surface 110 and the electrode 106, which is a cathode, its voltage is expected to be positive but lower than the front surface voltage of the wafer 104. The front surface 110 and the electrode 106 are connected to a power supply 112 through electrical contacts (not shown). The electrical contacts may be conductive brushes contacting the perimeter of the wafer 104 while the wafer is moved or rotated. Such electrical contacts are described in U.S. patent application Ser. No. 10/282,930 entitled Method and System to Provide Electrical Contacts for Electrotreating Processes filed Oct. 28, 2002, which is owned assignee of the present application. Alternately, other contacting methods well known in the art may be used. The wafer 104 may be a semiconductor wafer and the front surface 110 may include a previously deposited copper layer to be electropolished, such as exemplified in FIG. 1. The carrier 102 is able to rotate and move wafer 104 vertically and laterally during the process.
  • The conductive member 108 includes a first surface 114 and a second surface 116 and a plurality of openings 118 extending between the first and the second surfaces. The first surface 114 faces the front surface 110 of the wafer 104, and the second surface 116 is placed across the electrode 106. In this embodiment, the first surface 114 is flat and placed parallel to the front surface 110 to facilitate uniform electropolishing of the front surface. However, as will be described more fully below, the first surface 114 of the conductive member 108 may have different geometrical profiles to shape removal profile of the front surface 110 of the wafer 104. Preferably, a plurality of openings 118 extends between the first surface 114 and the second surface 116 of the conductive member 108. A process solution 120 such as an electropolishing solution flow through the openings 118.
  • Referring back to FIG. 2, the conductive member 108 divides system 100 into two sections, namely a cathodic section 122 and an anodic section 124. Openings 118 allow the electropolishing solution 120 to flow between the cathodic section 122 and the anodic section 124 of the system 100. In the cathodic section 122, the electropolishing solution 120 is in contact with the cathode electrode 106 and the conductive member 108, and in the anodic section 124, the solution 120 is in contact with the front surface 110 (conductive surface) of the wafer 104 and the conductive member 108. Although FIG. 2 exemplifies the cathode electrode 106, the conductive member 108 and the wafer 104 in a lateral configuration, they can be aligned vertically or in upside down geometry and this is within the scope of this invention.
  • The conductive member 108 is made of a conductive material, such as a metal or metal alloy, or coated with a conductive material. The conductive member 108 can also be a conductive porous material or a mesh, instead of having openings 118 which are well defined, as shown in FIG. 2. However, in any case the conductive member should allow solution flow between the anodic section and the cathodic section. The conductive member 108 is separated from the front surface of the wafer 104 by a distance d1 and from the electrode 106 by a distance d2. Preferably, the distance d1 is smaller than the distance d2. The distance between the front surface 110 of the wafer 104 and the electrode is d3. In one exemplary embodiment d2 may be larger than 50 millimeters (mm) and d1 is smaller than 5 mm.
  • In one exemplary electropolishing process of the present invention, the front surface of the wafer 104 is moved closer to the first surface 114 of the conductive member 108 while the electropolishing solution 120 is flowed through the conductive member 108. As the wafer 104 is rotated or moved, or rotated and moved in proximity of the first surface 114 of the conductive member, a potential difference is applied between the front surface and the electrode 106 to electropolish the copper of the front surface 110. In this example, the distance d1 is 2-4 mm. During electropolishing, the front surface 110 of the wafer 104 may get very close to the first surface of the conductive member 108 but it never touches the conductive member.
  • In an alternative embodiment, the front surface 110 of the wafer may be occasionally or continuously swept with a pad material (not shown) during the electrochemical removal process. The sweeping process may be used to planarize the front surface 110 as it is electropolished. An example of use of pad material during electrochemical mechanical processes can be found in U.S. application Ser. No. 09/607,567 entitled Method and Apparatus for Electrochemical Mechanical Deposition, filed Jun. 29, 2000, which is owned by the assignee of the present application and which is incorporated herein by reference. This process is sometimes referred to as electrochemical mechanical etching (ECME) or electrochemical mechanical polishing (ECMP). In one embodiment, the pad material may be mounted on the first surface 114 of the conductive member itself. The pad material may have openings to let the process solution flow through or it may be made of a porous pad material. The pad material may also be attached on the first surface 114 of the conductive member 108 as pad pieces or strips. It should be noted that in FIGS. 2 and 3 the electropolishing solution 120 is shown to flow from the cathode electrode 106 towards the front surface 110 of the wafer 104. This is the preferred process solution flow direction. However, the present invention can be also performed by reversing the direction of the process solution. Further, in one embodiment, the process solution does not flow but forms a process solution pool in which electropolishing is carried out. Furthermore, although not shown, the electropolishing solution 120 may be re-circulated after filtering and cleaning.
  • In FIG. 3, the curve 132 shows material removal profile across the diameter of the wafer 104 when the electropolishing process of the present embodiment is applied. Removal profile depicted in curve 132 shows a flat removal profile with less than 2% non-uniformity. As shown in FIG. 3 for comparison reasons, when the same electropolishing process is repeated after replacing the conductive member 108 with a non-conductive member or by taking it out of the process solution altogether, the removal profile depicted with curve 134 is non-uniform and consequently non-repeatable. It should be appreciated that when the electrochemical removal process is applied to a large numbers of wafers, copper removed from the wafer surface is mostly deposited on the electrode surface. However, this copper may be porous or powdery and as it deposits on the electrode it may change the shape of the electrode and its surface conductance. Consequently, in time, as more and more wafers are processed, electric field lines between the electrode and the substrate are expected to change. This causes changes in the material removal profiles. In other words, the removal profile may not be repeatable for processing large number of wafers. This is not acceptable in a semiconductor IC production environment. Presence of the conductive element, which is positioned very close to the front surface of the wafer, assures uniform copper removal rate irrespective of the number of wafers processed.
  • FIG. 4 shows another exemplary system to perform the electropolishing process of the present invention. In system 200, a conductive member 202 encloses a solution chamber 203 including a cathode electrode 204 in a process solution 205. The process solution 205 may be an electropolishing solution or electrolyte. It should be noted that the cathode electrode 204 does not have to be in the solution chamber 203. It may be placed at a different location as long as there is fluid communication between it and the solution chamber 203 through the process solution 205. A wafer carrier 206 holds a conductive surface 208 of a workpiece 209 or wafer close to an upper surface 210 of the conductive member 202. Process solution 205 is delivered into the solution chamber 203 through a delivery port 214 and flowed through openings 216 of the conductive member 202 towards the conductive surface 208 of the wafer 204. During the process, wafer 209 is rotated and/or laterally moved above the upper surface 210 of the conductive member 202 while a potential difference is applied between the conductive surface 208 and the cathode electrode 204 from a power source 218. In this embodiment, sidewalls 220 of the solution chamber 203 are made of a non-conductive, isolating material to prevent electrical shorting between the cathode electrode 204 and the conductive member 202. It should be noted that other components such as filters, bubble reduction means, shaping plates, etc., may be included in the solution chamber design of FIG. 4. For example, a filter element may be attached to a lower surface 222 of the conductive member 202 to reduce or eliminate particles that may come to the front surface 208 of the wafer 209. Another filter element may be placed over the cathode electrode 204 confining particles generated on the electrode during the process to the region close to the electrode.
  • As shown in FIGS. 5A and 6A, the conductive members can be shaped depending on desired removal profile of the conductive surface of the wafer. FIG. 5A shows a conductive member 300 with center high design with openings 302 extending between a first surface 304 and a second surface 306. The first surface 304 has a convex shape. The conductive surface 310 of the wafer 312 faces the first surface 304. For the purpose of clarity, in FIG. 5A, the center high shape of the first surface 304 is exaggerated. In practice, the height ‘h’ of the convex surface may be in the range of 0.5-3 mm or less. As shown in FIG. 5B with curve 315, electropolishing process with the conductive member 300 yields a center high material removal profile.
  • FIG. 6A shows another example of a conductive member 400 with edge high design with openings 402 extending between a first surface 404 and a second surface 406. The first surface 404 has a concave shape. The conductive surface 410 of the wafer 412 faces the first surface 404. For the purpose of clarity, in FIG. 6A, the center low shape of the first surface 404 is exaggerated. In practice, depth ‘d’ of the surface may be in the range of 0.5-3 mm or less. As shown in FIG. 6B with curve 415, electropolishing process with the conductive member 400 yields a center low and edge high material removal profile. The second surfaces 306, 406 are shown flat in FIGS. 5A and 6A. It should be understood that shapes of these surfaces may be different. What is most effective in determining removal profile is the shape of the first surfaces 304 and 404.
  • In another example, conductive member may have insulating or high resistivity portions juxtaposed with the conductive portions. Shape, geometry and the location of the insulating portions shape the removal profile. One example of a conductive member 500 having insulated regions 502, 504 and conductive region 505 is shown in FIGS. 7A-7B. The conductive member 500 has a first surface 506 and a second surface 508. Openings 510 extend between the first and the second surfaces. The insulated regions 502, 504 of the conductive member 500 may be made of an electrical insulation material or may just be an electrically insulating film or layer partially coated or attached on the first surface of the conductive member 500. Insulated regions 502, 504 as well as the conductive region 505 may not be co-planar but they may be formed as recesses or raised regions. For example, the insulated regions 502, 504 may form the recessed regions and the conductive region 505 may form the raised region. As a front surface 512 of a wafer 514 is electropolished, when a portion of the front surface 512 moves over the insulated regions 502, 504, that portion is electropolished in a reduced rate for that time duration. As shown in FIG. 7A in plan view and in FIG. 7B in cross section, in this embodiment, as the wafer 514 is rotated, edge region of the front surface 512 is partially exposed to the insulated regions 502, 504 and material removal from the edge region will be less than the center of the front surface 512 which is exposed to the conductive region 505 of the conductive member 500. This electropolishing process yields a center high removal profile similar to the one shown in FIG. 5B. During the electropolishing process, electrical contact to the front surface may be made along the edge of the wafer using conductive brush or other type contacts. Such contacts are described in the above mentioned U.S. application Ser. No. 10/282,930 which is incorporated herein by reference.
  • FIGS. 8A-8C exemplifies a conductive member 600 having movable sections 602, 604 and 606 and openings 608. By moving the sections 602, 604 and 606 up and down with respect to one another, various configurations of the conductive member 600 may be obtained. Such configurations can be used to obtain different material removal profiles that have been described above. For example, conductive member configuration shown in FIG. 8A can be used to obtain uniform material profiles. Conductive member configuration shown in FIG. 8B can be used to obtain center high-edge low material removal profile and the configuration in FIG. 8C can be used to obtain center low-edge high material removal profile.
  • Conductive members may have discontinuous surface profiles including raised and recessed portions. Raised or recessed portions may be aligned along certain profiles. FIG. 9A shows a conductive member 700 having raised portions 702 and recessed portions 704 formed along a primary surface 705 of the conductive member 700. Openings 706 may be formed through the raised portions 702 and recessed portions 704. In this embodiment, a plurality of raised portions 704 form a center high profile, which in turn enables center high material removal profile during the electropolishing. The surface to be electropolished must face the raised and recessed portions, or primary surface 705 of the conductive member 700, during the process. FIG. 9B shows another conductive member 800 having raised portions 802 and recessed portions 804 formed along a primary surface 805 of the conductive member. Openings 806 are formed through the portions 802 and 804. In this embodiment, raised portions 804 have the same height, which enables uniform material removal profile during the electropolishing. The surface to be electropolished must face the raised and recessed portions, or primary surface of the conductive member, during the process. The recessed portions may be coated with an insulating material leaving only the raised portions conductive and active during the process.
  • FIG. 10 illustrates a method for cleaning a conductive member 900. As described above, after a certain time of use or process cycles, a conductive material accumulation may occur on the conductive member 900 since the conductive member is more cathodic compared to a conductive surface 902 of a wafer 904. Therefore, conductive member needs to be cleaned with certain intervals. One possible way of cleaning may be done by anodically polarizing the conductive member 900 and dissolving the accumulated material at certain intervals. FIG. 10 shows one embodiment of the cleaning process. In this embodiment, when a switch 905 is connected position “A”, power source 906 applies a potential difference between the conductive surface 902 and the cathode electrode 907. In presence of electropolishing solution 908, this connection results in electropolishing of the conductive surface 902. Most of the removed material deposits on the cathode electrode 907. However, depending on the distance between the surface 902 and the top surface of the conductive member 900, some deposition can also take place on the conductive member 900. This deposited conductive material affects the electropolishing uniformity provided by the conductive member 900 and needs to be cleaned at intervals. Typically, larger distances would result in more deposition on the conductive member. For cleaning the conductive member 900, the switch 905 is turned to position “B” and a potential difference, which may or may not be the same as the one applied when switch 905 was in “A” position, is applied between the conductive member 900 and the electrode 907 making the conductive member an anode. This action cleans the accumulated material on the conductive member 900. After the cleaning, electropolishing process may continue on other wafers by moving the switch 905 to position “A”.
  • Although the present invention has been particularly described with reference to the preferred embodiments, it should be readily apparent to those of ordinary skill in the art that changes and modifications in the form and details may be made without departing from the spirit and scope of the invention.

Claims (29)

1. An apparatus for electropolishing a conductive layer on a workpiece using a process solution, comprising:
a carrier to hold the workpiece;
an electrode; and
a conductive element placed between the electrode and the conductive layer, the conductive element having openings permitting process solution to flow through the conductive element and the conductive element having a surface placed across from the conductive layer, the surface of the conductive element including a surface profile to control the material removal profile of the conductive layer.
2. The apparatus of claim 1, wherein the surface profile is a convex surface profile.
3. The apparatus of claim 1, wherein the surface profile is a concave surface profile.
4. The apparatus of claim 1, wherein the surface profile is flat.
5. The apparatus of claim 1 further comprising a power supply to apply a potential difference between the electrode and the conductive surface.
6. The apparatus of claim 1, wherein the surface of the conductive element includes a pad to polish the conductive layer.
7. The apparatus of claim 1, wherein the carrier is configured to vary the distance between the conductive layer and the surface of the conductive layer.
8. The apparatus of claim 5, wherein the power supply is configured to vary the potential difference between the conductive layer and the electrode.
9. The apparatus of claim 5, wherein the power supply is configured to apply a potential difference between the conductive element and the electrode to electrochemically clean the conductive element at process intervals.
10. The apparatus of claim 1, wherein the conductive layer is copper.
11. A method of electropolishing a conductive layer on a wafer using a process solution and an electrode, the method comprising:
placing a surface of a conductive element across from the conductive layer, the surface of the conductive element having a first surface profile; and
applying a potential difference between the conductive layer and the electrode; and
forming a first conductive layer profile of the conductive layer.
12. The method of claim 11, wherein the step of forming comprises electropolishing the conductive layer according to a first material removal profile.
13. The method of claim 11, wherein the step of placing comprises placing a surface of another conductive element, the surface having a second surface profile.
14. The method of claim 13 further comprising:
applying a potential difference between the conductive layer and the electrode; and
forming a second conductive layer profile of the conductive layer.
15. The method of claim 14, wherein the step of forming comprises electropolishing the conductive layer according to a second material removal profile.
16. The method of claim 13 further comprising varying the potential difference during the step of applying to vary material removal rate from the conductive layer.
17. An apparatus for electropolishing a conductive layer on a workpiece using a process solution, comprising:
a carrier to hold the workpiece;
an electrode; and
a conductive element placed between the electrode and the conductive layer, the conductive element having openings permitting process solution to flow through the conductive element and the conductive element having a surface placed across from the conductive layer; and
wherein the conductive element is comprised of movable sections to alter the profile of the surface by moving the movable sections to control the material removal profile of the conductive layer.
18. The apparatus of claim 17 further comprising a power supply to apply a potential difference between the electrode and the conductive surface.
19. The apparatus of claim 17, wherein the surface of the conductive element includes a pad to polish the conductive layer.
20. The apparatus of claim 17, wherein the carrier is configured to vary the distance between the conductive layer and the surface of the conductive element.
21. The apparatus of claim 18, wherein the power supply is configured to vary the potential difference between the conductive layer and the electrode.
22. The apparatus of claim 18, wherein the power supply is configured to apply a potential difference between the conductive element and the electrode to electrochemically clean the conductive element at process intervals.
23. The apparatus of claim 17, wherein the conductive layer is copper.
24. A method of electropolishing a conductive layer on a wafer using a process solution and an electrode, the method comprising:
placing a surface of a conductive member across from the conductive layer, the conductive element having openings permitting process solution to flow through the conductive element and the conductive element comprising movable sections;
changing the profile of the surface of the conductive member to a predetermined profile by moving the movable sections;
applying a potential difference between the conductive layer and the electrode; and
forming a predetermined conductive layer profile of the conductive layer.
25. The method of claim 24, wherein the step of forming comprises electropolishing the conductive layer according to a predetermined material removal profile.
26. The method of claim 24, wherein the step of changing comprises changing the profile of the surface of the conductive member to another predetermined profile by moving the movable sections.
27. The method of claim 26 further comprising:
applying a potential difference between the conductive layer and the electrode; and
forming another predetermined conductive layer profile of the conductive.
28. The method of claim 24, wherein the step of forming comprises electropolishing the conductive layer according to another predetermined material removal profile.
29. The method of claim 24 further comprising varying the potential difference during the step of applying to vary material removal rate from the conductive layer.
US10/902,241 2000-02-23 2004-07-29 Method and system for controlled material removal by electrochemical polishing Abandoned US20090020437A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/902,241 US20090020437A1 (en) 2000-02-23 2004-07-29 Method and system for controlled material removal by electrochemical polishing

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US09/511,278 US6413388B1 (en) 2000-02-23 2000-02-23 Pad designs and structures for a versatile materials processing apparatus
US10/152,793 US7378004B2 (en) 2000-02-23 2002-05-23 Pad designs and structures for a versatile materials processing apparatus
US10/302,755 US7204917B2 (en) 1998-12-01 2002-11-21 Workpiece surface influencing device designs for electrochemical mechanical processing and method of using the same
US49147003P 2003-07-30 2003-07-30
US10/902,241 US20090020437A1 (en) 2000-02-23 2004-07-29 Method and system for controlled material removal by electrochemical polishing

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/302,755 Continuation-In-Part US7204917B2 (en) 1998-12-01 2002-11-21 Workpiece surface influencing device designs for electrochemical mechanical processing and method of using the same

Publications (1)

Publication Number Publication Date
US20090020437A1 true US20090020437A1 (en) 2009-01-22

Family

ID=40263971

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/902,241 Abandoned US20090020437A1 (en) 2000-02-23 2004-07-29 Method and system for controlled material removal by electrochemical polishing

Country Status (1)

Country Link
US (1) US20090020437A1 (en)

Citations (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US1739657A (en) * 1928-01-16 1929-12-17 Reuben B Shemitz Electroplating device
US1758682A (en) * 1925-07-13 1930-05-13 Batenburg Pad for electroplating devices
US2540602A (en) * 1946-07-03 1951-02-06 Lockheed Aircraft Corp Method and apparatus for the surface treatment of metals
US3328273A (en) * 1966-08-15 1967-06-27 Udylite Corp Electro-deposition of copper from acidic baths
US3395092A (en) * 1965-05-24 1968-07-30 Ribes Vincent Dressing apparatus for diamond wheels
US3436259A (en) * 1966-05-12 1969-04-01 Ibm Method for plating and polishing a silicon planar surface
US3890746A (en) * 1973-09-07 1975-06-24 Kyuji Saegusa Flapper wheel
US3922207A (en) * 1974-05-31 1975-11-25 United Technologies Corp Method for plating articles with particles in a metal matrix
US3959089A (en) * 1972-07-31 1976-05-25 Watts John Dawson Surface finishing and plating method
US4140598A (en) * 1976-06-03 1979-02-20 Hitachi Shipbuilding & Engineering Co., Ltd. Mirror finishing
US4430173A (en) * 1981-07-24 1984-02-07 Rhone-Poulenc Specialties Chimiques Additive composition, bath and process for acid copper electroplating
US4610772A (en) * 1985-07-22 1986-09-09 The Carolinch Company Electrolytic plating apparatus
US4948474A (en) * 1987-09-18 1990-08-14 Pennsylvania Research Corporation Copper electroplating solutions and methods
US4954142A (en) * 1989-03-07 1990-09-04 International Business Machines Corporation Method of chemical-mechanical polishing an electronic component substrate and polishing slurry therefor
US4975159A (en) * 1988-10-24 1990-12-04 Schering Aktiengesellschaft Aqueous acidic bath for electrochemical deposition of a shiny and tear-free copper coating and method of using same
US5024735A (en) * 1989-02-15 1991-06-18 Kadija Igor V Method and apparatus for manufacturing interconnects with fine lines and spacing
US5084071A (en) * 1989-03-07 1992-01-28 International Business Machines Corporation Method of chemical-mechanical polishing an electronic component substrate and polishing slurry therefor
US5171412A (en) * 1991-08-23 1992-12-15 Applied Materials, Inc. Material deposition method for integrated circuit manufacturing
US5256565A (en) * 1989-05-08 1993-10-26 The United States Of America As Represented By The United States Department Of Energy Electrochemical planarization
US5272111A (en) * 1991-02-05 1993-12-21 Mitsubishi Denki Kabushiki Kaisha Method for manufacturing semiconductor device contact
US5354490A (en) * 1992-06-04 1994-10-11 Micron Technology, Inc. Slurries for chemical mechanically polishing copper containing metal layers
US5429733A (en) * 1992-05-21 1995-07-04 Electroplating Engineers Of Japan, Ltd. Plating device for wafer
US5516412A (en) * 1995-05-16 1996-05-14 International Business Machines Corporation Vertical paddle plating cell
US5543032A (en) * 1994-11-30 1996-08-06 Ibm Corporation Electroetching method and apparatus
US5558568A (en) * 1994-10-11 1996-09-24 Ontrak Systems, Inc. Wafer polishing machine with fluid bearings
US5650039A (en) * 1994-03-02 1997-07-22 Applied Materials, Inc. Chemical mechanical polishing apparatus with improved slurry distribution
US5681215A (en) * 1995-10-27 1997-10-28 Applied Materials, Inc. Carrier head design for a chemical mechanical polishing apparatus
US5692947A (en) * 1994-08-09 1997-12-02 Ontrak Systems, Inc. Linear polisher and method for semiconductor wafer planarization
US5755859A (en) * 1995-08-24 1998-05-26 International Business Machines Corporation Cobalt-tin alloys and their applications for devices, chip interconnections and packaging
US5762544A (en) * 1995-10-27 1998-06-09 Applied Materials, Inc. Carrier head design for a chemical mechanical polishing apparatus
US5770095A (en) * 1994-07-12 1998-06-23 Kabushiki Kaisha Toshiba Polishing agent and polishing method using the same
US5773364A (en) * 1996-10-21 1998-06-30 Motorola, Inc. Method for using ammonium salt slurries for chemical mechanical polishing (CMP)
US5793272A (en) * 1996-08-23 1998-08-11 International Business Machines Corporation Integrated circuit toroidal inductor
US5795215A (en) * 1995-06-09 1998-08-18 Applied Materials, Inc. Method and apparatus for using a retaining ring to control the edge effect
US5807165A (en) * 1997-03-26 1998-09-15 International Business Machines Corporation Method of electrochemical mechanical planarization
US5833820A (en) * 1997-06-19 1998-11-10 Advanced Micro Devices, Inc. Electroplating apparatus
US5840629A (en) * 1995-12-14 1998-11-24 Sematech, Inc. Copper chemical mechanical polishing slurry utilizing a chromate oxidant
US5858813A (en) * 1996-05-10 1999-01-12 Cabot Corporation Chemical mechanical polishing slurry for metal layers and films
US5863412A (en) * 1995-10-17 1999-01-26 Canon Kabushiki Kaisha Etching method and process for producing a semiconductor element using said etching method
US5897375A (en) * 1997-10-20 1999-04-27 Motorola, Inc. Chemical mechanical polishing (CMP) slurry for copper and method of use in integrated circuit manufacture
US5911619A (en) * 1997-03-26 1999-06-15 International Business Machines Corporation Apparatus for electrochemical mechanical planarization
US5922091A (en) * 1997-05-16 1999-07-13 National Science Council Of Republic Of China Chemical mechanical polishing slurry for metallic thin film
US5930669A (en) * 1997-04-03 1999-07-27 International Business Machines Corporation Continuous highly conductive metal wiring structures and method for fabricating the same
US5933753A (en) * 1996-12-16 1999-08-03 International Business Machines Corporation Open-bottomed via liner structure and method for fabricating same
US5954997A (en) * 1996-12-09 1999-09-21 Cabot Corporation Chemical mechanical polishing slurry useful for copper substrates
US5985123A (en) * 1997-07-09 1999-11-16 Koon; Kam Kwan Continuous vertical plating system and method of plating
US6004880A (en) * 1998-02-20 1999-12-21 Lsi Logic Corporation Method of single step damascene process for deposition and global planarization
US6027631A (en) * 1997-11-13 2000-02-22 Novellus Systems, Inc. Electroplating system with shields for varying thickness profile of deposited layer
US6063506A (en) * 1995-06-27 2000-05-16 International Business Machines Corporation Copper alloys for chip and package interconnections
US6066030A (en) * 1999-03-04 2000-05-23 International Business Machines Corporation Electroetch and chemical mechanical polishing equipment
US6071388A (en) * 1998-05-29 2000-06-06 International Business Machines Corporation Electroplating workpiece fixture having liquid gap spacer
US6074544A (en) * 1998-07-22 2000-06-13 Novellus Systems, Inc. Method of electroplating semiconductor wafer using variable currents and mass transfer to obtain uniform plated layer
US6103085A (en) * 1998-12-04 2000-08-15 Advanced Micro Devices, Inc. Electroplating uniformity by diffuser design
US6110011A (en) * 1997-11-10 2000-08-29 Applied Materials, Inc. Integrated electrodeposition and chemical-mechanical polishing tool
US6132587A (en) * 1998-10-19 2000-10-17 Jorne; Jacob Uniform electroplating of wafers
US6136163A (en) * 1999-03-05 2000-10-24 Applied Materials, Inc. Apparatus for electro-chemical deposition with thermal anneal chamber
US6176992B1 (en) * 1998-11-03 2001-01-23 Nutool, Inc. Method and apparatus for electro-chemical mechanical deposition
US6217426B1 (en) * 1999-04-06 2001-04-17 Applied Materials, Inc. CMP polishing pad
US6242349B1 (en) * 1998-12-09 2001-06-05 Advanced Micro Devices, Inc. Method of forming copper/copper alloy interconnection with reduced electromigration
US6409904B1 (en) * 1998-12-01 2002-06-25 Nutool, Inc. Method and apparatus for depositing and controlling the texture of a thin film
US20030079995A1 (en) * 2000-03-27 2003-05-01 Novellus Systems, Inc. Dynamically variable field shaping element
US6974525B2 (en) * 2001-02-12 2005-12-13 Speedfam-Ipec Corporation Method and apparatus for electrochemical planarization of a workpiece

Patent Citations (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US1758682A (en) * 1925-07-13 1930-05-13 Batenburg Pad for electroplating devices
US1739657A (en) * 1928-01-16 1929-12-17 Reuben B Shemitz Electroplating device
US2540602A (en) * 1946-07-03 1951-02-06 Lockheed Aircraft Corp Method and apparatus for the surface treatment of metals
US3395092A (en) * 1965-05-24 1968-07-30 Ribes Vincent Dressing apparatus for diamond wheels
US3436259A (en) * 1966-05-12 1969-04-01 Ibm Method for plating and polishing a silicon planar surface
US3328273A (en) * 1966-08-15 1967-06-27 Udylite Corp Electro-deposition of copper from acidic baths
US3959089A (en) * 1972-07-31 1976-05-25 Watts John Dawson Surface finishing and plating method
US3890746A (en) * 1973-09-07 1975-06-24 Kyuji Saegusa Flapper wheel
US3922207A (en) * 1974-05-31 1975-11-25 United Technologies Corp Method for plating articles with particles in a metal matrix
US4140598A (en) * 1976-06-03 1979-02-20 Hitachi Shipbuilding & Engineering Co., Ltd. Mirror finishing
US4430173A (en) * 1981-07-24 1984-02-07 Rhone-Poulenc Specialties Chimiques Additive composition, bath and process for acid copper electroplating
US4610772A (en) * 1985-07-22 1986-09-09 The Carolinch Company Electrolytic plating apparatus
US4948474A (en) * 1987-09-18 1990-08-14 Pennsylvania Research Corporation Copper electroplating solutions and methods
US4975159A (en) * 1988-10-24 1990-12-04 Schering Aktiengesellschaft Aqueous acidic bath for electrochemical deposition of a shiny and tear-free copper coating and method of using same
US5024735A (en) * 1989-02-15 1991-06-18 Kadija Igor V Method and apparatus for manufacturing interconnects with fine lines and spacing
US5084071A (en) * 1989-03-07 1992-01-28 International Business Machines Corporation Method of chemical-mechanical polishing an electronic component substrate and polishing slurry therefor
US4954142A (en) * 1989-03-07 1990-09-04 International Business Machines Corporation Method of chemical-mechanical polishing an electronic component substrate and polishing slurry therefor
US5256565A (en) * 1989-05-08 1993-10-26 The United States Of America As Represented By The United States Department Of Energy Electrochemical planarization
US5272111A (en) * 1991-02-05 1993-12-21 Mitsubishi Denki Kabushiki Kaisha Method for manufacturing semiconductor device contact
US5171412A (en) * 1991-08-23 1992-12-15 Applied Materials, Inc. Material deposition method for integrated circuit manufacturing
US5429733A (en) * 1992-05-21 1995-07-04 Electroplating Engineers Of Japan, Ltd. Plating device for wafer
US5354490A (en) * 1992-06-04 1994-10-11 Micron Technology, Inc. Slurries for chemical mechanically polishing copper containing metal layers
US5650039A (en) * 1994-03-02 1997-07-22 Applied Materials, Inc. Chemical mechanical polishing apparatus with improved slurry distribution
US5770095A (en) * 1994-07-12 1998-06-23 Kabushiki Kaisha Toshiba Polishing agent and polishing method using the same
US5692947A (en) * 1994-08-09 1997-12-02 Ontrak Systems, Inc. Linear polisher and method for semiconductor wafer planarization
US5558568A (en) * 1994-10-11 1996-09-24 Ontrak Systems, Inc. Wafer polishing machine with fluid bearings
US5543032A (en) * 1994-11-30 1996-08-06 Ibm Corporation Electroetching method and apparatus
US5516412A (en) * 1995-05-16 1996-05-14 International Business Machines Corporation Vertical paddle plating cell
US5795215A (en) * 1995-06-09 1998-08-18 Applied Materials, Inc. Method and apparatus for using a retaining ring to control the edge effect
US6063506A (en) * 1995-06-27 2000-05-16 International Business Machines Corporation Copper alloys for chip and package interconnections
US5755859A (en) * 1995-08-24 1998-05-26 International Business Machines Corporation Cobalt-tin alloys and their applications for devices, chip interconnections and packaging
US5863412A (en) * 1995-10-17 1999-01-26 Canon Kabushiki Kaisha Etching method and process for producing a semiconductor element using said etching method
US5762544A (en) * 1995-10-27 1998-06-09 Applied Materials, Inc. Carrier head design for a chemical mechanical polishing apparatus
US5681215A (en) * 1995-10-27 1997-10-28 Applied Materials, Inc. Carrier head design for a chemical mechanical polishing apparatus
US5840629A (en) * 1995-12-14 1998-11-24 Sematech, Inc. Copper chemical mechanical polishing slurry utilizing a chromate oxidant
US5858813A (en) * 1996-05-10 1999-01-12 Cabot Corporation Chemical mechanical polishing slurry for metal layers and films
US5884990A (en) * 1996-08-23 1999-03-23 International Business Machines Corporation Integrated circuit inductor
US5793272A (en) * 1996-08-23 1998-08-11 International Business Machines Corporation Integrated circuit toroidal inductor
US5773364A (en) * 1996-10-21 1998-06-30 Motorola, Inc. Method for using ammonium salt slurries for chemical mechanical polishing (CMP)
US5954997A (en) * 1996-12-09 1999-09-21 Cabot Corporation Chemical mechanical polishing slurry useful for copper substrates
US5933753A (en) * 1996-12-16 1999-08-03 International Business Machines Corporation Open-bottomed via liner structure and method for fabricating same
US5807165A (en) * 1997-03-26 1998-09-15 International Business Machines Corporation Method of electrochemical mechanical planarization
US5911619A (en) * 1997-03-26 1999-06-15 International Business Machines Corporation Apparatus for electrochemical mechanical planarization
US5930669A (en) * 1997-04-03 1999-07-27 International Business Machines Corporation Continuous highly conductive metal wiring structures and method for fabricating the same
US5922091A (en) * 1997-05-16 1999-07-13 National Science Council Of Republic Of China Chemical mechanical polishing slurry for metallic thin film
US5833820A (en) * 1997-06-19 1998-11-10 Advanced Micro Devices, Inc. Electroplating apparatus
US5985123A (en) * 1997-07-09 1999-11-16 Koon; Kam Kwan Continuous vertical plating system and method of plating
US5897375A (en) * 1997-10-20 1999-04-27 Motorola, Inc. Chemical mechanical polishing (CMP) slurry for copper and method of use in integrated circuit manufacture
US6110011A (en) * 1997-11-10 2000-08-29 Applied Materials, Inc. Integrated electrodeposition and chemical-mechanical polishing tool
US6027631A (en) * 1997-11-13 2000-02-22 Novellus Systems, Inc. Electroplating system with shields for varying thickness profile of deposited layer
US6004880A (en) * 1998-02-20 1999-12-21 Lsi Logic Corporation Method of single step damascene process for deposition and global planarization
US6071388A (en) * 1998-05-29 2000-06-06 International Business Machines Corporation Electroplating workpiece fixture having liquid gap spacer
US6074544A (en) * 1998-07-22 2000-06-13 Novellus Systems, Inc. Method of electroplating semiconductor wafer using variable currents and mass transfer to obtain uniform plated layer
US6132587A (en) * 1998-10-19 2000-10-17 Jorne; Jacob Uniform electroplating of wafers
US6176992B1 (en) * 1998-11-03 2001-01-23 Nutool, Inc. Method and apparatus for electro-chemical mechanical deposition
US6409904B1 (en) * 1998-12-01 2002-06-25 Nutool, Inc. Method and apparatus for depositing and controlling the texture of a thin film
US6103085A (en) * 1998-12-04 2000-08-15 Advanced Micro Devices, Inc. Electroplating uniformity by diffuser design
US6242349B1 (en) * 1998-12-09 2001-06-05 Advanced Micro Devices, Inc. Method of forming copper/copper alloy interconnection with reduced electromigration
US6066030A (en) * 1999-03-04 2000-05-23 International Business Machines Corporation Electroetch and chemical mechanical polishing equipment
US6136163A (en) * 1999-03-05 2000-10-24 Applied Materials, Inc. Apparatus for electro-chemical deposition with thermal anneal chamber
US6217426B1 (en) * 1999-04-06 2001-04-17 Applied Materials, Inc. CMP polishing pad
US20030079995A1 (en) * 2000-03-27 2003-05-01 Novellus Systems, Inc. Dynamically variable field shaping element
US6974525B2 (en) * 2001-02-12 2005-12-13 Speedfam-Ipec Corporation Method and apparatus for electrochemical planarization of a workpiece

Similar Documents

Publication Publication Date Title
US7578923B2 (en) Electropolishing system and process
US6402925B2 (en) Method and apparatus for electrochemical mechanical deposition
US6946066B2 (en) Multi step electrodeposition process for reducing defects and minimizing film thickness
JP4034655B2 (en) Method and apparatus for electrodepositing a uniform thin film onto a substrate with minimal edge exclusion
US7341649B2 (en) Apparatus for electroprocessing a workpiece surface
US6852630B2 (en) Electroetching process and system
US7238092B2 (en) Low-force electrochemical mechanical processing method and apparatus
US20050173260A1 (en) System for electrochemical mechanical polishing
US20040231994A1 (en) Method and apparatus for controlling thickness uniformity of electroplated layers
US6773570B2 (en) Integrated plating and planarization process and apparatus therefor
US7427337B2 (en) System for electropolishing and electrochemical mechanical polishing
US7648622B2 (en) System and method for electrochemical mechanical polishing
US7550070B2 (en) Electrode and pad assembly for processing conductive layers
KR20030093294A (en) Method and apparatus for avoiding particle accumulation during an electrochemical process
US7204743B2 (en) Integrated circuit interconnect fabrication systems
US20020121445A1 (en) Mask plate design
US20090020437A1 (en) Method and system for controlled material removal by electrochemical polishing
US20060131177A1 (en) Means to eliminate bubble entrapment during electrochemical processing of workpiece surface
US6821409B2 (en) Electroetching methods and systems using chemical and mechanical influence
US20050112868A1 (en) Method and apparatus for localized material removal by electrochemical polishing

Legal Events

Date Code Title Description
AS Assignment

Owner name: ASM NUTOOL, INC., CALIFORNIA

Free format text: CHANGE OF NAME;ASSIGNOR:NUTOOL, INC.;REEL/FRAME:015723/0066

Effective date: 20040729

AS Assignment

Owner name: ASM NUTOOL, INC., ARIZONA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BASOL, BULENT M.;UZOH, CYPRIAN E.;GUO, GEORGE XINSHENG;REEL/FRAME:018430/0888;SIGNING DATES FROM 20060905 TO 20060914

AS Assignment

Owner name: NOVELLUS SYSTEMS, INC.,CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ASM NUTOOL, INC.;REEL/FRAME:019000/0080

Effective date: 20061204

Owner name: NOVELLUS SYSTEMS, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ASM NUTOOL, INC.;REEL/FRAME:019000/0080

Effective date: 20061204

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION