US20080226223A1 - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
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- US20080226223A1 US20080226223A1 US12/123,531 US12353108A US2008226223A1 US 20080226223 A1 US20080226223 A1 US 20080226223A1 US 12353108 A US12353108 A US 12353108A US 2008226223 A1 US2008226223 A1 US 2008226223A1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y20/00—Nanooptics, e.g. quantum optics or photonic crystals
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/12004—Combinations of two or more optical elements
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/122—Basic optical elements, e.g. light-guiding paths
- G02B6/1225—Basic optical elements, e.g. light-guiding paths comprising photonic band-gap structures or photonic lattices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
- H01S5/042—Electrical excitation ; Circuits therefor
- H01S5/0425—Electrodes, e.g. characterised by the structure
- H01S5/04252—Electrodes, e.g. characterised by the structure characterised by the material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
- H01S5/042—Electrical excitation ; Circuits therefor
- H01S5/0425—Electrodes, e.g. characterised by the structure
- H01S5/04256—Electrodes, e.g. characterised by the structure characterised by the configuration
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/015—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements with at least one potential jump barrier, e.g. PN, PIN junction
- G02F1/025—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements with at least one potential jump barrier, e.g. PN, PIN junction in an optical waveguide structure
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2202/00—Materials and properties
- G02F2202/32—Photonic crystals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0083—Periodic patterns for optical field-shaping in or on the semiconductor body or semiconductor body package, e.g. photonic bandgap structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
- H01S5/042—Electrical excitation ; Circuits therefor
- H01S5/0421—Electrical excitation ; Circuits therefor characterised by the semiconducting contacting layers
- H01S5/0422—Electrical excitation ; Circuits therefor characterised by the semiconducting contacting layers with n- and p-contacts on the same side of the active layer
- H01S5/0424—Electrical excitation ; Circuits therefor characterised by the semiconducting contacting layers with n- and p-contacts on the same side of the active layer lateral current injection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
- H01S5/042—Electrical excitation ; Circuits therefor
- H01S5/0425—Electrodes, e.g. characterised by the structure
- H01S5/04256—Electrodes, e.g. characterised by the structure characterised by the configuration
- H01S5/04257—Electrodes, e.g. characterised by the structure characterised by the configuration having positive and negative electrodes on the same side of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/1082—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region with a special facet structure, e.g. structured, non planar, oblique
- H01S5/1085—Oblique facets
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/11—Comprising a photonic bandgap structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/2004—Confining in the direction perpendicular to the layer structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/305—Structure or shape of the active region; Materials used for the active region characterised by the doping materials used in the laser structure
- H01S5/3054—Structure or shape of the active region; Materials used for the active region characterised by the doping materials used in the laser structure p-doping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
Abstract
A semiconductor device has a two-dimensional slab photonic crystal structure in which a substrate supports a sheet-like slab layer including, sequentially stacked, a lower cladding layer, an active layer, and an upper cladding layer. A periodic refractive index profile structure, in surfaces of the stacked layers, introduces a linear defect region that serves as a waveguide. A p-type region and an n-type region in the slab layer define a pn junction surface at a predetermined angle with respect to the surfaces of the stacked layers in the slab layer.
Description
- 1) Field of the Invention
- The present invention relates to a semiconductor device that is an optical device used for optical communication and optical information processing and in which an optical control function has been improved by pumping a two-dimensional slab photonic crystal and driving the two-dimensional slab photonic crystal at a current and a method of manufacturing the semiconductor device.
- 2) Description of the Related Art
- An active operation of a conventional optical active device that uses a two-dimensional slab photonic crystal including an active layer is realized by optical pumping (see, for example, “Room Temperature Optical Pumping/Oscillation by 2D Slab Photonic Crystal Waveguide Laser”, Atsushi SUGITATE et al, Proceedings of the Electronics Society Conference, the Institute of Electronics, Information, and Communication Engineers, 2002, p. 329)). This literature discloses that, in the two-dimensional slab photonic crystal in which a hole pattern of a two-dimensional triangular lattice is formed in a layer structure, in which the active layer of a multiple quantum well structure made of InGaAsP is put between air cladding layers, and in which a linear defect is introduced into the hole pattern, if a pumping laser light is irradiated from an upper portion of a waveguide constituted by the linear defect, lasing occurs from an edge of the waveguide.
- The conventional optical active device has, as disclosed in the above-mentioned literature, following disadvantage. Since electrode formation means is not established, the crystal cannot be pumped by current injection. As a result, the optical active device can operate as an active optical device such as a laser or a modulator only by optical pumping.
- It is an object of the present invention to solve at least the problems in the conventional technology.
- A semiconductor device according to an aspect of the present invention includes any one of a two-dimensional slab photonic crystal structure in which a substrate supports a sheet-like slab layer that is formed by sequentially stacking a lower cladding layer, an active layer, and an upper cladding layer and that has a periodic refractive index profile structure formed in surfaces of the stacked layers, the periodic refractive index profile structure introducing a linear defect region serving as a waveguide, a two-dimensional slab photonic crystal structure in which the sheet-like slab layer is stacked on and held by a dielectric layer, and a two-dimensional slab photonic crystal structure in which the sheet-like slab layer having the periodic refractive index profile structure is stacked on and held by a solid semiconductor layer. A a p-type region and an n-type region are formed in the slab layer so that a pn junction surface is formed at a predetermined angle with respect to the surfaces of the stacked layers in the slab layer.
- A method of manufacturing a semiconductor device according to another aspect of the present invention includes forming a slab layer on a substrate by sequentially stacking a lower cladding layer, an active layer, and an upper cladding layer; forming a pn junction surface at a predetermined angle with respect to surfaces of the stacked layers in the slab layer; forming an ohmic contact layer for attaching an electrode, on the upper cladding layer; forming a periodic air hole structure introducing a linear defect region serving as a waveguide, on the slab layer and the ohmic contact layer; forming the electrode on the ohmic contact layer in each of a p-type region and an n-type region in the slab layer; removing the ohmic contact layer; and undercutting an interior of the substrate to be hollow so as to form the sheet-like slab layer.
- A method of manufacturing a semiconductor device according to still another aspect of the present invention includes forming a slab layer on a substrate by sequentially stacking a lower cladding layer, an active layer, and an upper cladding layer; forming a pn junction surface at a predetermined angle with respect to surfaces of the stacked layers in the slab layer; forming an ohmic contact layer for attaching an electrode, on the upper cladding layer; forming a periodic air hole structure introducing a linear defect region serving as a waveguide, on the slab layer and the ohmic contact layer; forming the electrode on the ohmic contact layer in each of a p-type region and an n-type region in the slab layer; removing the ohmic contact layer; and oxidizing an Al-containing layer in a lower portion or in both an upper portion and a lower portion of the slab layer into a dielectric layer, so as to form a semiconductor slab layer.
- A method of manufacturing a semiconductor device according to still another aspect of the present invention includes forming a slab layer on a first substrate by sequentially stacking a lower cladding layer, an active layer, and an upper cladding layer; forming a pn junction surface at a predetermined angle with respect to surfaces of the stacked layers in the slab layer; forming a periodic air hole structure introducing a linear defect region serving as a waveguide, on the slab layer and the ohmic contact layer; removing a lower portion or an upper portion and a lower portion of the slab layer, so as to form a semiconductor slab layer; fusion-connecting a second substrate prepared separately from the first substrate, to the first substrate; and forming the electrode to be in contact with the ohmic contact layer in a p-type region and an n-type region on the second substrate that has been fusion-connected to the first substrate.
- A method of manufacturing a semiconductor device according to still another aspect of the present invention includes forming a slab layer on a substrate by sequentially stacking a lower cladding layer, an active layer, and an upper cladding layer; forming an ohmic contact layer for attaching an electrode, on the upper cladding layer; forming a periodic air hole structure introducing a linear defect region serving as a waveguide, on the slab layer and the ohmic contact layer; forming a pn junction surface at a predetermined angle with respect to surfaces of the stacked layers in the slab layer; forming the electrode on the ohmic contact layer in each of a p-type region and an n-type region in the slab layer; removing the ohmic contact layer; and undercutting an interior of the substrate to be hollow, so as to form the sheet-like slab layer.
- The other objects, features, and advantages of the present invention are specifically set forth in or will become apparent from the following detailed description of the invention when read in conjunction with the accompanying drawings.
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FIG. 1A is a perspective view of a semiconductor device according to a first embodiment of the present invention; -
FIG. 1B toFIG. 1D are cross-sectional views, taken along a line A-A shown inFIG. 1A , of the semiconductor device according to the first embodiment; -
FIG. 2A toFIG. 2C typically illustrate forms of a pn junction in a slab layer; -
FIG. 3A toFIG. 3G are cross-sectional side views which typically illustrate a method of manufacturing the semiconductor device; -
FIG. 4A andFIG. 4B are cross-sectional views which typically illustrate an example of the configuration of the semiconductor device; -
FIG. 5A is a plan view of a semiconductor device according to a second embodiment of the present invention; -
FIG. 5B is a cross-sectional view, taken along a line B-B shown inFIG. 5A , of the semiconductor device according to the second embodiment -
FIG. 6A toFIG. 6C are cross-sectional views of a semiconductor device according to a third embodiment of the present invention; -
FIG. 7A toFIG. 7J are cross-sectional views for explaining an example of a method of manufacturing the semiconductor device in the third embodiment; -
FIG. 8 toFIG. 10 are cross-sectional views of a semiconductor device according to a fourth embodiment of the present invention; and -
FIG. 11 andFIG. 12 are cross-sectional views of a semiconductor device according to a fifth embodiment of the present invention. - Exemplary embodiments of a semiconductor device and a method of manufacturing the semiconductor device according to the present invention will be explained hereinafter in detail with reference to the accompanying drawings.
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FIG. 1A andFIG. 1B typically illustrate asemiconductor device 10 according to a first embodiment of the present invention.FIG. 1A is a perspective view, andFIG. 1B is a cross-sectional view, taken along a line A-A shown inFIG. 1A , of thesemiconductor device 10. - The
semiconductor device 10 is constituted based on a two-dimensional slab photonic crystal structure. In thesemiconductor device 10, aslab layer 4 is formed by sequentially stacking alower cladding layer 2, anactive layer 1, and anupper cladding layer 3 on asubstrate 5, an interior of which is hollow, and a periodic refractive index profile structure is formed in a two-dimensional plane of theslab layer 4. In the example ofFIG. 1A andFIG. 1B , a triangular lattice-likeair hole structure 6 is formed, as the periodic refractive index profile structure formed on theslab layer 4, to penetrate theslab layer 4 in a stack direction. A linear defect (waveguide 7) for the periodicair hole structure 6 in the two-dimensional plane is formed near a center of theslab layer 4. In another embodiment, as shown inFIG. 1C , thesemiconductor device 10 is constituted based on the two-dimensional slab photonic crystal structure. In thesemiconductor device 10, adielectric layer 20 is formed in a lower portion of the periodicair hole structure 6, theslab layer 4 is formed by sequentially stacking thelower cladding layer 2, theactive layer 1, and theupper cladding layer 3 on thedielectric layer 20, and the periodic refractive index profile structure is formed in the two-dimensional plane of theslab layer 4. In still another embodiment, as shown inFIG. 1D , thesemiconductor device 10 is constituted based on the two-dimensional slab photonic crystal structure. In thesemiconductor device 10, asolid semiconductor layer 5 is formed in the lower portion of the periodicair hole structure 6, theslab layer 4 is formed by sequentially stacking thelower cladding layer 2, theactive layer 1, and theupper cladding layer 3 on thesolid semiconductor layer 5, and the periodic refractive index profile structure is formed in the two-dimensional plane of theslab layer 4. - The present invention is characterized as follows. In the
semiconductor device 10 including the two-dimensional slab photonic crystal thus constituted, a p-type region and an n-type region are formed in surfaces of the stacked layers in theslab layer 4 and a pn junction surface having a predetermined angle with respect to the surfaces of the stacked layers in theslab layer 4 is formed in order to pump theactive layer 1 by current injection.FIG. 2A toFIG. 2C typically illustrate form of a pn junction in theslab layer 4. To facilitate understanding of these forms, theair hole structure 6 is not shown inFIG. 2A toFIG. 2C . A pn junction may be formed by forming a p-type region 1 p and an n-type region 1 n in theactive layer 1 as shown inFIG. 2A . The pn junction may be formed by forming an n-type region 2 n and a p-type region 3 p in the lower and upper cladding layers 2 and 3, between which theactive layer 1 as an intrinsic layer is put, respectively, as shown inFIG. 2B or forming a p-type region 2 p and an n-type region 3 n in the upper andlower cladding layers FIG. 2C . Further, the pn junction may be formed by a combination thereof. Namely, each of the p-type region and the n-type region may be formed in the active layer, thelower cladding layer 2, or theupper cladding layer 3 so as to form a pn junction surface in theslab layer 4 at a predetermined angle with respect to the surfaces of the stacked layers in theslab layer 4. - By thus forming the pn junction surface so as to have the predetermined angle with respect to the surfaces of the stacked layers in the
slab layer 4, a current can be carried to cross the pn junction surface. It is preferable that a cross line between the pn junction surface and the surfaces of the stacked layers in theslab layer 4 is equal to an extension direction of the waveguide (linear defect) 7. In order to carry the current to cross the pn junction surface, it is not always necessary to attach electrodes vertically to the stack direction of theslab layer 4 but it suffices to arrange them on both sides of theslab layer 4 between which the pn junction is put, respectively. As a result, it is possible to simplify the structure and manufacturing of thesemiconductor device 10 having the two-dimensional slab photonic crystal structure in which the electrodes are attached. - The
semiconductor device 10 is made of compound semiconductors each having a heterojunction if theactive layer 1 is a single layer. Thesemiconductor device 10 is made of compound semiconductors each having a multiple quantum well (MQW) junction if the active layer has an MQW structure. Accordingly, any ordinary compound semiconductor can be used as a material for each of theactive layer 1 and the cladding layers 2 and 3. Specifically, GaAs, InGaAsP, AlGaAs, GaP, GaAsP, AlGaInP, GaInNAs or the like can be as a material for each of theactive layer 11 and the cladding layers 2 and 3. Zn, Be, Cd, Si, Ge, C, Mg or the like can be used as a p-type dopant to transform the material to the p-type material, and Si, Ge, S, Sn, or Te can be used as an n-type dopant to transform the material to the n-type material. - A method of manufacturing the
semiconductor device 10 will next be explained.FIG. 3A toFIG. 3G are cross-sectional side views to explain the method of manufacturing thesemiconductor device 10. InFIG. 3A toFIG. 3G , an instance in which InP is used as a material for thesubstrate 5, n-type InGaAsP (n-InGaAsP) is used as a material for each of thelower cladding layer 2, theactive layer 1, and theupper cladding layer 3, and in which Zn is used as a p-type dopant will be explained. - On an
InP substrate 5, a thin film of an n-InGaAsP layer that serves as thelower cladding layer 2 having a relatively large energy band gap is grown by a crystal structure system such as a metal-organic chemical vapor deposition (MOCVD) system or a molecular beam epitaxy (MBE) system. A thin film of theactive layer 1 having a relatively small energy band gap as compared with that of thelower cladding layer 2, i.e., made of n-InGaAsP slightly different in composition ratio from thelower cladding layer 2, and including an MQW layer and a barrier layer, is then grown by the crystal growth system such as the MOCVD or MBE system. Thicknesses, the number of layers, and energy band gap values of the MQW layer and the barrier layer determine a light emission wavelength band of theactive layer 1. Therefore, theactive layer 1 is formed in accordance with the wavelength band of the two-dimensional slab photonic crystal structure and the wavelength band required for thesemiconductor device 10 to be manufactured. On theactive layer 1, a thin film of an n-InGaAsP layer that serves as theupper cladding layer 3 having a relatively large energy band gap is grown by the crystal growth system such as the MOCVD or MBE system. A state in which thelower cladding layer 2, theactive layer 1, and theupper cladding layer 3 are thus formed on thesubstrate 5 is shown inFIG. 3A . - As shown in
FIG. 3B , aZnO layer 11 is stacked on substantially half of theupper cladding layer 3, and amask layer 12 made of Si3N4 or SiO2 is formed on theZnO layer 11. Thereafter, the substrate on which theZnO layer 11 and themask layer 12 are formed is subjected to annealing in a high temperature bath, thereby diffusing Zn to reach theactive layer 1. As a result, Zn is diffused into theactive layer 1 and the pn junction is formed in theactive layer 1.FIG. 3C illustrates this state. That is, the active layer includes two regions of the n-type region 1 n and the p-type region 1 p. Themask layer 12 acts as a cap that prevents the dopant from being diffused from the surface of the film into an annealing atmosphere during the annealing. - The
mask layer 12 and theZnO layer 11 are removed and an electron beam (EB) exposure resist 13 made of an organic material is applied onto an upper surface of theupper cladding layer 3.FIG. 3D illustrates this state. - As shown in
FIG. 3E , a pattern for forming a refractive index profile structure including a defect structure (which is the periodicair hole structure 6 in the two-dimensional plane in this embodiment) is drawn by an EB exposure system. The EB exposure resist 13 in the region in which the refractive index profile structure is to be formed is removed while the EB exposure resist 13 in the region other than the region is left. - As shown in
FIG. 3F , etching is performed up to an upper portion of thesubstrate 5 to penetrate theslab layer 4 from theupper cladding layer 3 to the InGaAsP layer that is thelower cladding layer 2, by an etching device such as a reactive ion etching (RIE) device or an induced coupled plasma etching (ICP) device, thereby forming theair hole structure 6. At this moment, if thesubstrate 5 is etched to some extent, a next step of selectively removing a substrate part in a lower portion of the periodic structure can be easily, appropriately executed. Thereafter, the EB exposure resist 13 applied onto the region in which etching has not been performed is removed. - As shown in
FIG. 3G , only thesubstrate 5 in the lower portion of the two-dimensional periodicair hole structure 6 is selectively removed by wet etching, thereby obtaining thesemiconductor device 10 having the two-dimensional slab photonic crystal structure including the pn junction surface having a predetermined angle with respect to the surfaces of the stacked layers in theslab layer 4. At this moment, the interior of thesubstrate 5 is hollow and the peripheral edge portion of the sheet-like slab layer 4 is supported by thesubstrate 5. With this structure, upper and lower surfaces of theslab layer 4 are in contact with the air. In the example ofFIG. 3A toFIG. 3G , a pn junction surface at an angle substantially perpendicular to the surfaces of the stacked layer in theslab layer 4 is formed. - While
FIG. 3A toFIG. 3G illustrate an example of the method of manufacturing thesemiconductor device 10, thesemiconductor device 10 may be manufactured by some other method. For example, after themask layer 11 and theZnO layer 12 shown inFIG. 3C are removed, a dielectric mask or a metallic mask layer including a dielectric film made of SiNx, SiO2 or the like and a metallic film made of Ti or the like is deposited on theupper cladding layer 3. A pattern for forming the periodic refractive index structure (which is the periodic air hole structure 6) including the defect structure is formed on the dielectric mask or metallic mask layer by a photo-etching process, an EB etching process, or the like. Etching is performed up to the upper layer portion of thesubstrate 5 so as to penetrate theslab layer 4 from theupper cladding layer 3 to thelower cladding layer 2. In addition, only thesubstrate 5 that constitutes the lower portion of theair hole structure 6 is selectively removed by wet etching for selectively removing the interior of thesubstrate 5. Finally, the dielectric film and the metallic film in portions in which etching has not been performed are removed, thereby obtaining thesemiconductor device 10. - If the pn junction is formed on the
active layer 1 inFIG. 3A toFIG. 3G , the upper andlower cladding layers active layer 1. By doing so, the pn junction obtained by Zn diffusion is formed only in theactive layer 1 and a current can be efficiently applied to the pn junction in theactive layer 1. The instance in which the pn junction surface is formed on theactive layer 1 has been explained with reference toFIG. 3A toFIG. 3G . Alternatively, theactive layer 1 may be an intrinsic layer and the pn junction may be formed on the upper andlower cladding layers active layer 1 is put. If so, it is preferable to form a p-type structure and an n-type structure or the n-type structure and the p-type structure diagonal to each other on the upper andlower cladding layers waveguide 7 put therebetween. Namely, thelower cladding layer 2 is doped with the n-type (or the p-type) dopant by injecting ions only into one side of thelayer 2 relative to a neighborhood of a center of the (portion which serves the)waveguide 7. Theupper cladding layer 3 is doped with the p-type (or the n-type) dopant by injecting or diffusing ions into the opposite side (that is, a portion diagonal to the n-type or p-type structure on the lower cladding layer 2) of thelayer 3. By doing so, a state similar to a boundary between the p-type structure and the n-type structure is realized on the active layer in the portion constituting thewaveguide 7 and the current is efficiently carried locally. At this moment, it is necessary to perform annealing so that the dopant sufficiently reaches theupper cladding layer 2. - Furthermore, by determining whether surface morphology is good or whether accuracy for managing dopant diffusion time is high, the entire substrate may be a p-type wafer, i.e., the
active layer 1 or the upper andlower cladding layers FIG. 4A , after manufacturing thesemiconductor device 10 shown inFIG. 3G , a separatelyprepared substrate 21 may be fusion-connected to theupper cladding layer 3 in theslab layer 4 and theoriginal substrate 5 may be cut off. As shown inFIG. 4B , thesemiconductor device 10 shown inFIG. 1C can be manufactured by selecting an Al-containing compound semiconductor material as a material for thesubstrate 5, and oxidizing the Al-containing compound semiconductor material to form adielectric layer 20 made of Al2O3 or the like after the step shown inFIG. 3F by a method including steps of arranging the Al-containing compound semiconductor material in, for example, a steam atmosphere, and of setting the temperature of the compound semiconductor material at a high temperature of 300 degrees or more, or the like. If thesemiconductor device 10 is thus manufactured, the step shown inFIG. 3G after the step shown inFIG. 3F is not executed. InFIG. 1C , the Al-containing compound semiconductor material is used as a material for thesubstrate 5. Alternatively, an Al-containing compound semiconductor material may be formed between thesubstrate 5 which does not contain Al and thelower cladding layer 2 or between thesubstrate 5 and thelower cladding layer 2 and on the upper cladding layer 3 (the resultant substrate corresponds to, for example, an epitaxially grown substrate referred to as “epitaxial wafer” or “epitaxial substrate” obtained by epitaxially growing a buffer layer, upper and lower cladding layers, an MQW active layer or the other active layer, and an Al-containing compound semiconductor film such as an AlGaAs layer on a crystal substrate which does not contain Al such as an InP crystal substrate). The Al-containing compound semiconductor material may be oxidized after the step shown inFIG. 3F . - According to the first embodiment, the
semiconductor device 10 is constituted by the two-dimensional slab photonic crystal including the pn junction surface at the predetermined angle with respect to the surfaces of the stacked layers in theslab layer 4. Therefore, it is advantageously possible to carry the current for pumping theactive layer 1 in the direction parallel to the surfaces of the stacked layers in theslab layer 4. In this first embodiment, the other layers are not explained in detail so as to explain the pn junction in detail. However, it is necessary to form an ohmic contact layer at need to obtain an ohmic junction when forming electrodes, which will be explained later. Further, after forming the periodicair hole structure 6 as shown inFIG. 3F , a thin semiconductor slab layer that efficiently confines light can be formed by transforming an Al-containing semiconductor made of AlAs, AlGaAs, or AlInAs to a low refractive index dielectric, instead of removing the lower portion of thesubstrate 5 by selective etching. Instead of using the slab structure, it is possible to obtain a high refractive index difference that cannot be obtained by ordinary crystal growth of semiconductors of the same type, by the junction of semiconductors of different types such as GaAs and InP using by fusion junction. This structure enables efficient optical confinement as compared with the instance of stacking theactive layer 1 and the upper andlower cladding layers semiconductor device 10. -
FIG. 5A andFIG. 5B are views to explain asemiconductor device 50 according to a second embodiment of the present invention. Thesemiconductor device 50 includes electrodes, to inject an electric current into the device, in addition to the configuration of thesemiconductor device 10 according to the first embodiment.FIG. 5A is a plan view of thesemiconductor device 50 andFIG. 5B is a cross-sectional view, taken along a line B-B shown inFIG. 5A . -
Electrodes semiconductor device 50 are formed on respective both end portions of thesemiconductor device 50 that includes the pn junction surface at the predetermined angle with respect to the surfaces of the stacked layers in theslab layer 4 explained in the first embodiment, between which thewaveguide 7 is put, so as to be substantially in parallel to the extension direction of thewaveguide 7. It is preferable that a direction of the cross line between the pn junction surface and the surfaces of the stacked layers in theslab layer 4 is substantially equal to the extension direction of thewaveguide 7. By connecting a positive electrode of a power supply to theelectrode 8 p formed in the p-type region 1 p of theactive layer 1 and connecting a negative electrode of the power supply to theelectrode 8 n formed in the n-type region 1 n of theactive layer 1, an injection current i can be injected into thesemiconductor device 50 substantially horizontally to theactive layer 1. As a result, carriers can be efficiently injected into the pn junction section. Such a configuration enables efficient lasing if thesemiconductor device 50 is employed as the semiconductor laser oscillator. - The
electrodes semiconductor device 50, manufactured inFIG. 3F which illustrates the first embodiment, in which portions theelectrodes semiconductor device 50. During the formation of theelectrodes type electrode 8 p formed in the p-type region, and an alloy containing a combination of Au, Ge, Ni, In, W, Ag, Sn, Te, Mo, W, Si, Al, Cu, Pd, Ta, Bi, Be, and the like can be used as a material for the n-type electrode 8 n formed in the n-type region. - Further, by using, as the
substrate 5, a semi-insulating substrate made of Fe-doped InP, undoped (intrinsic) GaAs, or Cr-doped GaAs, it is possible to suppress leakage of the injection current i to thesubstrate 5 and to realize more efficient carrier injection into theactive layer 1. If theentire substrate 5 is not semi-insulating, but if the p-type or n-type semiconductor substrate 5 is used and thelower cladding layer 2 is a semi-insulating layer or an undoped layer or if a semi-insulating layer or an undoped layer having a thickness of 100 nanometers or more is formed between thelower cladding layer 2 and thesubstrate 5, then it is also possible to suppress the leakage of the injection current i to thesubstrate 5. - Furthermore, as shown in
FIG. 5B , if theupper cladding layer 3 is a cladding layer doped with the p-type dopant and thelower cladding layer 2 is a cladding layer doped with the n-type dopant, the current can be efficiently carried to the pn junction section in theactive layer 1. If so, by using at least one of boundaries between theactive layer 1 and theupper cladding layer 3 and between theactive layer 1 and thelower cladding layer 2 as a waveguide part, it is possible to easily concentrate the current on the waveguide part ofactive layer 1 and to realize efficient lasing. By using both of the boundaries between theactive layer 1 and theupper cladding layer 3 and between theactive layer 1 and thelower cladding layers 2 as the waveguide part and arranging the upper andlower cladding layers FIG. 2B andFIG. 2C , it is possible to more easily concentrate the injection current on the waveguide part of theactive layer 1 and to realize more efficient lasing. In the second embodiment, even if theupper cladding layer 3 is doped with the n-type dopant and thelower cladding layer 2 is doped with the p-type dopant, thesemiconductor device 50 can exhibit the same advantages. - According to the second embodiment, the
electrodes waveguide 7 is put in the direction substantially equal to the extension direction of the pn junction surface provided at the predetermined angle with respect to the surfaces of the stacked layers in theslab layer 4, so as to be substantially in parallel to the extension direction of thewaveguide 7. Therefore, carriers can be efficiently injected into the pn junction section of theactive layer 1. -
FIG. 6A toFIG. 6C are cross-sectional views of asemiconductor device 60 according to a third embodiment of the present invention. Thesemiconductor device 60 is characterized in that theohmic contact layer 9 made of InGaAs or the like is formed, as an uppermost layer, between the two-dimensional slab photonic crystal (upper cladding layer 3) and electrodes 8 so as to have ohmic contact between the electrodes 8 and theslab layer 4. However, if theohmic contact layer 9 is left on an upper portion of a laser light emission section, theohmic contact layer 9 functions as an optical absorption layer. Therefore, it is necessary to remove theohmic contact layer 9 from the periodic two-dimensional refractive index profile structure. As shown inFIGS. 6B and 6C , anotherohmic contact layer 9 b may be formed under thelower cladding layer 2. As shown inFIG. 6B , a cross section of the n-type electrode 8 n-side semiconductor device 60 ranging from thesubstrate 5 to theupper cladding layer 3 may be exposed by anisotropic etching, and the n-type electrode 8 n may be formed on theohmic contact layer 9 b in the exposed lower portion of thesemiconductor device 60 as will be explained later. As shown inFIG. 6C , the n-type electrode 8 n-side substrate 5 may be removed to expose theohmic contact layer 9 b in the lower portion of thesemiconductor device 60 and the n-type electrode 8 n may be formed in the removed portion. -
FIG. 7A toFIG. 7J are cross-sectional views for explaining an example of a method of manufacturing thesemiconductor device 60. Similarly to the steps shown inFIG. 3A toFIG. 3C which illustrate the first embodiment, thelower cladding layer 2 such as an n-InGaAsP layer, theactive layer 1 made of n-InGaAsP or the like and including the MQW layer and the barrier layer, and theupper cladding layer 3 such as an n-InGaAsP layer are formed by the crystal growth system such as a metal-organic chemical vapor deposition (MOCVD) or a molecular beam epitaxy (MBE) system, and sequentially stacked on theInP substrate 5. Using a dielectric mask or the like, theZnO layer 11 is stacked on substantially the half surface of theupper cladding layer 3. Theresultant substrate 5 is subjected to annealing in the high temperature bath to diffuse Zn into theactive layer 1 or thelower cladding layer 2, and the pn junction is formed on theactive layer 1 or the upper andlower cladding layers 2 and 3 (FIG. 7A toFIG. 7C ). At this moment, an alignment mark that can identify the pn junction section is added to a portion of theupper cladding layer 3 in which the electrode 8 or the like is not formed. - After removing the
ZnO layer 11 and themask layer 12 used to diffuse the dopant, theohmic contact layer 9 is stacked on an upper surface of theupper cladding layer 3 as shown inFIG. 7D , and adielectric mask layer 14 made of SiNx, SiO2 or the like and an EB exposure resistlayer 15 are formed on theohmic contact layer 9. Thereafter, as shown inFIG. 7E , based on the alignment mark added onto the surface of thesubstrate 5, a pattern for forming the periodic refractive index profile structure including a defect structure is drawn by the EB exposure device. In addition, the EB exposure resistlayer 15 in a portion in which the periodic refractive index profile structure is to be formed is removed while leaving thelayer 15 in portions other than the portion in which the periodic refractive index profile structure is formed. At this step, the pattern for forming the periodic refractive index profile structure including the defect structure is drawn by the EB exposure device so that a center of a width of the linear defect that serves as thewaveguide 7 is at a position of the alignment mark. As shown inFIG. 7F , theair hole structure 6 is formed to penetrate the surfaces of the stacked layers in theslab layer 4 substantially in a perpendicularly direction by the etching system such as the ICP system. - After removing the EB exposure resist
layer 15 and thedielectric mask layer 14, afirst photomask 16 is formed on theohmic contact layer 9. Thefirst photomask 16 at a position at which the p-type electrode 8 p formed in the p-type region is arranged is removed. The p-type electrode 8 p, including, for example, AuZn of a thickness of 50 nanometers, Ti of a thickness of 10 nanometers, and Al of a thickness of 500 nanometers, is formed in the first photomask 16-removed portion by vacuum evaporation, sputtering, or the like, and theelectrode 8 p is alloyed.FIG. 7G illustrates this state. - After removing the
first photomask 16, asecond photomask 17 is formed on theohmic contact layer 9 and the p-type electrode 8 p, and thesecond photomask 17 at a position at which the n-type electrode 8 n formed in the n-type region is arranged is removed. The n-type electrode 8 n, including, for example, AuGe of a thickness of 50 nanometers, Ni of a thickness of 10 nanometers, and Au of a thickness of 500 nanometers, is formed in the second photomask 17-removed portion by vacuum evaporation, sputtering, or the like, and theelectrode 8 n is alloyed.FIG. 7H illustrates this state. - As shown in
FIG. 7I , thesecond photomask 17 is removed and theohmic contact layer 9 in portions other than those in which theelectrodes FIG. 7J , only thesubstrate 5 in the lower portion of the two-dimensional periodicair hole structure 6 is selectively etched by wet etching, thereby obtaining thesemiconductor device 10 in which the peripheral edge of the sheet-like slab layer 4 is supported by the peripheral edge of thesubstrate 5 the interior of which is hollow. Wirings necessary to drive thesemiconductor device 10 are arranged by wire bonding or the like. - It is preferable to arrange the two
electrodes electrodes electrodes waveguide 7, theohmic contact layer 9 functions as the optical absorption layer. It is, therefore, necessary to provide theohmic contact layer 9 to be away from thewaveguide 7 to the extent that theohmic contact layer 9 does not greatly absorb light. Conversely, if the twoelectrodes air hole structure 6 in the two-dimensional slab photonic crystal functions as a resistance against the injection current. It is, therefore, necessary to provide theelectrodes waveguide 7 by forming the structure in a range of about minus and plus ten micrometers from thewaveguide 7 in a horizontal direction. If a distance between the portions of the ohmic contact layers 9 (i.e., between theelectrodes FIG. 7I , theohmic contact layer 9 within the range of plus and minus ten micrometers from thewaveguide 7 in the direction orthogonal to the extension direction of thewaveguide 7 is removed in the parallel direction to the extension direction of thewaveguide 7 based on the alignment mark added onto the surface of thesubstrate 5 during the formation of the pn junction. A removal width of theohmic contact layer 9 may be further narrowed within an allowable range of optical absorption. This can reduce loss caused by the electric resistance (i.e., lasing efficiency can be improved). At this moment, theohmic contact layer 9 is often formed so as to overlap theair hole structure 6. If so, theohmic contact layer 9 can be removed with high accuracy. - The instance in which the periodic
air hole structure 6 is processed after forming the pn junction has been explained. This is intended to prevent the pattern for forming theair hole structure 6 from being deformed. - The method of manufacturing the
semiconductor device 60 explained above is only an example. Any other know method may be used to manufacture thesemiconductor device 60. The instance in which the periodicair hole structure 6 is formed after the pn junction is formed has been explained. Alternatively, for example, thesemiconductor device 60 may be formed by forming the pattern for forming the periodicair hole structure 6 including the linear defect structure, adding the alignment mark to the position at which the center of the width of the linear defect can be identified, and then forming the pn junction based on the alignment mark. - According to the third embodiment, the
ohmic contact layer 9 is formed between theslab layer 4 and the electrodes 8. It is, therefore, advantageously possible to carry an ohmic current between theslab layer 4 and the electrodes 8. - Further, since the periodic
air hole structure 6 is processed after the pn junction is formed, it is possible to prevent theair hole structure 6 from being deformed. During the formation of the pn junction, the alignment mark that can identify the pn junction section is formed and the periodicair hole structure 6 including the defect structure is formed based on the alignment mark. It is, therefore, possible to control alignment between theair hole structure 6 and the pn junction section with high accuracy. After each electrode 8 is formed, the interior of thesubstrate 5 is undercut by wet etching to thereby form a slab. Therefore, the probability of damaging the thin slab during the electrode formation process can be advantageously avoided. In the third embodiment, a layer formed between thelower cladding layer 2 and thesubstrate 5 has not been explained at all. However, if a layer of any structure such as another ohmic contact layer or a buffer layer intended to improve flatness is formed therebetween, it is possible to improve a degree of freedom for later electrode formation and improve crystal quality. In the third embodiment, the p-type dopant is doped by diffusing Zn. Alternatively, if the p-type dopant and the n-type dopant are employed oppositely for ion injection, epitaxial states before diffusion and injection, and the dopants to be diffused and injected, thesemiconductor device 60 can exhibit the same advantages. In the third embodiment, similarly to the preceding embodiments, the step of forming the dielectric supported or semiconductor supported structure instead of forming the hollow slab can be applied. -
FIG. 8 toFIG. 10 are cross-sectional views of asemiconductor device 70 according to a fourth embodiment of the present invention. Thesemiconductor device 70 is characterized in that a position at which one of the electrodes 8 is attached is set lower than theupper cladding layer 3. - As shown in
FIG. 8 , thelower cladding layer 2 in a region in which oneelectrode 8 n is formed is exposed, that is, thelower cladding layer 2 is exposed while providing a stepped portion so that the region in which theelectrode 8 n is formed is lower than the other regions. Theelectrode 8 n is formed on thelower cladding layer 2 thus exposed. One side surface of theelectrode 8 n formed at this step is in contact with theactive layer 1. The stepped portion can be formed by the dry etching system such as the ICP or RIE system. In this instance, if theactive layer 1 is doped with the p-type dopant and the n-type dopant, and if one of or both of the p-type region 1 p-sideupper cladding layer 3 and the n-type region 1 n-sidelower cladding layer 2 are similarly doped with the p-type dopant and the n-type dopant, respectively, (that is, if one of or both of the upper andlower cladding layers active layer 1 and efficient lasing can be realized. Besides, if only theactive layer 1 is doped with the p-type dopant and the n-type dopant, more efficient lasing can be realized. -
FIG. 9 illustrates that the stepped portion is formed up to the region of theactive layer 1 without exposing thelower cladding layer 2 as shown inFIG. 8 , and that theelectrode 8 n is formed on the partially exposedactive layer 1. In the instance shown inFIG. 9 , similarly to the instance shown inFIG. 8 , one side surface of theelectrode 8 n thus formed is in contact with theactive layer 1. In this instance, if theactive layer 1 is doped with the p-type dopant and the n-type dopant, and if one of or both of the p-type region 1 p-sideupper cladding layer 3 and the n-type region 1 n-sidelower cladding layer 2 are similarly doped with the p-type dopant and the n-type dopant, respectively, (that is, if one of or both of the upper andlower cladding layers active layer 1 and efficient lasing can be realized. Besides, if only theactive layer 1 is doped with the p-type dopant and the n-type dopant, more efficient lasing can be realized. -
FIG. 8 andFIG. 9 illustrate the configurations in which one side surface of theelectrode 8 n is in contact with theactive layer 1. However, it is difficult to control an electrode formation state with these configurations. Therefore, as shown inFIG. 10 , instead of bringing one side surface of theelectrode 8 n into contact with theactive layer 1, a surface of theelectrode 8 n substantially horizontal to the surfaces of the stacked layers in theslab layer 4 may be brought into contact with thelower cladding layer 2. By doing so, theelectrode 8 n is formed in the stepped portion formed by dry etching so that the side surface of theelectrode 8 n is out of contact with theactive layer 1. WhileFIG. 10 illustrates the instance in which the horizontal surface of theelectrode 8 n is in contact with thelower cladding layer 2, the horizontal surface thereof may be in contact with theactive layer 1. In this instance, if theactive layer 1 is doped with the p-type dopant and the n-type dopant, and if one of or both of the p-type region 1 p-sideupper cladding layer 3 and the n-type region 1 n-sidelower cladding layer 2 are similarly doped with the p-type dopant and the n-type dopant, respectively, (that is, if one of or both of the upper andlower cladding layers active layer 1 and efficient lasing can be realized. Besides, if only theactive layer 1 is doped with the p-type dopant and the n-type dopant, more efficient lasing can be realized. - While
FIG. 8 toFIG. 10 illustrate that theelectrode 8 n is directly formed on theactive layer 1 or thelower cladding layer 2, theohmic contact layer 9 may be formed at the position at which the stepped portion is formed and theelectrode 8 n may be formed on the stepped portion as explained in the third embodiment. - According to the fourth embodiment, the
semiconductor device 70 is constituted so that the position at which one of the electrodes 8 is formed is set lower than theupper cladding layer 3. It is, therefore, possible to control a current path and efficiently inject the current into the pn junction section in theactive layer 1. In the fourth embodiment, even if the p-type dopant and the n-type dopant are oppositely doped, thesemiconductor device 10 can exhibit the same advantages. -
FIG. 11 andFIG. 12 are cross-sectional views of asemiconductor device 80 according to a fifth embodiment of the present invention. As shown inFIG. 11 , thesemiconductor device 80 is characterized in that electrode formation portions are formed aslant relative to the horizontal direction by anisotropic etching using crystal orientation. - For example, if InP having the same structure as that of InGaAsP is used as a material, it is known that a crystal orientation [001] is faster in etching rate than a crystal orientation [011]. Therefore, if the
slab layer 4 is epitaxially grown so that a surface (001) is in parallel to the surface of thesubstrate 5 and subjected to wet etching, the surface (001) can be exposed to the end portions of theslab layer 4 as shown inFIG. 11 . Theelectrode 8 n can be attached to a portion including theactive layer 1 in the exposed region. Therefore, by thus forming each electrode formation portion to have a predetermined angle with respect to the surfaces of the stacked layers in theslab layer 4 and attaching each electrode 8 to the electrode formation portion, a good contact interface can be obtained. In this instance, if theactive layer 1 is doped with the p-type dopant and the n-type dopant, and if one of or both of the p-type region 1 p-sideupper cladding layer 3 and the n-type region 1 n-sidelower cladding layer 2 are similarly doped with the p-type dopant and the n-type dopant, respectively, (that is, if one of or both of the upper andlower cladding layers active layer 1 and efficient lasing can be realized. Besides, if only theactive layer 1 is doped with the p-type dopant and the n-type dopant, more efficient lasing can be realized. - The crystal orientation relationship is only one example. If the crystal is subjected to anisotropic etching, the
slab layer 4 can be grown so that a surface having a higher etching rate is aslant at a predetermined angle with respect to the surface of thesubstrate 5. -
FIG. 11 illustrates that theelectrode 8 n is brought into contact with theactive layer 1 and thelower cladding layer 2 while making theelectrode 8 n out of contact only with theupper cladding layer 3. Alternatively, theelectrode 8 n may be brought into contact only with thelower cladding layer 2 while making theelectrode 8 n out of contact with both theupper cladding layer 3 and theactive layer 1. If so, as explained in the third embodiment, theohmic contact layer 9 may be provided between theelectrode 8 n and theslab layer 4. In this instance, if theactive layer 1 is doped with the p-type dopant and the n-type dopant, and if one of or both of the p-type region 1 p-sideupper cladding layer 3 and the n-type region 1 n-sidelower cladding layer 2 are similarly doped with the p-type dopant and the n-type dopant, respectively, (that is, if one of or both of the upper andlower cladding layers active layer 1 and efficient lasing can be realized. Besides, if only theactive layer 1 is doped with the p-type dopant and the n-type dopant, more efficient lasing can be realized. -
FIG. 11 illustrates that only theelectrode 8 n provided on one side of thesemiconductor device 80 is subjected to anisotropic etching. Alternatively, theelectrodes FIG. 12 . In this instance, if theactive layer 1 is doped with the p-type dopant and the n-type dopant, and if one of or both of the p-type region 1 p-sideupper cladding layer 3 and the n-type region 1 n-sidelower cladding layer 2 are similarly doped with the p-type dopant and the n-type dopant, respectively, (that is, if one of or both of the upper andlower cladding layers active layer 1 and efficient lasing can be realized. Besides, if only theactive layer 1 is doped with the p-type dopant and the n-type dopant, more efficient lasing can be realized. If so, it suffices that each of theelectrodes active layer 1 and the upper andlower cladding layers - According to the fifth embodiment, the
semiconductor device 80 is constituted so that theslab layer 4 is subjected to wet etching so as to expose the surface aslant at the predetermined angle with respect to the surfaces of the stacked layers in theslab layer 4 using the anisotropy of the material for theslab layer 4 during wet etching, and each electrode 8 is formed on the exposed surface. Therefore, it is advantageously possible to obtain the good contact interface between the electrode 8 and theactive layer 1 or between the electrode 8 and thelower cladding layer 2. - According to the present invention, it is possible to carry a current for pumping the active layer in a direction parallel to the surfaces of the stacked layers in the slab layer. Accordingly, if the semiconductor device is employed as an active device, it is also advantageously possible to make the device small in size as compared with the conventional device which is unavoidably made large in size because the active layer can be pumped only by optical pumping.
- Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.
Claims (19)
1-36. (canceled)
37. A method of manufacturing a semiconductor device comprising:
forming a slab layer on a substrate by sequentially stacking a lower cladding layer, an active layer, and an upper cladding layer as stacked layers;
forming a pn junction surface at a predetermined angle with respect to surfaces of the stacked layers in the slab layer;
forming an ohmic contact layer for attaching an electrode, on the upper cladding layer;
forming a periodic air hole structures introducing a linear defect region serving as a waveguide, on the slab layer and the ohmic contact layer;
forming an electrode on the ohmic contact layer in each of a p-type region and an n-type region in the slab layer;
removing the ohmic contact layer; and
oxidizing an Al-containing layer in a lower portion or in both an upper portion and a lower portion of the slab layer into a dielectric layer, to form a semiconductor slab layer.
38. The method according to claim 37 , wherein
forming a slab layer includes forming each of the active layer and the upper and lower cladding layers of n-type compound semiconductor materials, and
forming the pn junction surface includes diffusing a dopant producing p-type conductivity into a predetermined region of the slab layer.
39. The method according to claim 37 , wherein
forming a slab layer includes forming each of the active layer and the upper and lower cladding layers of p-type compound semiconductor materials, and
forming the pn junction surface includes diffusing a dopant producing n-type conductivity into a predetermined region of the slab layer.
40. The method according to claim 37 , wherein
forming a pn junction surface includes forming an alignment mark on the slab layer that indicates position of the pn junction, and
removing the ohmic contact layer includes removing the ohmic contact layer in a predetermined region based on the alignment mark.
41. The method according to claim 37 , wherein
forming a pn junction surface includes forming an alignment mark on the slab layer that indicates position of the pn junction, and
forming the periodic air hole structure includes matching position of the periodic air hole structure with the alignment mark when forming the periodic air hole structure.
42. The method according to claim 37 , including forming the pn junction surface before forming the ohmic contact layer.
43. The method according to claim 37 , including forming the pn junction surface after forming the ohmic contact layer.
44. The method according to claim 37 , including forming the periodic air hole structure before removing the ohmic contact layer.
45. The method according to claim 37 , including forming the periodic air hole structure after removing the ohmic contact layer.
46. A method of manufacturing a semiconductor device comprising:
forming a slab layer on a first substrate by sequentially stacking a lower cladding layer, an active layer, and an upper cladding layer as stacked layers;
forming a pn junction surface at a predetermined angle with respect to surfaces of the stacked layers in the slab layer;
forming a periodic air hole structure introducing a linear defect region serving as a waveguide, on the slab layer;
removing a lower portion or an upper portion and a lower portion of the slab layer, to form a semiconductor slab layer;
fusing a second substrate, prepared separately from the first substrate, to the first substrate; and
forming an electrode in a p-type region and an n-type region on the second substrate that has been fused to the first substrate.
47. The method according to claim 46 , further comprising:
forming an ohmic contact layer for attaching the electrode, on the upper cladding layer, and
forming the pn junction surface before forming the ohmic contact layer.
48. The method according to claim 46 , further comprising forming an ohmic contact layer for attaching the electrode, on the upper cladding layer, and
forming the pn junction surface after forming the ohmic contact layer.
49. The method according to claim 46 , further comprising
forming an ohmic contact layer for attaching the electrode, on the upper cladding layer, and
forming the periodic air hole structure before removing the ohmic contact layer.
50. The method according to claim 46 , further comprising
forming an ohmic contact layer for attaching the electrode, on the upper cladding layer, and
forming the periodic air hole structure after removing the ohmic contact layer.
51. The method according to claim 46 , further comprising forming an ohmic contact layer for attaching the electrode, on a lower portion of the lower cladding layer.
52. A method of manufacturing a semiconductor device comprising:
forming a slab layer on a substrate by sequentially stacking a lower cladding layer, an active layer, and an upper cladding layer as stacked layers;
forming an ohmic contact layer for attaching an electrode, on the upper cladding layer;
forming a periodic air hole structure introducing a linear defect region serving as a waveguide, on the slab layer and the ohmic contact layer;
forming a pn junction surface at a predetermined angle with respect to surfaces of the stacked layers in the slab layer;
forming an electrode on the ohmic contact layer in each of a p-type region and an n-type region in the slab layer;
removing the ohmic contact layer; and
removing an interior portion of the substrate, so the substrate is hollow, to form the sheet-like slab layer.
53. The method according to claim 52 , including forming the periodic air hole structure before removing the ohmic contact layer.
54. The method according to claim 52 , including forming the periodic air hole structure after removing the ohmic contact layer.
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US11/375,016 US7390683B2 (en) | 2003-07-25 | 2006-03-15 | Method of manufacturing a semiconductor device including a slab layer with a periodic air hole structure and a linear defect region |
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US7390683B2 (en) | 2008-06-24 |
US20050029536A1 (en) | 2005-02-10 |
JP2005045162A (en) | 2005-02-17 |
US20060157716A1 (en) | 2006-07-20 |
US7042014B2 (en) | 2006-05-09 |
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