US20080224158A1 - Light Emitting Device With Undoped Substrate And Doped Bonding Layer - Google Patents
Light Emitting Device With Undoped Substrate And Doped Bonding Layer Download PDFInfo
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- US20080224158A1 US20080224158A1 US11/860,502 US86050207A US2008224158A1 US 20080224158 A1 US20080224158 A1 US 20080224158A1 US 86050207 A US86050207 A US 86050207A US 2008224158 A1 US2008224158 A1 US 2008224158A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/405—Reflective materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/42—Transparent materials
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Abstract
Description
- The present application is a continuation of and claims priority to U.S. patent application Ser. No. 10/960,391, filed Oct. 6, 2004, entitled “Contact and Omnidirectional Reflective Mirror for Flip Chipped Light Emitting Devices”, by Decai Sun, which is incorporated herein by reference.
- The present invention relates generally to light emitting diodes and more specifically to contacts for light emitting diodes.
- Semiconductor light emitting devices such as light emitting diodes (LEDs) are among the most efficient light sources currently available. Material systems currently of interest in the manufacture of high brightness LEDs capable of operation across the visible spectrum include group III-V semiconductors, particularly binary, ternary, and quaternary alloys of gallium, aluminum, indium, and nitrogen, also referred to as III-nitride materials; and binary, ternary, and quaternary alloys of gallium, aluminum, indium, and phosphorus, also referred to as III-phosphide materials. Often III-nitride devices are epitaxially grown on sapphire, silicon carbide, or III-nitride substrates and III-phosphide devices are epitaxially grown on gallium arsenide by metal organic chemical vapor deposition (MOCVD) molecular beam epitaxy (MBE) or other epitaxial techniques. These LED device structures can also be transferred to a transparent substrate by wafer bonding. Often, an n-type layer (or layers) is deposited on the substrate, then an active region is deposited on the n-type layers, then a p-type layer (or layers) is deposited on the active region. The order of the layers may be reversed such that the p-type layers are adjacent to the substrate by either epitaxial growth or wafer bonding.
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FIG. 1 illustrates a cross-sectional view of a conventional light emitting diode (LED) 10. As shown inFIG. 1 , one or more p type layers are formed over asubstrate 12. By way of example, a p-AlInP layer 16 may be formed over a p dopedregion 14 of aGaP substrate 10 by wafer bonding, and p-contacts 18 are formed on the p dopedregion 14. Anactive region 20 is formed over thep type layer 16 and ann type layer 22, e.g., an n-AlInP layer, is formed over theactive region 20. Ann contact 24 is formed over then type layer 22, but the contact area is minimized in order to increase the area of thereflective mirror 26 area for better light extraction through thesubstrate 10. Thus, theLED 10 can be used in a flip chip configuration with the p-contacts 18 and n-contacts 24 formed on the same side of the device when flip-chipped on a submount and where the light is extracted through thesubstrate 12, which is the top of the device. - The design scheme of the
flip chip LED 10 forces lateral current injection, which results in current crowding under the n-contact 24 and near thep contact area 18 as illustrated by the arrows inFIG. 1 . The current crowding results in non-uniform current injection as well as high series resistance and high forward voltage Vf compared to vertical injection LEDs. - One manner of solving the non-uniform current injection problem in the n-side is to use full sheet n-metal contact. However, because the n-metal contact has to be annealed at high temperature, e.g., greater than 420° C., to achieve a good ohmic contact, the metal surface is rough. As a result, the reflectively of the full sheet n-metal contact is poor and thus, decreases light extraction.
- Thus, it is highly desirable to improve the contacts used with LEDs reduce the non-uniform current injection problem without decreasing light extraction.
- In accordance with one embodiment, a light emitting device includes a stack of layers bonded to an undoped substrate with a doped layer between the stack of layers and the undoped substrate. The stack of layers include a layer of first conductivity type over the doped layer, an active region overlying the layer of first conductivity type, and a layer of second conductivity type overlying the active region. In one embodiment, the doped substrate is part of the stack of layers and is bonded to the undoped substrate. The doped layer and undoped substrate may be formed from the same semiconductor material, such as GaP. First and second electrical contacts are coupled to the device on a side opposite the undoped substrate. The doped layer may provide electrical contact between the first electrical contact and the layer of first conductivity type.
- In accordance with another embodiment, a method of forming a light emitting device includes providing a transparent undoped substrate and forming a stack of layers including a layer of first conductivity type, an active region over the layer of first conductivity type, a layer of second conductivity type over the active region. The method includes bonding the stack of layers to the undoped substrate with a doped layer between the stack and the undoped substrate. In one embodiment, the doped layer is part of the stack of layers and may be formed on a sacrificial substrate prior to bonding to the undoped substrate. The method further includes removing a portion of the layer of first conductivity type, the active region, and the layer of second conductivity type to expose the doped layer and forming a first electrical contact to contact the layer of first conductivity type and forming a second electrical contact to contact the exposed doped layer. The first and second electrical contacts are on the same side of the doped layer opposed the undoped substrate.
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FIG. 1 illustrates a cross-sectional view of a conventional light emitting diode. -
FIG. 2 illustrates a cross sectional view of a light emitting device that uses a full sheet contact with an omnidirectional high reflective mirror (ODRM) structure, in accordance with one embodiment of the present invention. -
FIG. 3 illustrates a top view of a light emitting device with an ODRM structure and a distributed p-contact array, in accordance with another embodiment of the present invention. -
FIG. 4 illustrates a cross sectional view of a portion of light emitting device fromFIG. 3 along line A-A. -
FIGS. 5A-5D illustrate an embodiment of the present invention at various stages during fabrication. -
FIG. 2 illustrates a cross sectional view of an light emitting device (LED) 100, in accordance with one embodiment of the present invention, that uses a full sheet contact with an omnidirectional high reflective mirror (ODRM)structure 101. - As shown in
FIG. 2 ,LED 100 includes one or more p-type layers 106 formed over asubstrate 102. The p-type layer 106, e.g., may be P-AlInP layers formed over a p dopedGaP layer 104 that is bonded to anundoped GaP substrate 102. Thep contacts 105, which may be formed from, e.g., AuZn, are formed over the p dopedGaP layer 104. Anactive region 108 is formed over thep type layer 106 and ann type layer 110, e.g., n-AlInP, is formed over theactive region 108. TheLED 100 may include one or morecapping layers 112, e.g., of n+GaAs and/or n+InGaP over then type layer 110. - The
ODRM structure 101 is formed over thecapping layers 112 from a full sheet conductivetransparent film 114 of, e.g., indium tin oxide (ITO), and a highreflective mirror 116 of, e.g., Ag or Au. The term “transparent” is used herein to indicate that an optical element so described, such as a “transparent film,” a “transparent layer,” or a “transparent substrate,” transmits light at the emission wavelengths of the LED with less than about 50%, preferably less than about 10%, single pass loss due to absorption or scattering. One of ordinary skill in the art will recognize that the conditions “less than 50% single pass loss” and “less than 10% single pass loss” may be met by various combinations of transmission path length and absorption constant. The conductivetransparent film 114 is sometimes referred to herein as anITO layer 114, but it should be understood that other conductive and transparent films may be used. The conductivetransparent film 114 serves as the n contact for theLED 100 and themirror 116 overlies the conductivetransparent film 114. Where indium tin oxide is used as the conductivetransparent film 114, the ITOlayer 114 has a thickness that is, e.g., a quarter of the wavelength produced by theLED 100. By example, theITO layer 114 is approximately 73 nm thick at a wavelength of 615 nm and has a refractive index of 2.1. The contact resistance of theITO layer 114 is expected to be 1.5 e−5Ω cm2 or lower, with a transmission of approximately 95% or better around 600 nm. - The
ODMR structure 101 provides high reflection for the light reaching theODRM structure 101 over all incident angles. For example, theODRM structure 101 with a quarterwavelength ITO layer 114 and anAg mirror 116 is expected to have a reflectively of over 90% for a wide range of incident angles. Moreover, using theITO layer 114 as a full sheet n-contact provides a uniform current injection from the n-side into theactive region 108, eliminating the current crowding problem at the n-layer 110 found in conventional devices. Accordingly, theODMR structure 101 reduces the forward voltage Vf and series resistance while increasing the extraction efficiency of theLED 100 compared to conventional devices. - It should be understood that, while the
LED 100 of the present embodiment is described as a flip chip AlInGaP type device, the present ODRM structure may be used with difference devices if desired. For example, the ODRM structure may be used with a flip chip InGaN LED devices. It has been demonstrated that the ITOlayer 114 can be used as a transparent contact on a p-GaN layer. TheITO layer 114 can also be applied on top of p-GaAs or P-InGaN contact layers. - With the use of the
ODRM structure 101, a uniform current injection is provided at the n side of the active region. The current injection at the p side of the active region, however, may still be problematic due to the lateral contact scheme in a wide mesa structure such as that shown inFIG. 2 . By way of example, for a 1 mm×1 mm square red flip chip die, four mesas are conventionally formed by etching to the p-GaP contact layer. The spacing between the p-contact and the center of the mesa for such a structure is over 100 μm. Due to the poor conductivity of the p-GaP, the hole injection on the p-side of the active region is not uniform across the mesa. Accordingly, current crowding may occur around the edges of the mesa. - Thus, in accordance with another embodiment of the present invention, a distributed p-contact array is used, along with the
ODRM structure 101, to improve current spreading and increase the junction area of the LED. The distributed contact array may be similar to that disclosed in U.S. 2003/0230754, entitled “Contacting Scheme for Large and Small Area Semiconductor Light Emitting Flip-Chip Devices”, by Daniel A. Steigerwald et al., filed Jun. 13, 2002, which has the same assignee as the present disclosure and is incorporated herein by reference. -
FIG. 3 illustrates a top view of anLED 200 with anODRM structure 201 that serves as the n-contact, and a distributed p-contact array, in accordance with an embodiment of the present invention.FIG. 4 illustrates a cross sectional view of a portion ofLED 200 along line A-A inFIG. 3 . - As can be seen in
FIG. 4 , the formation ofLED 200 is similar to that ofLED 100 shown inFIG. 2 . For example,LED 200 includes one or more p-type layers 206 formed over p dopedlayer 204 that is bonded to asubstrate 202. The p dopedlayer 204 may be, e.g., 2 to 20 μm of p-GaP that is optimized for good current spreading. In general, the thicker the p-dopedlayer 204, the larger the p-contact array spacing can be for uniform current spreading. A thicker p-dopedlayer 204, however, increases light absorption loss. Therefore, the p-dopedlayer 204 should be kept as thin as possible with a small p-contact array pitch for uniform current spreading. Over the p-type layer 206 is formed theactive region 208 and ann layer 210. Acapping layer 212 of, e.g., of n+GaAs and/or n+InGaP, is formed over then layer 210. TheODRM 201 is formed over thecapping layer 212 as a conductivetransparent film 214, such as a quarter wavelengththick ITO layer 214, and an Ag or Aureflective mirror 216 formed over theITO layer 214. TheLED 200 may be mounted to a submount (not shown) of silicon or ceramic and the cathode and the anode of theLED 200 can be connected to the corresponding contact pads on the submount through solder bumps or Au—Au stud bumps. - As illustrated in
FIG. 3 and 4 , however, the p-contact 205 is formed as a distributedarray 116 by etchingseveral vias 217 down to the p dopedlayer 204, by etching away theODRM 201, thecapping layer 212, the n-type layer 210, theactive region 208 and the p-type layer 206 with, for example, a reactive ion etch; by ion implantation; by dopant diffusion; or by selective growth of the layers. Thus, the p dopedlayer 204 is exposed for thep contact 205. Adielectric layer 218, such as SiNx or SiO2, is formed over the LED epi structure, i.e., layers 206, 208, 210, 212, and 201. Ap contact layer 220 of, e.g., AuZn, is formed over thedielectric layer 218 and is in electrical contact with the underlying p dopedlayer 204 to form thep contact 205. The p-contacts 205 in the distributedarray 216 are connected together byinterconnect 222, which is formed by thep contact layer 220, as illustrated inFIG. 3 . Thedielectric layer 218 isolates thep contact layer 220 from thereflective mirror 216 andITO layer 214 in theODRM 201. - By way of example, for a 500 μm×500 μm square LED chip, a 4×4 distributed p-contact array, such as that shown in
FIG. 3 , is formed by etchingvias 217 through the device and into the p-GaP layer 204 and depositing an AuZn p-contact layer 220 into thevias 217. The via pitch (dimension P inFIG. 3 ) may be, for example, about 50 μm to about 1000 μm, and is usually about 50 μm to about 200 μm. The via diameter (dimension D inFIG. 3 ) may be, for example, between about 2 μm and about 100 μm, and is usually between about 10 μm and about 50 μm. Where the via pitch is 100 μm and the via diameter is 25 μm, the farthest current conduction path for holes is approximately 37.5 μm, which is the distance from the edge of a p-contact 205 to the center of two adjacent p-contacts 205 and approximately 58 μm on the diagonally betweenp contacts 205. Moreover, the total junction area is approximately 96 percent. By way of comparison, a conventional LED of the same size with dual mesas and stripped p-contacts has a junction of approximately 75 percent assuming the mesa width is approximately 210 μm, the p-contact line around the mesa is 20 μm wide and the solder metal pad is 50 μm in diameter. - It should be understood, that the other dimensions or other materials may be used with the present invention if desired. Moreover, while the device illustrated in
FIG. 3 has a 4×4 rectangular array of vias, a rectangular array of a different size (for example, 6×6 or 9×9) may also be used, as well as a hexagonal array, a rhombohedral array, a face-centered cubic array, an arbitrary arrangement, or any other suitable arrangement. -
FIGS. 5A-5D illustrate an embodiment of the present invention at various stages during fabrication.Layers FIG. 5A , are epitaxially grown on an n-GaAs substrate (not shown) and then bonded toGaP substrate 202. Thus, thecapping layer 212, e.g., of n+GaAs or n+InGaP, is formed over the n-GaAs substrate. One or more n-type layers 210 are formed on thecapping layer 212. N-type layers 210 may include, for example, a buffer layer, a contact layer, an undoped crystal layer, and n-type layers of varying composition and dopant concentration. Anactive region 208 is then formed on the n-type layers 210.Active region 208 may include, for example, a set of quantum well layers separated by a set of barrier layers. One or more p-type layers 206 are formed on theactive region 208. P-type layers 206 may include, for example, may include, for example, a carrier confining layer, a contact layer, and other p-type layers of various composition and dopant concentration. The various layers may be deposited by, for example, MOCVD or other appropriate, well known techniques. The p-type layers 206 are then bonded to theGaP substrate 202 and the n-GaAs substrate is selectively removed. TheITO layer 214 is deposited over thecapping layer 212 and thereflective mirror layer 216 of, e.g., Ag or Au, is deposited over theITO layer 214 resulting in the structure shown inFIG. 5A . TheITO layer 214 and thereflective mirror layer 216 may be deposited by, e.g., e-beam evaporation or sputtering. - The
ITO layer 214,mirror layer 216 and thecapping layer 212 are patterned as shown inFIG. 5B , using for example photolithography along with etching, or a lift-off process. The patterning removes any of theITO layer 214,mirror layer 216 andcapping layer 212 that will not be used as an n-contact. The patterning thus removes any of the ncontact overlying vias 217 shown inFIGS. 3 and 4 . As shown inFIG. 5C , one or more etching steps are then performed to formvias 217. - A
dielectric layer 218, such as for example silicon nitride or silicon oxide, is deposited, as shown inFIG. 5D to electrically isolate theITO layer 214 andmirror layer 216, which serve as the n-contact, from the p metal to be deposited in via 217.Dielectric layer 218 may be any material that electrically isolates two materials on either side ofdielectric layer 218.Dielectric layer 218 is patterned to remove a portion of the dielectric material covering thep layer 204 at the bottom of via 217 and a portion of the top of themirror layer 216.Dielectric layer 218 must have a low density of pinholes to prevent short circuiting between the p- and n-contacts. In some embodiments,dielectric layer 218 is multiple dielectric layers. - The
p contact layer 220 is then deposited over thedielectric layer 218 and in via 217. Theinterconnect 222, which connects the p-metal deposited in each via 217, may also be deposited at this time. Thep contact layer 220 is patterned to remove a portion of the material covering themirror layer 216 as shown inFIG. 4 . - Although the present invention is illustrated in connection with specific embodiments for instructional purposes, the present invention is not limited thereto. Various adaptations and modifications may be made without departing from the scope of the invention. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description.
Claims (25)
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US11/860,502 US20080224158A1 (en) | 2004-10-06 | 2007-09-24 | Light Emitting Device With Undoped Substrate And Doped Bonding Layer |
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US10/960,391 US7274040B2 (en) | 2004-10-06 | 2004-10-06 | Contact and omnidirectional reflective mirror for flip chipped light emitting devices |
US11/860,502 US20080224158A1 (en) | 2004-10-06 | 2007-09-24 | Light Emitting Device With Undoped Substrate And Doped Bonding Layer |
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US10/960,391 Continuation US7274040B2 (en) | 2004-10-06 | 2004-10-06 | Contact and omnidirectional reflective mirror for flip chipped light emitting devices |
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US10/960,391 Active US7274040B2 (en) | 2004-10-06 | 2004-10-06 | Contact and omnidirectional reflective mirror for flip chipped light emitting devices |
US11/860,502 Abandoned US20080224158A1 (en) | 2004-10-06 | 2007-09-24 | Light Emitting Device With Undoped Substrate And Doped Bonding Layer |
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EP (1) | EP1646092B1 (en) |
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Also Published As
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US20060071228A1 (en) | 2006-04-06 |
DE602005012207D1 (en) | 2009-02-26 |
EP1646092A3 (en) | 2006-12-06 |
EP1646092A2 (en) | 2006-04-12 |
TW200627676A (en) | 2006-08-01 |
EP1646092B1 (en) | 2009-01-07 |
US7274040B2 (en) | 2007-09-25 |
JP2006108698A (en) | 2006-04-20 |
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