US20080017909A1 - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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Publication number
US20080017909A1
US20080017909A1 US11/647,837 US64783706A US2008017909A1 US 20080017909 A1 US20080017909 A1 US 20080017909A1 US 64783706 A US64783706 A US 64783706A US 2008017909 A1 US2008017909 A1 US 2008017909A1
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well
region
semiconductor substrate
predetermined
impurity
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US11/647,837
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Wan Shin
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SK Hynix Inc
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Hynix Semiconductor Inc
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Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SHIN, WAN CHEUL
Publication of US20080017909A1 publication Critical patent/US20080017909A1/en
Priority to US12/546,064 priority Critical patent/US8222148B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

Definitions

  • the invention relates in general to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device and a method of manufacturing the same, wherein leakage current occurring due to a parasitic bipolar transistor by a triple well structure at the time of erasure can be prevented.
  • An NAND flash memory device performs data program by injecting electrons into the floating gate by Fowler-Nordheim (FN) tunneling.
  • FN Fowler-Nordheim
  • the NAND flash memory device provides a large capacity and a high level of integration.
  • the NAND flash memory device includes a number of cell blocks.
  • Each cell block includes a number of cell strings in which a number of cells for storing data are connected in series to form one string, and a drain select transistor and a source select transistor formed between the cell string and the drain, and the cell string and the source, respectively.
  • Each cell block further includes a peri region in which a number of circuit elements for generating a predetermined bias for the program, erasure, and read operations of a cell and transferring the bias are formed.
  • drain select transistors are commonly connected to a drain select line (DSL) and are driven by the potential of the drain select line.
  • DSL drain select line
  • source select transistors are commonly connected to a source select line and are driven by the potential of the source select line.
  • the NAND flash memory cell includes a gate in which a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate are laminated in a predetermined region of a semiconductor substrate, and a junction formed on the semiconductor substrate at both sides of the gate.
  • a NAND flash memory device constructed as described above is an electrically programmable and erasable device, and it performs program and erase functions in such a manner that electrons vary the threshold voltage while being moved due to a strong electric field through a thin tunnel oxide layer.
  • the NAND flash memory device implements erasure on a block basis. For the purpose of erasure, it is necessary that a ground voltage (Vss) be applied to the entire word lines of a selected cell block and a high voltage of about 20 V be applied to the well.
  • Vss ground voltage
  • the NAND flash memory device performs the erasure operation by applying a high voltage typically of about 20 V, to the well.
  • the semiconductor substrate of the cell region must have a triple well structure. That is, an N well is formed on a P-type semiconductor substrate and a P well is formed on an N well, thereby forming the triple well structure.
  • a parasitic bipolar transistor is formed between the semiconductor substrate, the N well, and the P well.
  • the parasitic bipolar transistor keeps turned off with a high voltage not being applied to the well. However, if a high voltage of about 20 V is applied to the well for erasure, the parasitic bipolar transistor is turned on and the leakage current is generated accordingly. More particularly, a great amount of leakage current is generated at the boundary of the cell region and the peri region. The leakage current causes to drop an erase voltage, resulting in the failure of the erase operation.
  • the invention relates to a semiconductor device and a method of manufacturing the same, wherein drop of an erase voltage, which is incurred by the leakage current between the cell region and the peri region due to the parasitic bipolar transistor at the time of erasure can be prevented.
  • the semiconductor substrate of the cell region has multiple wells of triple or more wells. More particularly, the P well is further formed in the N well, forming the well of a PNPN structure. If so, a breakdown voltage can be increased compared with an existing PNP structure, the leakage current can be reduced, and the drop of an erase voltage can be prevented.
  • a semiconductor device includes a first well formed in a predetermined region of a semiconductor substrate, a second well formed in a predetermined region within the first well, and a third well formed within the first well with the third well being spaced apart from the second well at a predetermined distance.
  • the first well may preferably be formed using an N-type impurity
  • the second well and the third well may preferably be formed using a P-type impurity.
  • the invention provides a method of manufacturing a semiconductor device, including the steps of injecting a predetermined impurity ion into a predetermined region of a semiconductor substrate, forming a first well, etching a predetermined region of the semiconductor substrate in which the first well is formed, forming a trench, gap-filling the trench with a polysilicon layer, forming an impurity region in a predetermined region within the first well so that the impurity region is connected to the polysilicon layer, forming a second well including the polysilicon layer and the impurity region, and performing a predetermined impurity ion implantation process to form a third well in a predetermined region within the first well so that the third well is spaced apart from the second well at a predetermined distance.
  • the first well may preferably be formed by injecting an N-type impurity.
  • the method may preferably further include the step of performing an annealing process after the trench is formed.
  • the annealing process may preferably be performed under a nitrogen atmosphere.
  • the annealing process may preferably be performed at a temperature of 850° C. to 100° C. for 30 minutes to 60 minutes.
  • the polysilicon layer may preferably be doped with a P-type impurity.
  • the impurity region may preferably be formed by injecting a P-type impurity and then performing an nitrogen annealing process so that the impurity region is connected to the bottom of the polysilicon layer.
  • the third well may preferably be formed by injecting a P-type impurity.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the invention.
  • FIGS. 2A to 2 E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the invention.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the invention.
  • An N-type first well 20 is formed on a P-type semiconductor substrate 10 .
  • a P-type second well 30 is formed within the first well 20 .
  • a P-type third well 40 is formed within the first well 20 with the first well 20 being intervened between the P-type third well 40 and the second well 30 . Accordingly, a multiple well structure of the semiconductor substrate 10 , the first well 20 , the second well 30 , the first well 20 , and the third well 40 , which are sequentially disposed, is formed.
  • FIGS. 2A to 2 E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the invention.
  • a first photoresist layer (not shown) is formed on a semiconductor substrate 11 .
  • the first photoresist layer (not shown) is patterned by photolithography and development processes employing a mask through which a predetermined region (for example, a cell region) of the semiconductor substrate 11 is exposed. Accordingly, the semiconductor substrate 11 of the cell region is exposed.
  • N-type impurity for example, phosphorous (P) ion
  • P phosphorous
  • an oxide layer 13 and a nitride layer 14 are formed on the semiconductor substrate 11 on which the first well 12 is formed.
  • a second photoresist layer (not shown) is formed on the nitride layer 14 .
  • the second photoresist layer (not shown) is patterned by photolithography and development processes using a predetermined mask.
  • the second photoresist layer causes the nitride layer 14 of a location at which the first well 12 is formed to be exposed such that a predetermined region of the semiconductor substrate 11 on which the first well 12 is formed is etched in a subsequent etch process.
  • the nitride layer 14 and the oxide layer 13 are etched using the patterned second photoresist layer (not shown) as a mask.
  • the semiconductor substrate 11 on which the first well 12 is formed is etched to predetermined width and depth, thus forming a trench 15 .
  • an annealing process for removing dangling bonds of silicon is implemented.
  • the annealing process may preferably be performed at a temperature of 850° C. to 1100° C. under a nitrogen atmosphere for 30 minutes to one hour.
  • a polysilicon layer 16 is formed on the entire surface so that the trench 15 is gap filled.
  • the polysilicon layer 16 may be one doped with a P-type ion (for example, boron (B) ion) having a concentration of 10E17 ions/cm 3 to 10E20 ions/cm 3 .
  • the oxide layer 13 , the nitride layer 14 , and the polysilicon layer 16 remaining on the semiconductor substrate 11 are stripped.
  • the nitride layer 14 may be stripped using any suitable means, such as phosphoric acid (H 3 PO 4 ) and the oxide layer 13 may be stripped using HF, for example.
  • a third photoresist layer (not shown) is formed on the entire surface, it is patterned by photolithography and development processes using a predetermined mask.
  • the third photoresist layer (not shown) is patterned such that the first well 12 within the trench 15 in which the polysilicon layer 16 is formed is exposed.
  • a P-type ion (preferably, the same ion (for example, boron (B) ion) as that doped into the polysilicon layer 16 ) is injected with energy of 200 to 500 keV and dose of 1.0E12 ions/cm 2 to 5.0E14 ions/cm 2 .
  • An annealing process is then performed to form an impurity region 17 within the first well 12 .
  • the annealing process may preferably be performed at a temperature of 850° C. to 1100° C. under a nitrogen atmosphere for 30 minutes to one hour.
  • the impurity region 17 is connected to the bottom of the polysilicon layer 16 . Accordingly, the polysilicon layer 16 and the impurity region 17 constitutes a P-type second well 18 and the first well 12 is divided by the P-type second well 18 .
  • a fourth photoresist layer (not shown) is formed on the entire surface.
  • the fourth photoresist layer (not shown) is patterned by photolithography and development processes using a predetermined mask.
  • the fourth photoresist layer (not shown) is patterned so that a predetermined region of the first well 12 is exposed with it being apart spaced from the second well 18 at a predetermined distance.
  • a P-type impurity for example, boron (B) ion
  • B boron
  • the semiconductor substrate is formed to have a multiple well structure of triple or more. Accordingly, a breakdown voltage can be increased and a leakage current can be reduced. It is therefore possible to prevent the drop of an erase voltage and to reduce the error of an erase operation.

Abstract

A semiconductor device and a method of manufacturing the same. The semiconductor device includes a first well formed in a predetermined region of a semiconductor substrate, a second well formed in a predetermined region within the first well, and a third well formed within the first well with the third well being spaced apart from the second well at a predetermined distance. A multiple well of the semiconductor substrate, the first well, the second well, the first well, and the third well, which are sequentially disposed, is formed. Accordingly, a breakdown voltage can be increased and a leakage current can be reduced. It is therefore possible to prevent the drop of an erase voltage and to reduce the error of an erase operation.

Description

    BACKGROUND
  • 1. Field of the Invention
  • The invention relates in general to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device and a method of manufacturing the same, wherein leakage current occurring due to a parasitic bipolar transistor by a triple well structure at the time of erasure can be prevented.
  • 2. Discussion of Related Art
  • An NAND flash memory device performs data program by injecting electrons into the floating gate by Fowler-Nordheim (FN) tunneling. The NAND flash memory device provides a large capacity and a high level of integration.
  • The NAND flash memory device includes a number of cell blocks. Each cell block includes a number of cell strings in which a number of cells for storing data are connected in series to form one string, and a drain select transistor and a source select transistor formed between the cell string and the drain, and the cell string and the source, respectively. Each cell block further includes a peri region in which a number of circuit elements for generating a predetermined bias for the program, erasure, and read operations of a cell and transferring the bias are formed.
  • Furthermore, cells that constitute different cell strings and are driven by the same word line (WL) form a page. Gates of a number of drain select transistors are commonly connected to a drain select line (DSL) and are driven by the potential of the drain select line. Gates of a number of source select transistors are commonly connected to a source select line and are driven by the potential of the source select line.
  • The NAND flash memory cell includes a gate in which a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate are laminated in a predetermined region of a semiconductor substrate, and a junction formed on the semiconductor substrate at both sides of the gate.
  • A NAND flash memory device constructed as described above is an electrically programmable and erasable device, and it performs program and erase functions in such a manner that electrons vary the threshold voltage while being moved due to a strong electric field through a thin tunnel oxide layer.
  • The NAND flash memory device implements erasure on a block basis. For the purpose of erasure, it is necessary that a ground voltage (Vss) be applied to the entire word lines of a selected cell block and a high voltage of about 20 V be applied to the well.
  • As described above, the NAND flash memory device performs the erasure operation by applying a high voltage typically of about 20 V, to the well. Accordingly, the semiconductor substrate of the cell region must have a triple well structure. That is, an N well is formed on a P-type semiconductor substrate and a P well is formed on an N well, thereby forming the triple well structure. In this case, a parasitic bipolar transistor is formed between the semiconductor substrate, the N well, and the P well.
  • The parasitic bipolar transistor keeps turned off with a high voltage not being applied to the well. However, if a high voltage of about 20 V is applied to the well for erasure, the parasitic bipolar transistor is turned on and the leakage current is generated accordingly. More particularly, a great amount of leakage current is generated at the boundary of the cell region and the peri region. The leakage current causes to drop an erase voltage, resulting in the failure of the erase operation.
    • SUMMARY OF THE INVENTION
  • In one embodiment, the invention relates to a semiconductor device and a method of manufacturing the same, wherein drop of an erase voltage, which is incurred by the leakage current between the cell region and the peri region due to the parasitic bipolar transistor at the time of erasure can be prevented.
  • The semiconductor substrate of the cell region has multiple wells of triple or more wells. More particularly, the P well is further formed in the N well, forming the well of a PNPN structure. If so, a breakdown voltage can be increased compared with an existing PNP structure, the leakage current can be reduced, and the drop of an erase voltage can be prevented.
  • A semiconductor device according to one aspect of the invention includes a first well formed in a predetermined region of a semiconductor substrate, a second well formed in a predetermined region within the first well, and a third well formed within the first well with the third well being spaced apart from the second well at a predetermined distance. A multiple well of the semiconductor substrate, the first well, the second well, the first well, and the third well, which are sequentially disposed, is formed.
  • The first well may preferably be formed using an N-type impurity, and the second well and the third well may preferably be formed using a P-type impurity.
  • According to another aspect, the invention provides a method of manufacturing a semiconductor device, including the steps of injecting a predetermined impurity ion into a predetermined region of a semiconductor substrate, forming a first well, etching a predetermined region of the semiconductor substrate in which the first well is formed, forming a trench, gap-filling the trench with a polysilicon layer, forming an impurity region in a predetermined region within the first well so that the impurity region is connected to the polysilicon layer, forming a second well including the polysilicon layer and the impurity region, and performing a predetermined impurity ion implantation process to form a third well in a predetermined region within the first well so that the third well is spaced apart from the second well at a predetermined distance.
  • The first well may preferably be formed by injecting an N-type impurity.
  • The method may preferably further include the step of performing an annealing process after the trench is formed.
  • The annealing process may preferably be performed under a nitrogen atmosphere.
  • The annealing process may preferably be performed at a temperature of 850° C. to 100° C. for 30 minutes to 60 minutes.
  • The polysilicon layer may preferably be doped with a P-type impurity.
  • The impurity region may preferably be formed by injecting a P-type impurity and then performing an nitrogen annealing process so that the impurity region is connected to the bottom of the polysilicon layer.
  • The third well may preferably be formed by injecting a P-type impurity.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • A more complete appreciation of the invention, and many of the attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:
  • FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the invention; and
  • FIGS. 2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the invention.
    • DETAILED DESCRIPTION OF EMBODIMENTS
  • The invention will now be described in detail in connection with certain exemplary embodiments with reference to the accompanying drawings.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the invention.
  • An N-type first well 20 is formed on a P-type semiconductor substrate 10. A P-type second well 30 is formed within the first well 20. A P-type third well 40 is formed within the first well 20 with the first well 20 being intervened between the P-type third well 40 and the second well 30. Accordingly, a multiple well structure of the semiconductor substrate 10, the first well 20, the second well 30, the first well 20, and the third well 40, which are sequentially disposed, is formed.
  • FIGS. 2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the invention.
  • Referring to FIG. 2A, a first photoresist layer (not shown) is formed on a semiconductor substrate 11. The first photoresist layer (not shown) is patterned by photolithography and development processes employing a mask through which a predetermined region (for example, a cell region) of the semiconductor substrate 11 is exposed. Accordingly, the semiconductor substrate 11 of the cell region is exposed.
  • An N-type impurity (for example, phosphorous (P) ion) is then injected with a predetermined energy and dose to form a first well 12. In other words, the first well 12 is formed by injecting the N-type impurity into the cell region of the semiconductor substrate 11.
  • Referring to FIG. 2B, an oxide layer 13 and a nitride layer 14 are formed on the semiconductor substrate 11 on which the first well 12 is formed. A second photoresist layer (not shown) is formed on the nitride layer 14. The second photoresist layer (not shown) is patterned by photolithography and development processes using a predetermined mask. The second photoresist layer (not shown) causes the nitride layer 14 of a location at which the first well 12 is formed to be exposed such that a predetermined region of the semiconductor substrate 11 on which the first well 12 is formed is etched in a subsequent etch process.
  • The nitride layer 14 and the oxide layer 13 are etched using the patterned second photoresist layer (not shown) as a mask. The semiconductor substrate 11 on which the first well 12 is formed is etched to predetermined width and depth, thus forming a trench 15.
  • Referring to FIG. 2C, after the second photoresist layer (not shown) is stripped, an annealing process for removing dangling bonds of silicon is implemented. The annealing process may preferably be performed at a temperature of 850° C. to 1100° C. under a nitrogen atmosphere for 30 minutes to one hour. A polysilicon layer 16 is formed on the entire surface so that the trench 15 is gap filled. The polysilicon layer 16 may be one doped with a P-type ion (for example, boron (B) ion) having a concentration of 10E17 ions/cm3 to 10E20 ions/cm3.
  • Referring to FIG. 2D, the oxide layer 13, the nitride layer 14, and the polysilicon layer 16 remaining on the semiconductor substrate 11 are stripped. The nitride layer 14 may be stripped using any suitable means, such as phosphoric acid (H3PO4) and the oxide layer 13 may be stripped using HF, for example.
  • After a third photoresist layer (not shown) is formed on the entire surface, it is patterned by photolithography and development processes using a predetermined mask. The third photoresist layer (not shown) is patterned such that the first well 12 within the trench 15 in which the polysilicon layer 16 is formed is exposed.
  • A P-type ion (preferably, the same ion (for example, boron (B) ion) as that doped into the polysilicon layer 16) is injected with energy of 200 to 500 keV and dose of 1.0E12 ions/cm2 to 5.0E14 ions/cm2. An annealing process is then performed to form an impurity region 17 within the first well 12. The annealing process may preferably be performed at a temperature of 850° C. to 1100° C. under a nitrogen atmosphere for 30 minutes to one hour.
  • If so, the impurity region 17 is connected to the bottom of the polysilicon layer 16. Accordingly, the polysilicon layer 16 and the impurity region 17 constitutes a P-type second well 18 and the first well 12 is divided by the P-type second well 18.
  • Referring to FIG. 2E, after the third photoresist layer (not shown) is stripped, a fourth photoresist layer (not shown) is formed on the entire surface. The fourth photoresist layer (not shown) is patterned by photolithography and development processes using a predetermined mask. The fourth photoresist layer (not shown) is patterned so that a predetermined region of the first well 12 is exposed with it being apart spaced from the second well 18 at a predetermined distance.
  • A P-type impurity (for example, boron (B) ion) is injected using the fourth photoresist layer (not shown) as a mask, forming a third well 19. After the fourth photoresist layer (not shown) is stripped, a subsequent process is performed.
  • As described above, in the NAND flash memory device according to the invention, the semiconductor substrate is formed to have a multiple well structure of triple or more. Accordingly, a breakdown voltage can be increased and a leakage current can be reduced. It is therefore possible to prevent the drop of an erase voltage and to reduce the error of an erase operation.
  • While the invention has been described in connection with practical exemplary embodiments, the invention is not limited to the disclosed embodiments but, to the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims (10)

1. A semiconductor device, comprising:
a first well formed in a predetermined region of a semiconductor substrate;
a second well formed in a predetermined region within the first well; and
a third well formed within the first well with the third well being spaced apart from the second well at a predetermined distance,
whereby a multiple well of the semiconductor substrate comprising the sequentially formed the first well and second well, and the sequentially formed first well and third well, is formed.
2. The semiconductor device of claim 1, wherein the first well is formed using an N-type impurity, and the second well and the third well are formed using a P-type impurity.
3. A method of manufacturing a semiconductor device, the method comprising the steps of:
injecting a predetermined impurity ion into a predetermined region of a semiconductor substrate, forming a first well;
etching a predetermined region of the semiconductor substrate in which the first well is formed, forming a trench;
gap-filling the trench with a polysilicon layer;
forming an impurity region in a predetermined region within the first well so that the impurity region is connected to the polysilicon layer, forming a second well comprising the polysilicon layer and the impurity region; and
performing a predetermined impurity ion implantation process to form a third well in a predetermined region within the first well so that the third well is spaced apart from the second well at a predetermined distance.
4. The method of claim 3, comprising forming the first well by injecting an N-type impurity.
5. The method of claim 3, further comprising the step of performing an annealing process after forming the trench.
6. The method of claim 5, comprising performing the annealing process under a nitrogen atmosphere.
7. The method of claim 5, comprising performing the annealing process at a temperature of 850° C. to 1100° C. for 30 minutes to 60 minutes.
8. The method of claim 3, comprising doping the polysilicon layer with a P-type impurity.
9. The method of claim 3, comprising forming the impurity region is formed by injecting a P-type impurity and then performing an nitrogen annealing process so that the impurity region is connected to the bottom of the polysilicon layer.
10. The method of claim 3, comprising forming the third well by injecting a P-type impurity.
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CN100547798C (en) 2009-10-07
KR100685620B1 (en) 2007-02-22

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