US20070292989A1 - Semiconductor device and a method of assembling a semiconductor device - Google Patents
Semiconductor device and a method of assembling a semiconductor device Download PDFInfo
- Publication number
- US20070292989A1 US20070292989A1 US11/826,858 US82685807A US2007292989A1 US 20070292989 A1 US20070292989 A1 US 20070292989A1 US 82685807 A US82685807 A US 82685807A US 2007292989 A1 US2007292989 A1 US 2007292989A1
- Authority
- US
- United States
- Prior art keywords
- substrate
- layer
- semiconductor chip
- joints
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
Definitions
- the present invention relates to a semiconductor device, more specifically to a semiconductor device having a plurality of chips stacked so as to implement a three-dimensional (3-D) configuration and a method of assembling the semiconductor device.
- a core board which serves as an intermediate layer, is sandwiched between a lower-layer semiconductor package and an upper-layer semiconductor package. Then, the core board and the lower-layer and upper-layer semiconductor packages are fixed by use of thermo compression.
- the lower-layer and upper-layer semiconductor packages can be connected with a plurality of vias buried in the core board.
- the upper-layer and the lower-layer semiconductor packages are stacked and connected directly with a plurality of bumps without using the intermediate layer.
- the intermediate layer since an alignment between the lower-layer and upper-layer semiconductor packages is difficult, a misalignment between the lower-layer and upper-layer semiconductor packages occurs.
- An aspect of the present invention inheres in a semiconductor device encompassing a base substrate; a first fixing layer provided on the base substrate; a first semiconductor chip fixed on the first fixing layer; a first substrate provided above the first semiconductor chip; a plurality of first connection members isolated from the first semiconductor chip, electrically connecting to the first substrate with the base substrate; and a first encapsulating layer provided around the first connection members.
- Another aspect of the present invention inheres in a method of assembling a semiconductor device encompassing providing a first fixing layer on a base substrate; facing a first substrate to the base substrate, the first substrate attaching a first semiconductor chip under a bottom surface of the first substrate; fixing the first semiconductor chip to the first fixing layer; providing a plurality of first connection members between the first substrate and the base substrate so as to connect the first substrate and the base substrate; and providing a first substrate encapsulating layer around the first connection members.
- FIG. 1A is a plan view viewed from the first substrate of a semiconductor device according to a first embodiment of the present invention
- FIG. 1B is a cross-sectional view taken on line I-I in FIG. 1A according to the first embodiment of the present invention
- FIG. 2 is a cross-sectional view illustrating a method of assembling a semiconductor device according to the first embodiment of the present invention
- FIG. 3 is a cross-sectional view illustrating the method of assembling the semiconductor device according to the first embodiment of the present invention
- FIG. 4 is a cross-sectional view illustrating the semiconductor device according to a modification of the first embodiment of the present invention
- FIG. 5 is a cross-sectional view illustrating a semiconductor device according to a second embodiment of the present invention.
- FIG. 6 is a cross-sectional view illustrating a method of assembling the semiconductor device according to the second embodiment of the present invention.
- FIG. 7 is a cross-sectional view illustrating the method of assembling the semiconductor device according to the second embodiment of the present invention.
- Prepositions such as “on”, “over”, “under”, “beneath” and “normal” are defined with respect to a planar surface of a substrate, regardless of the orientation in which the substrate is actually held. A layer is on another layer even if there are intervening layers.
- a semiconductor device includes a base substrate 1 , a base substrate 1 , a first fixing layer 8 provided on the base substrate 1 , a first semiconductor chip 14 fixed on the first fixing layer 8 , a first substrate 10 provided above the first semiconductor chip 14 .
- a plurality of first connection members (first lower joints 5 c, 5 m, first intermediate joints 6 c, 6 m, first upper joints 7 c, 7 m ) are isolated from the first semiconductor chip 14 and electrically connecting the first substrate 10 with base substrate 1 .
- a first encapsulating layer 9 is provided around the first connection members 5 c, 5 m, 6 c, 6 m, 7 c, and 7 m.
- the base substrate 1 As a material of the base substrate 1 , various organic synthetic resins and inorganic materials including ceramic and glass can be used. Among organic synthetic resins, phenolic resin, polyester resin, epoxy resin, polyimide resin, fluoroplastic can be used. Meanwhile, paper, woven glass fabric, a glass backing material, or the like is used as a backing material that becomes a core in forming a slab-shaped structure. As a general inorganic base material, ceramic can be used. Alternatively, a metal substrate is used in order to improve the heat-radiating characteristics. In the case where a transparent substrate is needed, glass is used.
- alumina (Al 2 O 3 ) mullite (3Al 2 O 3 .2SiO 2 ), beryllia (BeO), aluminum nitride (AlN), silicon nitride (SiN) can be used.
- a lead frame in which a polyimide resin plate having high thermal resistance is laminated onto metal, such as iron or copper, can be used.
- the first fixing layer 8 has an outer contour aligned with a contour of the first semiconductor chip 14 .
- the first fixing layer 8 is positioned on an area of the base substrate 1 where the first semiconductor chip 14 is mounted.
- the first fixing layer 8 is adhered to the bottom surface of the first semiconductor chip 14 .
- a synthetic resin made of epoxy resin or acrylic resin can be used as a material of the first fixing layer 8 .
- the synthetic resin includes a liquid resin and a resin sheet (film).
- the resin sheet may be suitable because the resin sheet is easier to handle and can control thickness and shape of the resin compared to the case where the liquid resin is used.
- a plurality of circuit elements is formed on a top surface of the first semiconductor chip 14 .
- the circuit elements include heavily doped impurity regions doped with donors or acceptors of approximately 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 (such as source regions and drain regions or emitter regions and collector regions) or the like.
- Insulating films are stacked into a multi-level structure on the circuit elements.
- Metallic interconnections made of aluminum (Al) aluminum alloy (Al—Si or Al—Cu—Si) or the like are alternatively stacked into the insulating films so as to connect the circuit elements.
- bonding pads are formed on the uppermost layer of the insulating films.
- First chip connection electrodes 13 a, 13 b, 13 c, and 13 d are connected to the bonding pads.
- Materials and concrete shapes of the first chip connection electrodes 13 a, 13 b, 13 c, and 13 d are not limited.
- the first chip connection electrodes 13 a, 13 b, 13 c, and 13 c may be made of solder balls or gold stud bumps.
- the first chip connection electrodes 13 a, 13 b, 13 c, and 13 d are connected to wirings (not shown), which are provided on the bottom surface of the first substrate 10 .
- the first semiconductor chip 14 is mounted in a face down configuration on the first substrate 10 with flip chip connection.
- a first chip covering layer 12 is provided around the first chip connection electrodes 13 a, 13 b, 13 c, and 13 d.
- a synthetic resin made of epoxy resin or acrylic resin can be used as a material of the first chip covering layer 12 .
- Both of the resin sheet and liquid resin can be used as the first chip covering layer 12 .
- FIG. 1B illustrates the flip-chip bonding device.
- the first semiconductor chip 14 can be mounted with bonding wires in place of solder balls or stud bumps.
- the first substrate 10 can be made from polyimide or glass epoxy and has a thickness of about 0.15 mm.
- a plurality of via plugs 11 c, 11 m, . . . are buried in the first substrate 10 .
- the via plugs 11 c, 11 m, . . . penetrate through the top surface and bottom surface of the first substrate 10 .
- the via plugs 11 c, 11 m, . . . are provided so as to surround the first semiconductor chip 14 .
- the first connection members (the first upper joint 7 c, the first intermediate joint 6 c, and the first lower joint 5 c ) are connected under the via plug 11 c.
- the first lower joint 5 c is connected to a wiring (not shown), which is provided on the base substrate 1 .
- the first connection members (the first upper joint 7 m, the first intermediate joint 6 m, and the first lower joint 5 m ) are connected under the via plug 11 m.
- the first lower joint 5 m is connected to a wiring (not shown), which is provided on the base substrate 1 .
- solder As materials of the first upper joints 7 c, 7 m, the first intermediate joints 6 c, 6 m, the first lower joints 5 c, 5 m, ball electrodes made of solder (Pb) can be suitable. Alloys made of Tin-Copper (Sn—Cu), Tin-Silver (Sn—Ag), Tin-Silver-Copper. (Sn—Ag—Cu) or Tin-Antimony (Sn—Sb) can also be used as the first connection members 5 c, 5 m, 6 c, 6 m, 7 c, and 7 m.
- the first encapsulating layer 9 encapsulates the first upper joint 7 c, 7 m, the first intermediate joint 6 c, 6 m, and the first lower joint 5 c, 5 m.
- a synthetic resin made of epoxy resin or acrylic resin can be used as a material of the first encapsulating layer 9 .
- the liquid resin such as a reactive liquid resin with a solder fluxing function for soldering interconnect (a non-flow underfill) may be used as the first encapsulating layer 9 .
- the first encapsulating layer 9 , the first fixing layer 8 , and the first chip covering layer 12 may be made of the same material considering the decrease of the reliability by peeling and adhesion strength between the interfaces of layers.
- the first fixing layer 8 is provided under the first semiconductor chip 14 . Therefore, the misalignment can be suppressed when the first lower joints 5 c, 5 m, the first intermediate joints 6 c, 6 m, and the first upper joints 7 c, 7 m are provided between the base substrate 1 and the first substrate 10 .
- the misalignment caused by the flowage of the first encapsulating layer 9 during assembling the first substrate 10 on the base substrate 1 can also be suppressed. Accordingly, the semiconductor device according to the first embodiment can be assembled with high accuracy.
- FIGS. 2 and 3 A method of assembling a semiconductor device according to the first embodiment of the present invention is described by using FIGS. 2 and 3 .
- the base substrate from a resin such, as glass epoxy, polyimide or the like is prepared.
- the first lower joints 5 c, 5 m are provided on the base substrate 1 , respectively.
- the first intermediate joints 6 c, 6 m are provided on the first lower joints 5 c, 5 m, respectively.
- the first upper joints 7 c, 7 m are provided on the first intermediate joints. 6 c, 6 m, respectively.
- the first lower joints 5 c, 5 m, the first intermediate joints 6 c, 6 m, and the first upper joints 7 c, 7 m may be provided by use of a ball mounter.
- the first fixing layer 8 is positioned on the area of the base substrate 1 where the first semiconductor chip 14 is mounted.
- the resin sheet made from epoxy resin or acrylic resin may be suitable.
- the first fixing layer 8 is patterned to have an outer contour aligned with a contour of the first semiconductor chip 14 .
- the first substrate 10 having the via plugs 11 c, 11 m, . . . penetrating through the top and bottom surfaces of the first substrate 10 is prepared.
- the first semiconductor chip 14 is mounted on the bottom surface of the first substrate 10 through the first chip connection electrodes 13 a, 13 b, 13 c, and 13 d.
- the first chip covering layer 12 is provided around the first chip connection electrodes 13 a, 13 b, 13 c, and 13 d.
- the bottom surface of the first substrate 10 is faced to the base substrate 1 .
- the first semiconductor chip 14 is adhered to the first fixing layer 8 .
- the first semiconductor chip 14 is fixed on the base substrate 1 by melting and curing the first fixing layer 8 .
- the base substrate 1 and the first substrate 10 is connected by reflowing the first lower joints 5 c, 5 m, the first intermediate joints 6 c, 6 m, and the first upper joints 7 c, 7 m.
- the first substrate encapsulating layer 9 is filled around the first lower joints 5 c, 5 m, the first intermediate joints 6 c, 6 m, and the first upper joints 7 c, 7 m, by vacuum printing, molding, potting, or the like.
- the first substrate encapsulating layer 9 is cured and the semiconductor device. Then, the semiconductor device as shown in FIGS. 1A and 1B is manufactured.
- the first lower joints 5 c, 5 m, the first intermediate joints 6 c, 6 m, and the first upper joints 7 c, 7 m may be connected during filling the first encapsulating layer simultaneously.
- the first semiconductor chip 14 is first fixed when assembling the first substrate 10 on the base substrate 1 . And then, the first semiconductor chip 14 provided between the base substrate 1 and the first substrate 10 is encapsulated by use of the first encapsulating layer 9 . Accordingly, the misalignment of the base substrate 1 and the first substrate 10 caused by the flowage of the first encapsulating layer 9 is suppressed and the semiconductor device assembled with high accuracy will be manufactured. Moreover, since the first substrate 10 is mounted directly on the base substrate with the first lower joints 5 c, 5 m, the intermediate layer, which connects upper and lower boards, is unnecessary. Accordingly, the manufacturing process will be simplified at a low cost.
- a semiconductor device differs from the semiconductor device as shown in FIGS. 1A and 1B in that first lower connection bumps 105 c, 105 m, first intermediate connection bumps 106 c, 106 m, and first upper connection bumps 107 c, 107 m are provided between the base substrate 1 and the first substrate 10 .
- first lower connection bumps 105 c, 105 m, the first intermediate connection bumps 106 c, 106 m, and the first upper connection bumps 107 c, 107 m metallic stud bump electrode made of gold, or the like, may be suitable.
- the base substrate 1 and the first substrate 10 are connected by applying physical oscillation, such as supersonic wave, to the first intermediate connection bumps 106 c, 106 m, and the first upper connection bumps 107 c, 107 m.
- the misalignment of the base substrate 1 and the first substrate 10 caused by the flowage of the first encapsulating layer 9 is suppressed and the semiconductor device assembled with high accuracy will be manufactured.
- the first substrate 10 is mounted directly on the base substrate with the first lower connection bumps 105 c, 105 m, the intermediate layer, which connects upper and lower boards, is unnecessary. Accordingly, the manufacturing process will be simplified at a low cost.
- a semiconductor device differs from the semiconductor device as shown in FIGS. 1A and 1B in that a plurality of semiconductor chips (a second semiconductor chip 24 , . . . , a k-th semiconductor chip 54 ) is stacked on the first substrate 10 .
- the second semiconductor chip 24 is provided on the first substrate 10 through a second fixing layer 28 .
- a synthetic resin sheet made of epoxy resin or acrylic resin may be used.
- the second semiconductor chip 24 is connected to wirings (not shown) provided on a bottom surface of the second substrate 20 through second chip connection electrodes 23 a, 23 b, 23 c, and 23 d, which are connected to the element surface of the semiconductor chip 24 .
- a plurality of via plugs 21 c, 21 m, . . . are buried in the second substrate 20 .
- the via plugs 21 c, 21 m, . . . penetrate through the top surface and bottom surface of the second substrate 10 .
- a plurality of second connection members (second lower joints 15 c, 15 m, second intermediate joints 16 c, 16 m, and second upper joints 17 c, 17 m ) are provided between the via plugs 21 c, 21 m and the via plugs 11 c, 11 m.
- the first substrate 10 and the second substrate 20 are electrically connected by the second lower joints 15 c, 15 m, the second intermediate joints 16 c, 16 m, and the second upper joints 17 c, 17 m.
- a second encapsulating layer 29 is provided around the second lower joints 15 c, 15 m, the second intermediate joints 16 c, 16 m, and the second upper joints 17 c, 17 m.
- a synthetic liquid resin made from epoxy resin or acrylic resin may be suitable.
- the k-th semiconductor chip 54 is fixed on a k-1 the substrate 40 , which is provided above the second substrate 20 , through a k-th fixing layer 48 .
- the k-th semiconductor chip 54 is connected to wirings (not shown) provided on a bottom surface of the k-th substrate 50 , which is the uppermost substrate of the semiconductor device as shown in FIG. 5 , through k-th chip connection electrodes 53 a, 53 b, 53 c, and 53 d connected to the element surface of the k-th semiconductor chip 54 .
- a k-th chip covering layer 52 is provided around the k-th chip connection electrodes 53 a, 53 b, 53 c, and 53 d.
- a plurality of via plugs 51 c, 51 m are buried in the k-th substrate 50 .
- the via plugs 51 c, 51 m penetrates through the top surface and bottom surface of k-th substrate 50 .
- a plurality of second connection members (k-th lower joints 45 c, 45 m, k-th intermediate joints 46 c, 46 m, and k-th upper joints 47 c, 47 m ) are provided between the via plugs 51 c, 51 m and via plugs 41 c, 41 m, buried in the k-1th substrate 40 .
- the first to k-th fixing layer 8 , 28 , . . . , 48 are provided on the base substrate 1 , and the first to k-1th substrate 10 , . . . , 40 , respectively. Since each of the first to k-th semiconductor chips 14 , 24 , . . . , 54 is fixed on the first to k-th fixing layer 8 , 28 , . . . , 24 , respectively, before filling the first to k-th encapsulating layers 9 , 29 , . . .
- the semiconductor device according to the second embodiment can be assembled with high accuracy.
- FIGS. 2, 6 and 7 A method of assembling a semiconductor device according to the second embodiment of the present invention is described by using FIGS. 2, 6 and 7 .
- the base substrate from a resin such, as glass epoxy, polyimide or the like is prepared.
- the first lower joints 5 c, 5 m are provided on the base substrate 1 .
- the first intermediate joints 6 c, 6 m are provided on the first lower joints 5 c, 5 m.
- the first upper joints 7 c, 7 m are provided on the first intermediate joints 6 c, 6 m.
- the first lower joints 5 c, 5 m, the first intermediate joints 6 c, 6 m, and the first upper joints 7 c, 7 m may be provided by use of the ball mounter.
- the first fixing layer 8 is positioned on the area opposing to the first semiconductor chip 14 on the base substrate 1 .
- the first substrate 10 having the first semiconductor chip 14 on the bottom surface is prepared and the bottom surface of the first substrate 10 is faced to the base substrate 1 .
- the first semiconductor chip 14 is adhered to the first fixing layer 8 .
- the first semiconductor chip 14 is fixed on the base substrate 1 by melting and curing the first fixing layer 8 .
- second fixing layer 28 is positioned on the area opposing to the second semiconductor chip 24 on the first substrate 10 .
- the second fixing layer 28 is patterned to have an outer contour aligned with a contour of the second semiconductor chip 24 .
- a synthetic resin sheet made of epoxy resin or acrylic resin may be suitable.
- the second substrate 20 having the second semiconductor chip 24 on the bottom surface is faced to the base substrate 1 .
- the second semiconductor chip 24 is adhered to the second fixing layer 28 .
- the first semiconductor chip 24 is fixed on the first substrate 10 by melting and curing the second fixing layer 28 .
- the k-th fixing layer 48 is provided on the top surface of the k-1 the substrate 40 .
- the k-th substrate 50 which is the uppermost substrate of the semiconductor device in FIG. 5 , is faced to the k-th fixing layer 48 .
- the bottom surface of the k-th semiconductor chip 54 is adhered to the k-th fixatiom layer 48 .
- the k-th semiconductor chip 54 is fixed on the k-1th substrate 40 by melting and curing the k-the fixing layer 48 .
- the base substrate 1 and the first substrate 10 is connected by reflowing the first lower joints 5 c, 5 m, the first intermediate joints 6 c, 6 m, and the first upper joints 7 c, 7 m.
- the first substrate 10 and the second substrate 20 is connected by reflowing the second lower joints 15 c, 15 m, the second intermediate joints 16 c, 16 m, and the second upper joints 17 c, 17 m.
- connection members stacked above the second substrate 20 are connected by reflowing, and finally, the k-1 the substrate 40 and the k-th substrate 50 are connected by reflowing the k-th lower joints 45 c, 45 m, the k-th intermediate joints 46 c, 46 m, and the k-th upper joints 47 c, 47 m.
- the second substrate encapsulating layer 29 is filled around the second lower joints 15 c, 15 m, the second intermediate joints 16 c, 16 m, and the second upper joints 17 c, 17 m, by vacuum printing, molding, potting, or the like.
- the k-th substrate encapsulating layer 59 is filled around the k-th lower joints 45 c, 45 m, the k-th intermediate joints 46 c, 46 m, and the k-th upper joints 47 c, 47 m, by vacuum printing, molding, potting, or the like. Accordingly, the semiconductor device as shown in FIG. 5 is manufactured.
- the first to k-th semiconductor chips 14 , 24 , . . . , 54 are first fixed on the base substrate 1 and the first to k-th substrates 10 , 20 , . . . , 50 , respectively. Then the first to k-th semiconductor chips 14 , 24 , . . . , 54 are encapsulated by the first to k-th encapsulating layers 9 , 29 , . . . , 59 . Therefore, the misalignments of the base substrate 1 , the first to k-th substrates 10 , 20 , . . .
- the semiconductor device assembled with high accuracy will be manufactured.
- the first to k-th substrates 10 , 20 , . . . , 50 are mounted directly on the base substrate 1 with the first to k-the lower joints 5 c, 5 m, 15 c, 15 m, 45 c, 45 m, the intermediate layers, which connects upper and lower substrates, are unnecessary. Accordingly, the manufacturing process will be simplified at a low cost.
- synthetic resins such as polyimide resin, phonolic resin can be used as the material of the encapsulating resin layers in place of the epoxy resin and the acrylic resin.
- synthetic resins such as polyimide resin, phonolic resin
- the base substrate 1 and the first substrate 10 are connected with the three connection members (the first lower joints 5 c, 5 m, the first intermediate joints 6 c, 6 m, and the first upper joints 7 c, 7 m ).
- the number of the connection members is acceptable even by one.
- FIG. 2 shows an assembling example, which provides the first connection members (the lower joints 5 c, 5 m, the first intermediate joints 6 c, 6 m, and the first upper joints 7 c, 7 m ) on the base substrate 1 .
- the first connection members can be stacked on predetermined area on the first substrate 10 .
Abstract
A semiconductor device includes a base substrate; a first fixing layer provided on the base substrate; a first semiconductor chip fixed on the first fixing layer; a first substrate provided above the first semiconductor chip; a plurality of first connection members isolated from the first semiconductor chip, electrically connecting to the first substrate with the base substrate; and a first encapsulating layer provided around the first connection members.
Description
- This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. P2004-298740, filed on Oct. 13, 2004; the entire contents of which are incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a semiconductor device, more specifically to a semiconductor device having a plurality of chips stacked so as to implement a three-dimensional (3-D) configuration and a method of assembling the semiconductor device.
- 2. Description of the Related Art
- With movement toward higher levels of integration and improved functions of electric devices in recent years, various assembling methods for 3-D chip stacking technology have been developed.
- As a commonly used method for assembling a semiconductor device, a core board, which serves as an intermediate layer, is sandwiched between a lower-layer semiconductor package and an upper-layer semiconductor package. Then, the core board and the lower-layer and upper-layer semiconductor packages are fixed by use of thermo compression. The lower-layer and upper-layer semiconductor packages can be connected with a plurality of vias buried in the core board.
- To improve electrical connection between the upper-layer and lower-layer semiconductor packages, a fluctuation of the height of the vias buried in the core board have to be suppressed. However, since the vias are formed by plating, a number of platings have to be processed to control the height of vias. This as a result, complicates manufacturing process and decreases manufacturability.
- As another assembling method for the semiconductor device, the upper-layer and the lower-layer semiconductor packages are stacked and connected directly with a plurality of bumps without using the intermediate layer. However, since an alignment between the lower-layer and upper-layer semiconductor packages is difficult, a misalignment between the lower-layer and upper-layer semiconductor packages occurs.
- An aspect of the present invention inheres in a semiconductor device encompassing a base substrate; a first fixing layer provided on the base substrate; a first semiconductor chip fixed on the first fixing layer; a first substrate provided above the first semiconductor chip; a plurality of first connection members isolated from the first semiconductor chip, electrically connecting to the first substrate with the base substrate; and a first encapsulating layer provided around the first connection members.
- Another aspect of the present invention inheres in a method of assembling a semiconductor device encompassing providing a first fixing layer on a base substrate; facing a first substrate to the base substrate, the first substrate attaching a first semiconductor chip under a bottom surface of the first substrate; fixing the first semiconductor chip to the first fixing layer; providing a plurality of first connection members between the first substrate and the base substrate so as to connect the first substrate and the base substrate; and providing a first substrate encapsulating layer around the first connection members.
-
FIG. 1A is a plan view viewed from the first substrate of a semiconductor device according to a first embodiment of the present invention; -
FIG. 1B is a cross-sectional view taken on line I-I inFIG. 1A according to the first embodiment of the present invention; -
FIG. 2 is a cross-sectional view illustrating a method of assembling a semiconductor device according to the first embodiment of the present invention; -
FIG. 3 is a cross-sectional view illustrating the method of assembling the semiconductor device according to the first embodiment of the present invention; -
FIG. 4 is a cross-sectional view illustrating the semiconductor device according to a modification of the first embodiment of the present invention; -
FIG. 5 is a cross-sectional view illustrating a semiconductor device according to a second embodiment of the present invention; -
FIG. 6 is a cross-sectional view illustrating a method of assembling the semiconductor device according to the second embodiment of the present invention; and -
FIG. 7 is a cross-sectional view illustrating the method of assembling the semiconductor device according to the second embodiment of the present invention. - Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified. In the following descriptions, numerous details are set forth such as specific signal values, etc. to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details.
- Prepositions, such as “on”, “over”, “under”, “beneath” and “normal” are defined with respect to a planar surface of a substrate, regardless of the orientation in which the substrate is actually held. A layer is on another layer even if there are intervening layers.
- As shown in
FIGS. 1A and 1B , a semiconductor device according to the first embodiment of the present invention includes abase substrate 1, abase substrate 1, afirst fixing layer 8 provided on thebase substrate 1, afirst semiconductor chip 14 fixed on thefirst fixing layer 8, afirst substrate 10 provided above thefirst semiconductor chip 14. A plurality of first connection members (firstlower joints intermediate joints upper joints first semiconductor chip 14 and electrically connecting thefirst substrate 10 withbase substrate 1. A first encapsulatinglayer 9 is provided around thefirst connection members - As a material of the
base substrate 1, various organic synthetic resins and inorganic materials including ceramic and glass can be used. Among organic synthetic resins, phenolic resin, polyester resin, epoxy resin, polyimide resin, fluoroplastic can be used. Meanwhile, paper, woven glass fabric, a glass backing material, or the like is used as a backing material that becomes a core in forming a slab-shaped structure. As a general inorganic base material, ceramic can be used. Alternatively, a metal substrate is used in order to improve the heat-radiating characteristics. In the case where a transparent substrate is needed, glass is used. As a ceramic substrate, alumina (Al2O3) mullite (3Al2O3.2SiO2), beryllia (BeO), aluminum nitride (AlN), silicon nitride (SiN) can be used. Furthermore, a lead frame in which a polyimide resin plate having high thermal resistance is laminated onto metal, such as iron or copper, can be used. - The
first fixing layer 8 has an outer contour aligned with a contour of thefirst semiconductor chip 14. Thefirst fixing layer 8 is positioned on an area of thebase substrate 1 where thefirst semiconductor chip 14 is mounted. Thefirst fixing layer 8 is adhered to the bottom surface of thefirst semiconductor chip 14. As a material of thefirst fixing layer 8, a synthetic resin made of epoxy resin or acrylic resin can be used. The synthetic resin includes a liquid resin and a resin sheet (film). As a material for the first fixing layer ofFIG. 1B , the resin sheet may be suitable because the resin sheet is easier to handle and can control thickness and shape of the resin compared to the case where the liquid resin is used. - A plurality of circuit elements (not shown) is formed on a top surface of the
first semiconductor chip 14. For example, the circuit elements include heavily doped impurity regions doped with donors or acceptors of approximately 1×1018 cm−3 to 1×1021 cm−3 (such as source regions and drain regions or emitter regions and collector regions) or the like. Insulating films are stacked into a multi-level structure on the circuit elements. Metallic interconnections made of aluminum (Al) aluminum alloy (Al—Si or Al—Cu—Si) or the like are alternatively stacked into the insulating films so as to connect the circuit elements. On the uppermost layer of the insulating films, bonding pads (not shown) are formed. - First
chip connection electrodes chip connection electrodes chip connection electrodes - The first
chip connection electrodes first substrate 10. Thefirst semiconductor chip 14 is mounted in a face down configuration on thefirst substrate 10 with flip chip connection. A firstchip covering layer 12 is provided around the firstchip connection electrodes chip covering layer 12, a synthetic resin made of epoxy resin or acrylic resin can be used. Both of the resin sheet and liquid resin can be used as the firstchip covering layer 12. Herein,FIG. 1B illustrates the flip-chip bonding device. However, thefirst semiconductor chip 14 can be mounted with bonding wires in place of solder balls or stud bumps. - The
first substrate 10 can be made from polyimide or glass epoxy and has a thickness of about 0.15 mm. A plurality of viaplugs first substrate 10. As shown inFIG. 1B , the via plugs 11 c, 11 m, . . . penetrate through the top surface and bottom surface of thefirst substrate 10. As shown inFIG. 1A , the via plugs 11 c, 11 m, . . . are provided so as to surround thefirst semiconductor chip 14. The first connection members (the first upper joint 7 c, the first intermediate joint 6 c, and the first lower joint 5 c) are connected under the viaplug 11 c. The first lower joint 5 c is connected to a wiring (not shown), which is provided on thebase substrate 1. - The first connection members (the first upper joint 7 m, the first intermediate joint 6 m, and the first lower joint 5 m) are connected under the via
plug 11 m. The first lower joint 5 m is connected to a wiring (not shown), which is provided on thebase substrate 1. - As materials of the first
upper joints intermediate joints lower joints first connection members - The
first encapsulating layer 9 encapsulates the first upper joint 7 c, 7 m, the first intermediate joint 6 c, 6 m, and the first lower joint 5 c, 5 m. As a material of thefirst encapsulating layer 9, a synthetic resin made of epoxy resin or acrylic resin can be used. The liquid resin, such as a reactive liquid resin with a solder fluxing function for soldering interconnect (a non-flow underfill) may be used as thefirst encapsulating layer 9. Thefirst encapsulating layer 9, thefirst fixing layer 8, and the firstchip covering layer 12 may be made of the same material considering the decrease of the reliability by peeling and adhesion strength between the interfaces of layers. - In the semiconductor device according to the first embodiment of the present invention, the
first fixing layer 8 is provided under thefirst semiconductor chip 14. Therefore, the misalignment can be suppressed when the firstlower joints intermediate joints upper joints base substrate 1 and thefirst substrate 10. The misalignment caused by the flowage of thefirst encapsulating layer 9 during assembling thefirst substrate 10 on thebase substrate 1 can also be suppressed. Accordingly, the semiconductor device according to the first embodiment can be assembled with high accuracy. - A method of assembling a semiconductor device according to the first embodiment of the present invention is described by using
FIGS. 2 and 3 . - The base substrate from a resin such, as glass epoxy, polyimide or the like is prepared. As shown in
FIG. 2 , the firstlower joints base substrate 1, respectively. The firstintermediate joints lower joints upper joints lower joints intermediate joints upper joints - The
first fixing layer 8 is positioned on the area of thebase substrate 1 where thefirst semiconductor chip 14 is mounted. As thefirst fixing layer 8, the resin sheet made from epoxy resin or acrylic resin may be suitable. Thefirst fixing layer 8 is patterned to have an outer contour aligned with a contour of thefirst semiconductor chip 14. - The
first substrate 10 having the via plugs 11 c, 11 m, . . . penetrating through the top and bottom surfaces of thefirst substrate 10 is prepared. Thefirst semiconductor chip 14 is mounted on the bottom surface of thefirst substrate 10 through the firstchip connection electrodes chip covering layer 12 is provided around the firstchip connection electrodes - As shown in
FIG. 3 , the bottom surface of thefirst substrate 10 is faced to thebase substrate 1. Thefirst semiconductor chip 14 is adhered to thefirst fixing layer 8. Thefirst semiconductor chip 14 is fixed on thebase substrate 1 by melting and curing thefirst fixing layer 8. Then, thebase substrate 1 and thefirst substrate 10 is connected by reflowing the firstlower joints intermediate joints upper joints substrate encapsulating layer 9 is filled around the firstlower joints intermediate joints upper joints substrate encapsulating layer 9 is cured and the semiconductor device. Then, the semiconductor device as shown inFIGS. 1A and 1B is manufactured. - Alternatively, when the reactive liquid resin with a solder fluxing function for soldering interconnect is used as the
first encapsulating layer 9, the firstlower joints intermediate joints upper joints - In accordance with the assembling method of the semiconductor device of the first embodiment, the
first semiconductor chip 14 is first fixed when assembling thefirst substrate 10 on thebase substrate 1. And then, thefirst semiconductor chip 14 provided between thebase substrate 1 and thefirst substrate 10 is encapsulated by use of thefirst encapsulating layer 9. Accordingly, the misalignment of thebase substrate 1 and thefirst substrate 10 caused by the flowage of thefirst encapsulating layer 9 is suppressed and the semiconductor device assembled with high accuracy will be manufactured. Moreover, since thefirst substrate 10 is mounted directly on the base substrate with the firstlower joints - As shown in
FIG. 4 , a semiconductor device according to a modification of the first embodiment differs from the semiconductor device as shown inFIGS. 1A and 1B in that first lower connection bumps 105 c, 105 m, first intermediate connection bumps 106 c, 106 m, and first upper connection bumps 107 c, 107 m are provided between thebase substrate 1 and thefirst substrate 10. - As the material of the first lower connection bumps 105 c, 105 m, the first intermediate connection bumps 106 c, 106 m, and the first upper connection bumps 107 c, 107 m, metallic stud bump electrode made of gold, or the like, may be suitable. The
base substrate 1 and thefirst substrate 10 are connected by applying physical oscillation, such as supersonic wave, to the first intermediate connection bumps 106 c, 106 m, and the first upper connection bumps 107 c, 107 m. - In accordance with the semiconductor device as shown in
FIG. 4 , the misalignment of thebase substrate 1 and thefirst substrate 10 caused by the flowage of thefirst encapsulating layer 9 is suppressed and the semiconductor device assembled with high accuracy will be manufactured. Moreover, since thefirst substrate 10 is mounted directly on the base substrate with the first lower connection bumps 105 c, 105 m, the intermediate layer, which connects upper and lower boards, is unnecessary. Accordingly, the manufacturing process will be simplified at a low cost. - As shown in
FIG. 5 , a semiconductor device according to a second embodiment of the present invention differs from the semiconductor device as shown inFIGS. 1A and 1B in that a plurality of semiconductor chips (asecond semiconductor chip 24, . . . , a k-th semiconductor chip 54) is stacked on thefirst substrate 10. - The
second semiconductor chip 24 is provided on thefirst substrate 10 through asecond fixing layer 28. As a material of thesecond fixing layer 8, a synthetic resin sheet made of epoxy resin or acrylic resin may be used. Thesecond semiconductor chip 24 is connected to wirings (not shown) provided on a bottom surface of thesecond substrate 20 through secondchip connection electrodes semiconductor chip 24. - A plurality of via
plugs second substrate 20. The via plugs 21 c, 21 m, . . . penetrate through the top surface and bottom surface of thesecond substrate 10. A plurality of second connection members (secondlower joints intermediate joints upper joints - The
first substrate 10 and thesecond substrate 20 are electrically connected by the secondlower joints intermediate joints upper joints second encapsulating layer 29 is provided around the secondlower joints intermediate joints upper joints second encapsulating layer 29, a synthetic liquid resin made from epoxy resin or acrylic resin may be suitable. - The k-
th semiconductor chip 54 is fixed on a k-1 thesubstrate 40, which is provided above thesecond substrate 20, through a k-th fixing layer 48. The k-th semiconductor chip 54 is connected to wirings (not shown) provided on a bottom surface of the k-th substrate 50, which is the uppermost substrate of the semiconductor device as shown inFIG. 5 , through k-thchip connection electrodes th semiconductor chip 54. A k-thchip covering layer 52 is provided around the k-thchip connection electrodes - A plurality of via
plugs th substrate 50. The via plugs 51 c, 51 m penetrates through the top surface and bottom surface of k-th substrate 50. A plurality of second connection members (k-thlower joints intermediate joints upper joints plugs 1th substrate 40. - In the semiconductor device according to the second embodiment of the present invention, the first to k-
th fixing layer base substrate 1, and the first to k-1th substrate 10, . . . , 40, respectively. Since each of the first to k-th semiconductor chips th fixing layer th encapsulating layers th encapsulating layers - A method of assembling a semiconductor device according to the second embodiment of the present invention is described by using
FIGS. 2, 6 and 7. - The base substrate from a resin such, as glass epoxy, polyimide or the like is prepared. As shown in
FIG. 2 , the firstlower joints base substrate 1. The firstintermediate joints lower joints upper joints intermediate joints lower joints intermediate joints upper joints - The
first fixing layer 8 is positioned on the area opposing to thefirst semiconductor chip 14 on thebase substrate 1. Thefirst substrate 10 having thefirst semiconductor chip 14 on the bottom surface is prepared and the bottom surface of thefirst substrate 10 is faced to thebase substrate 1. Thefirst semiconductor chip 14 is adhered to thefirst fixing layer 8. Thefirst semiconductor chip 14 is fixed on thebase substrate 1 by melting and curing thefirst fixing layer 8. - As shown in
FIG. 6 ,second fixing layer 28 is positioned on the area opposing to thesecond semiconductor chip 24 on thefirst substrate 10. Thesecond fixing layer 28 is patterned to have an outer contour aligned with a contour of thesecond semiconductor chip 24. As thesecond fixing layer 28, a synthetic resin sheet made of epoxy resin or acrylic resin may be suitable. Thesecond substrate 20 having thesecond semiconductor chip 24 on the bottom surface is faced to thebase substrate 1. Thesecond semiconductor chip 24 is adhered to thesecond fixing layer 28. Thefirst semiconductor chip 24 is fixed on thefirst substrate 10 by melting and curing thesecond fixing layer 28. - A desired amount of the substrates are stacked on the
second substrate 20. Finally, as shown inFIG. 7 , the k-th fixing layer 48 is provided on the top surface of the k-1 the substrate40. The k-th substrate 50, which is the uppermost substrate of the semiconductor device inFIG. 5 , is faced to the k-th fixing layer 48. The bottom surface of the k-th semiconductor chip 54 is adhered to the k-th fixatiom layer 48. The k-th semiconductor chip 54 is fixed on the k-1th substrate 40 by melting and curing the k-thefixing layer 48. - The
base substrate 1 and thefirst substrate 10 is connected by reflowing the firstlower joints intermediate joints upper joints first substrate 10 and thesecond substrate 20 is connected by reflowing the secondlower joints intermediate joints upper joints second substrate 20 are connected by reflowing, and finally, the k-1 thesubstrate 40 and the k-th substrate 50 are connected by reflowing the k-thlower joints intermediate joints upper joints substrate encapsulating layer 29 is filled around the secondlower joints intermediate joints upper joints substrate encapsulating layer 59 is filled around the k-thlower joints intermediate joints upper joints FIG. 5 is manufactured. - In accordance with the assembling method of the semiconductor device of the second embodiment, the first to k-
th semiconductor chips base substrate 1 and the first to k-th substrates th semiconductor chips th encapsulating layers base substrate 1, the first to k-th substrates th encapsulating layers th substrates base substrate 1 with the first to k-thelower joints - Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.
- In the first and second embodiments of the present invention, synthetic resins such as polyimide resin, phonolic resin can be used as the material of the encapsulating resin layers in place of the epoxy resin and the acrylic resin. As the
first fixing layer 8, the firstchip covering layer 12, and the firstchip covering layer 9, a plurality of resins having various curing temperatures, curing times, viscosities can be used. - As shown in
FIGS. 1A and 1B , thebase substrate 1 and thefirst substrate 10 are connected with the three connection members (the firstlower joints intermediate joints upper joints -
FIG. 2 shows an assembling example, which provides the first connection members (thelower joints intermediate joints upper joints base substrate 1. However, the first connection members can be stacked on predetermined area on thefirst substrate 10.
Claims (11)
1-10. (canceled)
11. A method of assembling a semiconductor device comprising:
providing a first fixing layer on a base substrate;
facing a first substrate to the base substrate, the first substrate attaching a first semiconductor chip under a bottom surface of the first substrate;
fixing the first semiconductor chip to the first fixing layer;
providing a plurality of first connection members between the first substrate and the base substrate so as to connect the first substrate and the base substrate; and
providing a first substrate encapsulating layer around the first connection members.
12. The method of claim 11 , wherein the first fixing layer is made one of epoxy resin and acrylic resin.
13. The method of claim 11 , wherein an outer contour of the first fixing layer is aligned with a contour of the first semiconductor chip.
14. The method of claim 11 , wherein the first fixing layer is a resin sheet.
15. The method of claim 11 , wherein the first encapsulating layer is made one of epoxy resin and acrylic resin.
16. The method of claim 11 , wherein the first encapsulating layer is a liquid resin.
17. The method of claim 11 , wherein the first connection members surround the first semiconductor chip.
18. The method of claim 11 , wherein the first connection members are made from a material selected from a group consisting of Pb, Sn—Cu, Sn—Ag, Sn—Ag—Cu, and Sn—Sb.
19. The method of claim 11 , wherein the first connection members comprise bump electrodes made of gold.
20. The method of claim 11 , further comprising:
providing a second fixing layer on the first substrate;
facing a second substrate to the first substrate, the second substrate attaching a second semiconductor chip under a bottom surface of the second substrate;
fixing the second semiconductor chip to the second fixing layer;
providing a plurality of second connection members between the first substrate and the second substrate so as to connect the first substrate to the second substrate; and
providing a second encapsulating layer around the second connection members.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/826,858 US20070292989A1 (en) | 2004-10-13 | 2007-07-19 | Semiconductor device and a method of assembling a semiconductor device |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004298740A JP2006114604A (en) | 2004-10-13 | 2004-10-13 | Semiconductor device and assembly method thereof |
JPP2004-298740 | 2004-10-13 | ||
US11/246,150 US7276784B2 (en) | 2004-10-13 | 2005-10-11 | Semiconductor device and a method of assembling a semiconductor device |
US11/826,858 US20070292989A1 (en) | 2004-10-13 | 2007-07-19 | Semiconductor device and a method of assembling a semiconductor device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/246,150 Division US7276784B2 (en) | 2004-10-13 | 2005-10-11 | Semiconductor device and a method of assembling a semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
US20070292989A1 true US20070292989A1 (en) | 2007-12-20 |
Family
ID=36145871
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/246,150 Expired - Fee Related US7276784B2 (en) | 2004-10-13 | 2005-10-11 | Semiconductor device and a method of assembling a semiconductor device |
US11/826,858 Abandoned US20070292989A1 (en) | 2004-10-13 | 2007-07-19 | Semiconductor device and a method of assembling a semiconductor device |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/246,150 Expired - Fee Related US7276784B2 (en) | 2004-10-13 | 2005-10-11 | Semiconductor device and a method of assembling a semiconductor device |
Country Status (5)
Country | Link |
---|---|
US (2) | US7276784B2 (en) |
JP (1) | JP2006114604A (en) |
KR (1) | KR100730255B1 (en) |
CN (1) | CN1763942A (en) |
TW (1) | TWI294657B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070187827A1 (en) * | 2005-10-27 | 2007-08-16 | Jong-Ung Lee | Semiconductor package, stack package using the same package and method of fabricating the same |
US20080315415A1 (en) * | 2007-06-22 | 2008-12-25 | Oki Electric Industry Co., Ltd. | Semiconductor device and manufacturing method thereof |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006114604A (en) * | 2004-10-13 | 2006-04-27 | Toshiba Corp | Semiconductor device and assembly method thereof |
US7659623B2 (en) * | 2005-04-11 | 2010-02-09 | Elpida Memory, Inc. | Semiconductor device having improved wiring |
US7545031B2 (en) * | 2005-04-11 | 2009-06-09 | Stats Chippac Ltd. | Multipackage module having stacked packages with asymmetrically arranged die and molding |
US7919844B2 (en) | 2005-05-26 | 2011-04-05 | Aprolase Development Co., Llc | Tier structure with tier frame having a feedthrough structure |
US7768113B2 (en) * | 2005-05-26 | 2010-08-03 | Volkan Ozguz | Stackable tier structure comprising prefabricated high density feedthrough |
JP5116268B2 (en) * | 2005-08-31 | 2013-01-09 | キヤノン株式会社 | Multilayer semiconductor device and manufacturing method thereof |
JP4528715B2 (en) * | 2005-11-25 | 2010-08-18 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
US20070202680A1 (en) * | 2006-02-28 | 2007-08-30 | Aminuddin Ismail | Semiconductor packaging method |
DE102006037538B4 (en) * | 2006-08-10 | 2016-03-10 | Infineon Technologies Ag | Electronic component, electronic component stack and method for their production and use of a bead placement machine for carrying out a method for producing an electronic component or component stack |
US7608921B2 (en) * | 2006-12-07 | 2009-10-27 | Stats Chippac, Inc. | Multi-layer semiconductor package |
FR2939963B1 (en) * | 2008-12-11 | 2011-08-05 | St Microelectronics Grenoble | METHOD FOR MANUFACTURING SEMICONDUCTOR COMPONENT CARRIER, SUPPORT AND SEMICONDUCTOR DEVICE |
JP5789431B2 (en) * | 2011-06-30 | 2015-10-07 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
JP2012134572A (en) * | 2012-04-12 | 2012-07-12 | Lapis Semiconductor Co Ltd | Semiconductor device |
US9455353B2 (en) * | 2012-07-31 | 2016-09-27 | Robert Bosch Gmbh | Substrate with multiple encapsulated devices |
TWI550736B (en) * | 2013-07-15 | 2016-09-21 | 英帆薩斯公司 | Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation |
JP2020145351A (en) * | 2019-03-07 | 2020-09-10 | キオクシア株式会社 | Semiconductor device and manufacturing method thereof |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6025648A (en) * | 1997-04-17 | 2000-02-15 | Nec Corporation | Shock resistant semiconductor device and method for producing same |
US6313522B1 (en) * | 1998-08-28 | 2001-11-06 | Micron Technology, Inc. | Semiconductor structure having stacked semiconductor devices |
US6451624B1 (en) * | 1998-06-05 | 2002-09-17 | Micron Technology, Inc. | Stackable semiconductor package having conductive layer and insulating layers and method of fabrication |
US6469374B1 (en) * | 1999-08-26 | 2002-10-22 | Kabushiki Kaisha Toshiba | Superposed printed substrates and insulating substrates having semiconductor elements inside |
US6686222B2 (en) * | 2001-05-18 | 2004-02-03 | Kabushiki Kaisha Toshiba | Stacked semiconductor device manufacturing method |
US7276784B2 (en) * | 2004-10-13 | 2007-10-02 | Kabushiki Kaisha Toshiba | Semiconductor device and a method of assembling a semiconductor device |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11103158A (en) | 1997-09-26 | 1999-04-13 | Olympus Optical Co Ltd | Flip-chip mounting to printed wiring board and mounting structure |
JP2000286380A (en) | 1999-03-30 | 2000-10-13 | Nec Corp | Packaging structure and manufacture of semiconductor |
JP2003007972A (en) | 2001-06-27 | 2003-01-10 | Toshiba Corp | Laminated semiconductor device and method of manufacturing the same |
JP2004047702A (en) | 2002-07-11 | 2004-02-12 | Toshiba Corp | Semiconductor device laminated module |
-
2004
- 2004-10-13 JP JP2004298740A patent/JP2006114604A/en active Pending
-
2005
- 2005-10-06 TW TW094134980A patent/TWI294657B/en not_active IP Right Cessation
- 2005-10-11 US US11/246,150 patent/US7276784B2/en not_active Expired - Fee Related
- 2005-10-12 KR KR1020050095935A patent/KR100730255B1/en not_active IP Right Cessation
- 2005-10-13 CN CNA2005101083905A patent/CN1763942A/en active Pending
-
2007
- 2007-07-19 US US11/826,858 patent/US20070292989A1/en not_active Abandoned
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6025648A (en) * | 1997-04-17 | 2000-02-15 | Nec Corporation | Shock resistant semiconductor device and method for producing same |
US6287892B1 (en) * | 1997-04-17 | 2001-09-11 | Nec Corporation | Shock-resistant semiconductor device and method for producing same |
US6451624B1 (en) * | 1998-06-05 | 2002-09-17 | Micron Technology, Inc. | Stackable semiconductor package having conductive layer and insulating layers and method of fabrication |
US6313522B1 (en) * | 1998-08-28 | 2001-11-06 | Micron Technology, Inc. | Semiconductor structure having stacked semiconductor devices |
US6469374B1 (en) * | 1999-08-26 | 2002-10-22 | Kabushiki Kaisha Toshiba | Superposed printed substrates and insulating substrates having semiconductor elements inside |
US6686222B2 (en) * | 2001-05-18 | 2004-02-03 | Kabushiki Kaisha Toshiba | Stacked semiconductor device manufacturing method |
US7276784B2 (en) * | 2004-10-13 | 2007-10-02 | Kabushiki Kaisha Toshiba | Semiconductor device and a method of assembling a semiconductor device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070187827A1 (en) * | 2005-10-27 | 2007-08-16 | Jong-Ung Lee | Semiconductor package, stack package using the same package and method of fabricating the same |
US20080315415A1 (en) * | 2007-06-22 | 2008-12-25 | Oki Electric Industry Co., Ltd. | Semiconductor device and manufacturing method thereof |
US8659151B2 (en) * | 2007-06-22 | 2014-02-25 | Lapis Semiconductor Co., Ltd. | Semiconductor device and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
KR100730255B1 (en) | 2007-06-20 |
TW200620511A (en) | 2006-06-16 |
US20060079020A1 (en) | 2006-04-13 |
JP2006114604A (en) | 2006-04-27 |
KR20060052210A (en) | 2006-05-19 |
TWI294657B (en) | 2008-03-11 |
US7276784B2 (en) | 2007-10-02 |
CN1763942A (en) | 2006-04-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7276784B2 (en) | Semiconductor device and a method of assembling a semiconductor device | |
US6297141B1 (en) | Mounting assembly of integrated circuit device and method for production thereof | |
US6025648A (en) | Shock resistant semiconductor device and method for producing same | |
US6621172B2 (en) | Semiconductor device and method of fabricating the same, circuit board, and electronic equipment | |
US7148560B2 (en) | IC chip package structure and underfill process | |
US6228676B1 (en) | Near chip size integrated circuit package | |
US6555917B1 (en) | Semiconductor package having stacked semiconductor chips and method of making the same | |
US7294928B2 (en) | Components, methods and assemblies for stacked packages | |
US6514792B2 (en) | Mechanically-stabilized area-array device package | |
US7344916B2 (en) | Package for a semiconductor device | |
US20180240789A1 (en) | Stackable electronic package and method of fabricating same | |
US7420814B2 (en) | Package stack and manufacturing method thereof | |
US20080029884A1 (en) | Multichip device and method for producing a multichip device | |
US20120267782A1 (en) | Package-on-package semiconductor device | |
US20180145015A1 (en) | Method of fabricating packaging layer of fan-out chip package | |
US6448110B1 (en) | Method for fabricating a dual-chip package and package formed | |
US6815830B2 (en) | Semiconductor device and method of manufacturing the same, circuit board and electronic instrument | |
KR100838352B1 (en) | Carrying structure of electronic components | |
US6806119B2 (en) | Method of balanced coefficient of thermal expansion for flip chip ball grid array | |
US20060220245A1 (en) | Flip chip package and the fabrication thereof | |
US6812567B2 (en) | Semiconductor package and package stack made thereof | |
CN110634880A (en) | Semiconductor device and method for manufacturing the same | |
WO2004018719A1 (en) | Negative volume expansion lead-free electrical connection | |
JP2000058716A (en) | Semiconductor device | |
KR101472901B1 (en) | Wafer level chip scale package including redistribution substrate and method of fabricating the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |